win-pvdrivers

view common/include/public/hvm/save.h @ 62:edd4a2ad5b44

Removed old inf files
author James Harper <james.harper@bendigoit.com.au>
date Wed Dec 19 10:22:50 2007 +1100 (2007-12-19)
parents 5712dede5a1b
children
line source
1 /*
2 * hvm/save.h
3 *
4 * Structure definitions for HVM state that is held by Xen and must
5 * be saved along with the domain's memory and device-model state.
6 *
7 *
8 * Copyright (c) 2007 XenSource Ltd.
9 *
10 * Permission is hereby granted, free of charge, to any person obtaining a copy
11 * of this software and associated documentation files (the "Software"), to
12 * deal in the Software without restriction, including without limitation the
13 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
14 * sell copies of the Software, and to permit persons to whom the Software is
15 * furnished to do so, subject to the following conditions:
16 *
17 * The above copyright notice and this permission notice shall be included in
18 * all copies or substantial portions of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
23 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
25 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
27 */
29 #ifndef __XEN_PUBLIC_HVM_SAVE_H__
30 #define __XEN_PUBLIC_HVM_SAVE_H__
32 /*
33 * Structures in this header *must* have the same layout in 32bit
34 * and 64bit environments: this means that all fields must be explicitly
35 * sized types and aligned to their sizes, and the structs must be
36 * a multiple of eight bytes long.
37 *
38 * Only the state necessary for saving and restoring (i.e. fields
39 * that are analogous to actual hardware state) should go in this file.
40 * Internal mechanisms should be kept in Xen-private headers.
41 */
43 /*
44 * Each entry is preceded by a descriptor giving its type and length
45 */
46 struct hvm_save_descriptor {
47 uint16_t typecode; /* Used to demux the various types below */
48 uint16_t instance; /* Further demux within a type */
49 uint32_t length; /* In bytes, *not* including this descriptor */
50 };
53 /*
54 * Each entry has a datatype associated with it: for example, the CPU state
55 * is saved as a HVM_SAVE_TYPE(CPU), which has HVM_SAVE_LENGTH(CPU),
56 * and is identified by a descriptor with typecode HVM_SAVE_CODE(CPU).
57 * DECLARE_HVM_SAVE_TYPE binds these things together with some type-system
58 * ugliness.
59 */
61 #define DECLARE_HVM_SAVE_TYPE(_x, _code, _type) \
62 struct __HVM_SAVE_TYPE_##_x { _type t; char c[_code]; }
64 #define HVM_SAVE_TYPE(_x) typeof (((struct __HVM_SAVE_TYPE_##_x *)(0))->t)
65 #define HVM_SAVE_LENGTH(_x) (sizeof (HVM_SAVE_TYPE(_x)))
66 #define HVM_SAVE_CODE(_x) (sizeof (((struct __HVM_SAVE_TYPE_##_x *)(0))->c))
69 /*
70 * Save/restore header: general info about the save file.
71 */
73 #define HVM_FILE_MAGIC 0x54381286
74 #define HVM_FILE_VERSION 0x00000001
76 struct hvm_save_header {
77 uint32_t magic; /* Must be HVM_FILE_MAGIC */
78 uint32_t version; /* File format version */
79 uint64_t changeset; /* Version of Xen that saved this file */
80 uint32_t cpuid; /* CPUID[0x01][%eax] on the saving machine */
81 uint32_t pad0;
82 };
84 DECLARE_HVM_SAVE_TYPE(HEADER, 1, struct hvm_save_header);
87 /*
88 * Processor
89 */
91 struct hvm_hw_cpu {
92 uint8_t fpu_regs[512];
94 uint64_t rax;
95 uint64_t rbx;
96 uint64_t rcx;
97 uint64_t rdx;
98 uint64_t rbp;
99 uint64_t rsi;
100 uint64_t rdi;
101 uint64_t rsp;
102 uint64_t r8;
103 uint64_t r9;
104 uint64_t r10;
105 uint64_t r11;
106 uint64_t r12;
107 uint64_t r13;
108 uint64_t r14;
109 uint64_t r15;
111 uint64_t rip;
112 uint64_t rflags;
114 uint64_t cr0;
115 uint64_t cr2;
116 uint64_t cr3;
117 uint64_t cr4;
119 uint64_t dr0;
120 uint64_t dr1;
121 uint64_t dr2;
122 uint64_t dr3;
123 uint64_t dr6;
124 uint64_t dr7;
126 uint32_t cs_sel;
127 uint32_t ds_sel;
128 uint32_t es_sel;
129 uint32_t fs_sel;
130 uint32_t gs_sel;
131 uint32_t ss_sel;
132 uint32_t tr_sel;
133 uint32_t ldtr_sel;
135 uint32_t cs_limit;
136 uint32_t ds_limit;
137 uint32_t es_limit;
138 uint32_t fs_limit;
139 uint32_t gs_limit;
140 uint32_t ss_limit;
141 uint32_t tr_limit;
142 uint32_t ldtr_limit;
143 uint32_t idtr_limit;
144 uint32_t gdtr_limit;
146 uint64_t cs_base;
147 uint64_t ds_base;
148 uint64_t es_base;
149 uint64_t fs_base;
150 uint64_t gs_base;
151 uint64_t ss_base;
152 uint64_t tr_base;
153 uint64_t ldtr_base;
154 uint64_t idtr_base;
155 uint64_t gdtr_base;
157 uint32_t cs_arbytes;
158 uint32_t ds_arbytes;
159 uint32_t es_arbytes;
160 uint32_t fs_arbytes;
161 uint32_t gs_arbytes;
162 uint32_t ss_arbytes;
163 uint32_t tr_arbytes;
164 uint32_t ldtr_arbytes;
166 uint32_t sysenter_cs;
167 uint32_t padding0;
169 uint64_t sysenter_esp;
170 uint64_t sysenter_eip;
172 /* msr for em64t */
173 uint64_t shadow_gs;
175 /* msr content saved/restored. */
176 uint64_t msr_flags;
177 uint64_t msr_lstar;
178 uint64_t msr_star;
179 uint64_t msr_cstar;
180 uint64_t msr_syscall_mask;
181 uint64_t msr_efer;
183 /* guest's idea of what rdtsc() would return */
184 uint64_t tsc;
186 /* pending event, if any */
187 union {
188 uint32_t pending_event;
189 struct {
190 uint8_t pending_vector:8;
191 uint8_t pending_type:3;
192 uint8_t pending_error_valid:1;
193 uint32_t pending_reserved:19;
194 uint8_t pending_valid:1;
195 };
196 };
197 /* error code for pending event */
198 uint32_t error_code;
199 };
201 DECLARE_HVM_SAVE_TYPE(CPU, 2, struct hvm_hw_cpu);
204 /*
205 * PIC
206 */
208 struct hvm_hw_vpic {
209 /* IR line bitmasks. */
210 uint8_t irr;
211 uint8_t imr;
212 uint8_t isr;
214 /* Line IRx maps to IRQ irq_base+x */
215 uint8_t irq_base;
217 /*
218 * Where are we in ICW2-4 initialisation (0 means no init in progress)?
219 * Bits 0-1 (=x): Next write at A=1 sets ICW(x+1).
220 * Bit 2: ICW1.IC4 (1 == ICW4 included in init sequence)
221 * Bit 3: ICW1.SNGL (0 == ICW3 included in init sequence)
222 */
223 uint8_t init_state:4;
225 /* IR line with highest priority. */
226 uint8_t priority_add:4;
228 /* Reads from A=0 obtain ISR or IRR? */
229 uint8_t readsel_isr:1;
231 /* Reads perform a polling read? */
232 uint8_t poll:1;
234 /* Automatically clear IRQs from the ISR during INTA? */
235 uint8_t auto_eoi:1;
237 /* Automatically rotate IRQ priorities during AEOI? */
238 uint8_t rotate_on_auto_eoi:1;
240 /* Exclude slave inputs when considering in-service IRQs? */
241 uint8_t special_fully_nested_mode:1;
243 /* Special mask mode excludes masked IRs from AEOI and priority checks. */
244 uint8_t special_mask_mode:1;
246 /* Is this a master PIC or slave PIC? (NB. This is not programmable.) */
247 uint8_t is_master:1;
249 /* Edge/trigger selection. */
250 uint8_t elcr;
252 /* Virtual INT output. */
253 uint8_t int_output;
254 };
256 DECLARE_HVM_SAVE_TYPE(PIC, 3, struct hvm_hw_vpic);
259 /*
260 * IO-APIC
261 */
263 #ifdef __ia64__
264 #define VIOAPIC_IS_IOSAPIC 1
265 #define VIOAPIC_NUM_PINS 24
266 #else
267 #define VIOAPIC_NUM_PINS 48 /* 16 ISA IRQs, 32 non-legacy PCI IRQS. */
268 #endif
270 struct hvm_hw_vioapic {
271 uint64_t base_address;
272 uint32_t ioregsel;
273 uint32_t id;
274 union vioapic_redir_entry
275 {
276 uint64_t bits;
277 struct {
278 uint8_t vector;
279 uint8_t delivery_mode:3;
280 uint8_t dest_mode:1;
281 uint8_t delivery_status:1;
282 uint8_t polarity:1;
283 uint8_t remote_irr:1;
284 uint8_t trig_mode:1;
285 uint8_t mask:1;
286 uint8_t reserve:7;
287 #if !VIOAPIC_IS_IOSAPIC
288 uint8_t reserved[4];
289 uint8_t dest_id;
290 #else
291 uint8_t reserved[3];
292 uint16_t dest_id;
293 #endif
294 } fields;
295 } redirtbl[VIOAPIC_NUM_PINS];
296 };
298 DECLARE_HVM_SAVE_TYPE(IOAPIC, 4, struct hvm_hw_vioapic);
301 /*
302 * LAPIC
303 */
305 struct hvm_hw_lapic {
306 uint64_t apic_base_msr;
307 uint32_t disabled; /* VLAPIC_xx_DISABLED */
308 uint32_t timer_divisor;
309 };
311 DECLARE_HVM_SAVE_TYPE(LAPIC, 5, struct hvm_hw_lapic);
313 struct hvm_hw_lapic_regs {
314 /* A 4k page of register state */
315 uint8_t data[0x400];
316 };
318 DECLARE_HVM_SAVE_TYPE(LAPIC_REGS, 6, struct hvm_hw_lapic_regs);
321 /*
322 * IRQs
323 */
325 struct hvm_hw_pci_irqs {
326 /*
327 * Virtual interrupt wires for a single PCI bus.
328 * Indexed by: device*4 + INTx#.
329 */
330 union {
331 DECLARE_BITMAP(i, 32*4);
332 uint64_t pad[2];
333 };
334 };
336 DECLARE_HVM_SAVE_TYPE(PCI_IRQ, 7, struct hvm_hw_pci_irqs);
338 struct hvm_hw_isa_irqs {
339 /*
340 * Virtual interrupt wires for ISA devices.
341 * Indexed by ISA IRQ (assumes no ISA-device IRQ sharing).
342 */
343 union {
344 DECLARE_BITMAP(i, 16);
345 uint64_t pad[1];
346 };
347 };
349 DECLARE_HVM_SAVE_TYPE(ISA_IRQ, 8, struct hvm_hw_isa_irqs);
351 struct hvm_hw_pci_link {
352 /*
353 * PCI-ISA interrupt router.
354 * Each PCI <device:INTx#> is 'wire-ORed' into one of four links using
355 * the traditional 'barber's pole' mapping ((device + INTx#) & 3).
356 * The router provides a programmable mapping from each link to a GSI.
357 */
358 uint8_t route[4];
359 uint8_t pad0[4];
360 };
362 DECLARE_HVM_SAVE_TYPE(PCI_LINK, 9, struct hvm_hw_pci_link);
364 /*
365 * PIT
366 */
368 struct hvm_hw_pit {
369 struct hvm_hw_pit_channel {
370 uint32_t count; /* can be 65536 */
371 uint16_t latched_count;
372 uint8_t count_latched;
373 uint8_t status_latched;
374 uint8_t status;
375 uint8_t read_state;
376 uint8_t write_state;
377 uint8_t write_latch;
378 uint8_t rw_mode;
379 uint8_t mode;
380 uint8_t bcd; /* not supported */
381 uint8_t gate; /* timer start */
382 } channels[3]; /* 3 x 16 bytes */
383 uint32_t speaker_data_on;
384 uint32_t pad0;
385 };
387 DECLARE_HVM_SAVE_TYPE(PIT, 10, struct hvm_hw_pit);
390 /*
391 * RTC
392 */
394 #define RTC_CMOS_SIZE 14
395 struct hvm_hw_rtc {
396 /* CMOS bytes */
397 uint8_t cmos_data[RTC_CMOS_SIZE];
398 /* Index register for 2-part operations */
399 uint8_t cmos_index;
400 uint8_t pad0;
401 };
403 DECLARE_HVM_SAVE_TYPE(RTC, 11, struct hvm_hw_rtc);
406 /*
407 * HPET
408 */
410 #define HPET_TIMER_NUM 3 /* 3 timers supported now */
411 struct hvm_hw_hpet {
412 /* Memory-mapped, software visible registers */
413 uint64_t capability; /* capabilities */
414 uint64_t res0; /* reserved */
415 uint64_t config; /* configuration */
416 uint64_t res1; /* reserved */
417 uint64_t isr; /* interrupt status reg */
418 uint64_t res2[25]; /* reserved */
419 uint64_t mc64; /* main counter */
420 uint64_t res3; /* reserved */
421 struct { /* timers */
422 uint64_t config; /* configuration/cap */
423 uint64_t cmp; /* comparator */
424 uint64_t fsb; /* FSB route, not supported now */
425 uint64_t res4; /* reserved */
426 } timers[HPET_TIMER_NUM];
427 uint64_t res5[4*(24-HPET_TIMER_NUM)]; /* reserved, up to 0x3ff */
429 /* Hidden register state */
430 uint64_t period[HPET_TIMER_NUM]; /* Last value written to comparator */
431 };
433 DECLARE_HVM_SAVE_TYPE(HPET, 12, struct hvm_hw_hpet);
436 /*
437 * PM timer
438 */
440 struct hvm_hw_pmtimer {
441 uint32_t tmr_val; /* PM_TMR_BLK.TMR_VAL: 32bit free-running counter */
442 uint16_t pm1a_sts; /* PM1a_EVT_BLK.PM1a_STS: status register */
443 uint16_t pm1a_en; /* PM1a_EVT_BLK.PM1a_EN: enable register */
444 };
446 DECLARE_HVM_SAVE_TYPE(PMTIMER, 13, struct hvm_hw_pmtimer);
448 /*
449 * Largest type-code in use
450 */
451 #define HVM_SAVE_CODE_MAX 13
454 /*
455 * The series of save records is teminated by a zero-type, zero-length
456 * descriptor.
457 */
459 struct hvm_save_end {};
460 DECLARE_HVM_SAVE_TYPE(END, 0, struct hvm_save_end);
462 #endif /* __XEN_PUBLIC_HVM_SAVE_H__ */