1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/xen/arch/ia64/linux-xen/sn/Makefile	Wed Dec 13 11:08:40 2006 -0700
     1.3 @@ -0,0 +1,1 @@
     1.4 +subdir-y += kernel

     2.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     2.2 +++ b/xen/arch/ia64/linux-xen/sn/kernel/Makefile	Wed Dec 13 11:08:40 2006 -0700
     2.3 @@ -0,0 +1,5 @@
     2.4 +obj-y += sn2_smp.o
     2.5 +obj-y += setup.o
     2.6 +obj-y += iomv.o
     2.7 +obj-y += irq.o
     2.8 +obj-y += io_init.o

     3.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     3.2 +++ b/xen/arch/ia64/linux-xen/sn/kernel/README.origin	Wed Dec 13 11:08:40 2006 -0700
     3.3 @@ -0,0 +1,12 @@
     3.4 +# Source files in this directory are near-identical copies of linux-2.6.19
     3.5 +# files:
     3.6 +
     3.7 +# NOTE: ALL changes to these files should be clearly marked
     3.8 +# (e.g. with #ifdef XEN or XEN in a comment) so that they can be
     3.9 +# easily updated to future versions of the corresponding Linux files.
    3.10 +
    3.11 +io_init.c		-> linux/arch/ia64/sn/kernel/io_init.c
    3.12 +iomv.c			-> linux/arch/ia64/sn/kernel/iomv.c
    3.13 +irq.c			-> linux/arch/ia64/sn/kernel/irq.c
    3.14 +setup.c			-> linux/arch/ia64/sn/kernel/setup.c
    3.15 +sn2_smp.c		-> linux/arch/ia64/sn/kernel/sn2/sn2_smp.c

     4.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     4.2 +++ b/xen/arch/ia64/linux-xen/sn/kernel/io_init.c	Wed Dec 13 11:08:40 2006 -0700
     4.3 @@ -0,0 +1,740 @@
     4.4 +/*
     4.5 + * This file is subject to the terms and conditions of the GNU General Public
     4.6 + * License.  See the file "COPYING" in the main directory of this archive
     4.7 + * for more details.
     4.8 + *
     4.9 + * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
    4.10 + */
    4.11 +
    4.12 +#include <linux/bootmem.h>
    4.13 +#include <linux/nodemask.h>
    4.14 +#include <asm/sn/types.h>
    4.15 +#include <asm/sn/addrs.h>
    4.16 +#include <asm/sn/sn_feature_sets.h>
    4.17 +#include <asm/sn/geo.h>
    4.18 +#include <asm/sn/io.h>
    4.19 +#include <asm/sn/l1.h>
    4.20 +#include <asm/sn/module.h>
    4.21 +#include <asm/sn/pcibr_provider.h>
    4.22 +#include <asm/sn/pcibus_provider_defs.h>
    4.23 +#include <asm/sn/pcidev.h>
    4.24 +#include <asm/sn/simulator.h>
    4.25 +#include <asm/sn/sn_sal.h>
    4.26 +#include <asm/sn/tioca_provider.h>
    4.27 +#include <asm/sn/tioce_provider.h>
    4.28 +#include "xtalk/hubdev.h"
    4.29 +#include "xtalk/xwidgetdev.h"
    4.30 +
    4.31 +
    4.32 +extern void sn_init_cpei_timer(void);
    4.33 +extern void register_sn_procfs(void);
    4.34 +
    4.35 +static struct list_head sn_sysdata_list;
    4.36 +
    4.37 +/* sysdata list struct */
    4.38 +struct sysdata_el {
    4.39 +	struct list_head entry;
    4.40 +	void *sysdata;
    4.41 +};
    4.42 +
    4.43 +struct slab_info {
    4.44 +	struct hubdev_info hubdev;
    4.45 +};
    4.46 +
    4.47 +struct brick {
    4.48 +	moduleid_t id;		/* Module ID of this module        */
    4.49 +	struct slab_info slab_info[MAX_SLABS + 1];
    4.50 +};
    4.51 +
    4.52 +int sn_ioif_inited;		/* SN I/O infrastructure initialized? */
    4.53 +
    4.54 +struct sn_pcibus_provider *sn_pci_provider[PCIIO_ASIC_MAX_TYPES];	/* indexed by asic type */
    4.55 +
    4.56 +static int max_segment_number;		 /* Default highest segment number */
    4.57 +static int max_pcibus_number = 255;	/* Default highest pci bus number */
    4.58 +
    4.59 +/*
    4.60 + * Hooks and struct for unsupported pci providers
    4.61 + */
    4.62 +
    4.63 +static dma_addr_t
    4.64 +sn_default_pci_map(struct pci_dev *pdev, unsigned long paddr, size_t size, int type)
    4.65 +{
    4.66 +	return 0;
    4.67 +}
    4.68 +
    4.69 +static void
    4.70 +sn_default_pci_unmap(struct pci_dev *pdev, dma_addr_t addr, int direction)
    4.71 +{
    4.72 +	return;
    4.73 +}
    4.74 +
    4.75 +static void *
    4.76 +sn_default_pci_bus_fixup(struct pcibus_bussoft *soft, struct pci_controller *controller)
    4.77 +{
    4.78 +	return NULL;
    4.79 +}
    4.80 +
    4.81 +static struct sn_pcibus_provider sn_pci_default_provider = {
    4.82 +	.dma_map = sn_default_pci_map,
    4.83 +	.dma_map_consistent = sn_default_pci_map,
    4.84 +	.dma_unmap = sn_default_pci_unmap,
    4.85 +	.bus_fixup = sn_default_pci_bus_fixup,
    4.86 +};
    4.87 +
    4.88 +/*
    4.89 + * Retrieve the DMA Flush List given nasid, widget, and device.
    4.90 + * This list is needed to implement the WAR - Flush DMA data on PIO Reads.
    4.91 + */
    4.92 +static inline u64
    4.93 +sal_get_device_dmaflush_list(u64 nasid, u64 widget_num, u64 device_num,
    4.94 +			     u64 address)
    4.95 +{
    4.96 +	struct ia64_sal_retval ret_stuff;
    4.97 +	ret_stuff.status = 0;
    4.98 +	ret_stuff.v0 = 0;
    4.99 +
   4.100 +	SAL_CALL_NOLOCK(ret_stuff,
   4.101 +			(u64) SN_SAL_IOIF_GET_DEVICE_DMAFLUSH_LIST,
   4.102 +			(u64) nasid, (u64) widget_num,
   4.103 +			(u64) device_num, (u64) address, 0, 0, 0);
   4.104 +	return ret_stuff.status;
   4.105 +}
   4.106 +
   4.107 +/*
   4.108 + * Retrieve the hub device info structure for the given nasid.
   4.109 + */
   4.110 +static inline u64 sal_get_hubdev_info(u64 handle, u64 address)
   4.111 +{
   4.112 +	struct ia64_sal_retval ret_stuff;
   4.113 +	ret_stuff.status = 0;
   4.114 +	ret_stuff.v0 = 0;
   4.115 +
   4.116 +	SAL_CALL_NOLOCK(ret_stuff,
   4.117 +			(u64) SN_SAL_IOIF_GET_HUBDEV_INFO,
   4.118 +			(u64) handle, (u64) address, 0, 0, 0, 0, 0);
   4.119 +	return ret_stuff.v0;
   4.120 +}
   4.121 +
   4.122 +/*
   4.123 + * Retrieve the pci bus information given the bus number.
   4.124 + */
   4.125 +static inline u64 sal_get_pcibus_info(u64 segment, u64 busnum, u64 address)
   4.126 +{
   4.127 +	struct ia64_sal_retval ret_stuff;
   4.128 +	ret_stuff.status = 0;
   4.129 +	ret_stuff.v0 = 0;
   4.130 +
   4.131 +	SAL_CALL_NOLOCK(ret_stuff,
   4.132 +			(u64) SN_SAL_IOIF_GET_PCIBUS_INFO,
   4.133 +			(u64) segment, (u64) busnum, (u64) address, 0, 0, 0, 0);
   4.134 +	return ret_stuff.v0;
   4.135 +}
   4.136 +
   4.137 +/*
   4.138 + * Retrieve the pci device information given the bus and device|function number.
   4.139 + */
   4.140 +static inline u64
   4.141 +sal_get_pcidev_info(u64 segment, u64 bus_number, u64 devfn, u64 pci_dev,
   4.142 +		    u64 sn_irq_info)
   4.143 +{
   4.144 +	struct ia64_sal_retval ret_stuff;
   4.145 +	ret_stuff.status = 0;
   4.146 +	ret_stuff.v0 = 0;
   4.147 +
   4.148 +	SAL_CALL_NOLOCK(ret_stuff,
   4.149 +			(u64) SN_SAL_IOIF_GET_PCIDEV_INFO,
   4.150 +			(u64) segment, (u64) bus_number, (u64) devfn,
   4.151 +			(u64) pci_dev,
   4.152 +			sn_irq_info, 0, 0);
   4.153 +	return ret_stuff.v0;
   4.154 +}
   4.155 +
   4.156 +/*
   4.157 + * sn_pcidev_info_get() - Retrieve the pcidev_info struct for the specified
   4.158 + *			  device.
   4.159 + */
   4.160 +inline struct pcidev_info *
   4.161 +sn_pcidev_info_get(struct pci_dev *dev)
   4.162 +{
   4.163 +	struct pcidev_info *pcidev;
   4.164 +
   4.165 +	list_for_each_entry(pcidev,
   4.166 +			    &(SN_PCI_CONTROLLER(dev)->pcidev_info), pdi_list) {
   4.167 +		if (pcidev->pdi_linux_pcidev == dev) {
   4.168 +			return pcidev;
   4.169 +		}
   4.170 +	}
   4.171 +	return NULL;
   4.172 +}
   4.173 +
   4.174 +/* Older PROM flush WAR
   4.175 + *
   4.176 + * 01/16/06 -- This war will be in place until a new official PROM is released.
   4.177 + * Additionally note that the struct sn_flush_device_war also has to be
   4.178 + * removed from arch/ia64/sn/include/xtalk/hubdev.h
   4.179 + */
   4.180 +static u8 war_implemented = 0;
   4.181 +
   4.182 +static s64 sn_device_fixup_war(u64 nasid, u64 widget, int device,
   4.183 +			       struct sn_flush_device_common *common)
   4.184 +{
   4.185 +	struct sn_flush_device_war *war_list;
   4.186 +	struct sn_flush_device_war *dev_entry;
   4.187 +	struct ia64_sal_retval isrv = {0,0,0,0};
   4.188 +
   4.189 +	if (!war_implemented) {
   4.190 +		printk(KERN_WARNING "PROM version < 4.50 -- implementing old "
   4.191 +		       "PROM flush WAR\n");
   4.192 +		war_implemented = 1;
   4.193 +	}
   4.194 +
   4.195 +	war_list = kzalloc(DEV_PER_WIDGET * sizeof(*war_list), GFP_KERNEL);
   4.196 +	if (!war_list)
   4.197 +		BUG();
   4.198 +
   4.199 +	SAL_CALL_NOLOCK(isrv, SN_SAL_IOIF_GET_WIDGET_DMAFLUSH_LIST,
   4.200 +			nasid, widget, __pa(war_list), 0, 0, 0 ,0);
   4.201 +	if (isrv.status)
   4.202 +		panic("sn_device_fixup_war failed: %s\n",
   4.203 +		      ia64_sal_strerror(isrv.status));
   4.204 +
   4.205 +	dev_entry = war_list + device;
   4.206 +	memcpy(common,dev_entry, sizeof(*common));
   4.207 +	kfree(war_list);
   4.208 +
   4.209 +	return isrv.status;
   4.210 +}
   4.211 +
   4.212 +/*
   4.213 + * sn_fixup_ionodes() - This routine initializes the HUB data strcuture for
   4.214 + *	each node in the system.
   4.215 + */
   4.216 +static void __init sn_fixup_ionodes(void)
   4.217 +{
   4.218 +	struct sn_flush_device_kernel *sn_flush_device_kernel;
   4.219 +	struct sn_flush_device_kernel *dev_entry;
   4.220 +	struct hubdev_info *hubdev;
   4.221 +	u64 status;
   4.222 +	u64 nasid;
   4.223 +	int i, widget, device, size;
   4.224 +
   4.225 +	/*
   4.226 +	 * Get SGI Specific HUB chipset information.
   4.227 +	 * Inform Prom that this kernel can support domain bus numbering.
   4.228 +	 */
   4.229 +	for (i = 0; i < num_cnodes; i++) {
   4.230 +		hubdev = (struct hubdev_info *)(NODEPDA(i)->pdinfo);
   4.231 +		nasid = cnodeid_to_nasid(i);
   4.232 +		hubdev->max_segment_number = 0xffffffff;
   4.233 +		hubdev->max_pcibus_number = 0xff;
   4.234 +		status = sal_get_hubdev_info(nasid, (u64) __pa(hubdev));
   4.235 +		if (status)
   4.236 +			continue;
   4.237 +
   4.238 +		/* Save the largest Domain and pcibus numbers found. */
   4.239 +		if (hubdev->max_segment_number) {
   4.240 +			/*
   4.241 +			 * Dealing with a Prom that supports segments.
   4.242 +			 */
   4.243 +			max_segment_number = hubdev->max_segment_number;
   4.244 +			max_pcibus_number = hubdev->max_pcibus_number;
   4.245 +		}
   4.246 +
   4.247 +		/* Attach the error interrupt handlers */
   4.248 +		if (nasid & 1)
   4.249 +			ice_error_init(hubdev);
   4.250 +		else
   4.251 +			hub_error_init(hubdev);
   4.252 +
   4.253 +		for (widget = 0; widget <= HUB_WIDGET_ID_MAX; widget++)
   4.254 +			hubdev->hdi_xwidget_info[widget].xwi_hubinfo = hubdev;
   4.255 +
   4.256 +		if (!hubdev->hdi_flush_nasid_list.widget_p)
   4.257 +			continue;
   4.258 +
   4.259 +		size = (HUB_WIDGET_ID_MAX + 1) *
   4.260 +			sizeof(struct sn_flush_device_kernel *);
   4.261 +		hubdev->hdi_flush_nasid_list.widget_p =
   4.262 +			kzalloc(size, GFP_KERNEL);
   4.263 +		if (!hubdev->hdi_flush_nasid_list.widget_p)
   4.264 +			BUG();
   4.265 +
   4.266 +		for (widget = 0; widget <= HUB_WIDGET_ID_MAX; widget++) {
   4.267 +			size = DEV_PER_WIDGET *
   4.268 +				sizeof(struct sn_flush_device_kernel);
   4.269 +			sn_flush_device_kernel = kzalloc(size, GFP_KERNEL);
   4.270 +			if (!sn_flush_device_kernel)
   4.271 +				BUG();
   4.272 +
   4.273 +			dev_entry = sn_flush_device_kernel;
   4.274 +			for (device = 0; device < DEV_PER_WIDGET;
   4.275 +			     device++,dev_entry++) {
   4.276 +				size = sizeof(struct sn_flush_device_common);
   4.277 +				dev_entry->common = kzalloc(size, GFP_KERNEL);
   4.278 +				if (!dev_entry->common)
   4.279 +					BUG();
   4.280 +
   4.281 +				if (sn_prom_feature_available(
   4.282 +						       PRF_DEVICE_FLUSH_LIST))
   4.283 +					status = sal_get_device_dmaflush_list(
   4.284 +						     nasid, widget, device,
   4.285 +						     (u64)(dev_entry->common));
   4.286 +				else
   4.287 +					status = sn_device_fixup_war(nasid,
   4.288 +						     widget, device,
   4.289 +						     dev_entry->common);
   4.290 +				if (status != SALRET_OK)
   4.291 +					panic("SAL call failed: %s\n",
   4.292 +					      ia64_sal_strerror(status));
   4.293 +
   4.294 +				spin_lock_init(&dev_entry->sfdl_flush_lock);
   4.295 +			}
   4.296 +
   4.297 +			if (sn_flush_device_kernel)
   4.298 +				hubdev->hdi_flush_nasid_list.widget_p[widget] =
   4.299 +						       sn_flush_device_kernel;
   4.300 +	        }
   4.301 +	}
   4.302 +}
   4.303 +
   4.304 +/*
   4.305 + * sn_pci_window_fixup() - Create a pci_window for each device resource.
   4.306 + *			   Until ACPI support is added, we need this code
   4.307 + *			   to setup pci_windows for use by
   4.308 + *			   pcibios_bus_to_resource(),
   4.309 + *			   pcibios_resource_to_bus(), etc.
   4.310 + */
   4.311 +static void
   4.312 +sn_pci_window_fixup(struct pci_dev *dev, unsigned int count,
   4.313 +		    s64 * pci_addrs)
   4.314 +{
   4.315 +	struct pci_controller *controller = PCI_CONTROLLER(dev->bus);
   4.316 +	unsigned int i;
   4.317 +	unsigned int idx;
   4.318 +	unsigned int new_count;
   4.319 +	struct pci_window *new_window;
   4.320 +
   4.321 +	if (count == 0)
   4.322 +		return;
   4.323 +	idx = controller->windows;
   4.324 +	new_count = controller->windows + count;
   4.325 +	new_window = kcalloc(new_count, sizeof(struct pci_window), GFP_KERNEL);
   4.326 +	if (new_window == NULL)
   4.327 +		BUG();
   4.328 +	if (controller->window) {
   4.329 +		memcpy(new_window, controller->window,
   4.330 +		       sizeof(struct pci_window) * controller->windows);
   4.331 +		kfree(controller->window);
   4.332 +	}
   4.333 +
   4.334 +	/* Setup a pci_window for each device resource. */
   4.335 +	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
   4.336 +		if (pci_addrs[i] == -1)
   4.337 +			continue;
   4.338 +
   4.339 +		new_window[idx].offset = dev->resource[i].start - pci_addrs[i];
   4.340 +		new_window[idx].resource = dev->resource[i];
   4.341 +		idx++;
   4.342 +	}
   4.343 +
   4.344 +	controller->windows = new_count;
   4.345 +	controller->window = new_window;
   4.346 +}
   4.347 +
   4.348 +void sn_pci_unfixup_slot(struct pci_dev *dev)
   4.349 +{
   4.350 +	struct pci_dev *host_pci_dev = SN_PCIDEV_INFO(dev)->host_pci_dev;
   4.351 +
   4.352 +	sn_irq_unfixup(dev);
   4.353 +	pci_dev_put(host_pci_dev);
   4.354 +	pci_dev_put(dev);
   4.355 +}
   4.356 +
   4.357 +/*
   4.358 + * sn_pci_fixup_slot() - This routine sets up a slot's resources
   4.359 + * consistent with the Linux PCI abstraction layer.  Resources acquired
   4.360 + * from our PCI provider include PIO maps to BAR space and interrupt
   4.361 + * objects.
   4.362 + */
   4.363 +void sn_pci_fixup_slot(struct pci_dev *dev)
   4.364 +{
   4.365 +	unsigned int count = 0;
   4.366 +	int idx;
   4.367 +	int segment = pci_domain_nr(dev->bus);
   4.368 +	int status = 0;
   4.369 +	struct pcibus_bussoft *bs;
   4.370 + 	struct pci_bus *host_pci_bus;
   4.371 + 	struct pci_dev *host_pci_dev;
   4.372 +	struct pcidev_info *pcidev_info;
   4.373 +	s64 pci_addrs[PCI_ROM_RESOURCE + 1];
   4.374 + 	struct sn_irq_info *sn_irq_info;
   4.375 + 	unsigned long size;
   4.376 + 	unsigned int bus_no, devfn;
   4.377 +
   4.378 +	pci_dev_get(dev); /* for the sysdata pointer */
   4.379 +	pcidev_info = kzalloc(sizeof(struct pcidev_info), GFP_KERNEL);
   4.380 +	if (!pcidev_info)
   4.381 +		BUG();		/* Cannot afford to run out of memory */
   4.382 +
   4.383 +	sn_irq_info = kzalloc(sizeof(struct sn_irq_info), GFP_KERNEL);
   4.384 +	if (!sn_irq_info)
   4.385 +		BUG();		/* Cannot afford to run out of memory */
   4.386 +
   4.387 +	/* Call to retrieve pci device information needed by kernel. */
   4.388 +	status = sal_get_pcidev_info((u64) segment, (u64) dev->bus->number, 
   4.389 +				     dev->devfn,
   4.390 +				     (u64) __pa(pcidev_info),
   4.391 +				     (u64) __pa(sn_irq_info));
   4.392 +	if (status)
   4.393 +		BUG(); /* Cannot get platform pci device information */
   4.394 +
   4.395 +	/* Add pcidev_info to list in sn_pci_controller struct */
   4.396 +	list_add_tail(&pcidev_info->pdi_list,
   4.397 +		      &(SN_PCI_CONTROLLER(dev->bus)->pcidev_info));
   4.398 +
   4.399 +	/* Copy over PIO Mapped Addresses */
   4.400 +	for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
   4.401 +		unsigned long start, end, addr;
   4.402 +
   4.403 +		if (!pcidev_info->pdi_pio_mapped_addr[idx]) {
   4.404 +			pci_addrs[idx] = -1;
   4.405 +			continue;
   4.406 +		}
   4.407 +
   4.408 +		start = dev->resource[idx].start;
   4.409 +		end = dev->resource[idx].end;
   4.410 +		size = end - start;
   4.411 +		if (size == 0) {
   4.412 +			pci_addrs[idx] = -1;
   4.413 +			continue;
   4.414 +		}
   4.415 +		pci_addrs[idx] = start;
   4.416 +		count++;
   4.417 +		addr = pcidev_info->pdi_pio_mapped_addr[idx];
   4.418 +		addr = ((addr << 4) >> 4) | __IA64_UNCACHED_OFFSET;
   4.419 +		dev->resource[idx].start = addr;
   4.420 +		dev->resource[idx].end = addr + size;
   4.421 +		if (dev->resource[idx].flags & IORESOURCE_IO)
   4.422 +			dev->resource[idx].parent = &ioport_resource;
   4.423 +		else
   4.424 +			dev->resource[idx].parent = &iomem_resource;
   4.425 +	}
   4.426 +	/* Create a pci_window in the pci_controller struct for
   4.427 +	 * each device resource.
   4.428 +	 */
   4.429 +	if (count > 0)
   4.430 +		sn_pci_window_fixup(dev, count, pci_addrs);
   4.431 +
   4.432 +	/*
   4.433 +	 * Using the PROMs values for the PCI host bus, get the Linux
   4.434 + 	 * PCI host_pci_dev struct and set up host bus linkages
   4.435 + 	 */
   4.436 +
   4.437 +	bus_no = (pcidev_info->pdi_slot_host_handle >> 32) & 0xff;
   4.438 +	devfn = pcidev_info->pdi_slot_host_handle & 0xffffffff;
   4.439 + 	host_pci_bus = pci_find_bus(segment, bus_no);
   4.440 + 	host_pci_dev = pci_get_slot(host_pci_bus, devfn);
   4.441 +
   4.442 +	pcidev_info->host_pci_dev = host_pci_dev;
   4.443 +	pcidev_info->pdi_linux_pcidev = dev;
   4.444 +	pcidev_info->pdi_host_pcidev_info = SN_PCIDEV_INFO(host_pci_dev);
   4.445 +	bs = SN_PCIBUS_BUSSOFT(dev->bus);
   4.446 +	pcidev_info->pdi_pcibus_info = bs;
   4.447 +
   4.448 +	if (bs && bs->bs_asic_type < PCIIO_ASIC_MAX_TYPES) {
   4.449 +		SN_PCIDEV_BUSPROVIDER(dev) = sn_pci_provider[bs->bs_asic_type];
   4.450 +	} else {
   4.451 +		SN_PCIDEV_BUSPROVIDER(dev) = &sn_pci_default_provider;
   4.452 +	}
   4.453 +
   4.454 +	/* Only set up IRQ stuff if this device has a host bus context */
   4.455 +	if (bs && sn_irq_info->irq_irq) {
   4.456 +		pcidev_info->pdi_sn_irq_info = sn_irq_info;
   4.457 +		dev->irq = pcidev_info->pdi_sn_irq_info->irq_irq;
   4.458 +		sn_irq_fixup(dev, sn_irq_info);
   4.459 +	} else {
   4.460 +		pcidev_info->pdi_sn_irq_info = NULL;
   4.461 +		kfree(sn_irq_info);
   4.462 +	}
   4.463 +}
   4.464 +
   4.465 +/*
   4.466 + * sn_pci_controller_fixup() - This routine sets up a bus's resources
   4.467 + * consistent with the Linux PCI abstraction layer.
   4.468 + */
   4.469 +void sn_pci_controller_fixup(int segment, int busnum, struct pci_bus *bus)
   4.470 +{
   4.471 +	int status;
   4.472 +	int nasid, cnode;
   4.473 +	struct pci_controller *controller;
   4.474 +	struct sn_pci_controller *sn_controller;
   4.475 +	struct pcibus_bussoft *prom_bussoft_ptr;
   4.476 +	struct hubdev_info *hubdev_info;
   4.477 +	void *provider_soft;
   4.478 +	struct sn_pcibus_provider *provider;
   4.479 +
   4.480 + 	status = sal_get_pcibus_info((u64) segment, (u64) busnum,
   4.481 + 				     (u64) ia64_tpa(&prom_bussoft_ptr));
   4.482 + 	if (status > 0)
   4.483 +		return;		/*bus # does not exist */
   4.484 +	prom_bussoft_ptr = __va(prom_bussoft_ptr);
   4.485 +
   4.486 +	/* Allocate a sn_pci_controller, which has a pci_controller struct
   4.487 +	 * as the first member.
   4.488 +	 */
   4.489 +	sn_controller = kzalloc(sizeof(struct sn_pci_controller), GFP_KERNEL);
   4.490 +	if (!sn_controller)
   4.491 +		BUG();
   4.492 +	INIT_LIST_HEAD(&sn_controller->pcidev_info);
   4.493 +	controller = &sn_controller->pci_controller;
   4.494 +	controller->segment = segment;
   4.495 +
   4.496 +	if (bus == NULL) {
   4.497 + 		bus = pci_scan_bus(busnum, &pci_root_ops, controller);
   4.498 + 		if (bus == NULL)
   4.499 + 			goto error_return; /* error, or bus already scanned */
   4.500 + 		bus->sysdata = NULL;
   4.501 +	}
   4.502 +
   4.503 +	if (bus->sysdata)
   4.504 +		goto error_return; /* sysdata already alloc'd */
   4.505 +
   4.506 +	/*
   4.507 +	 * Per-provider fixup.  Copies the contents from prom to local
   4.508 +	 * area and links SN_PCIBUS_BUSSOFT().
   4.509 +	 */
   4.510 +
   4.511 +	if (prom_bussoft_ptr->bs_asic_type >= PCIIO_ASIC_MAX_TYPES)
   4.512 +		goto error_return; /* unsupported asic type */
   4.513 +
   4.514 +	if (prom_bussoft_ptr->bs_asic_type == PCIIO_ASIC_TYPE_PPB)
   4.515 +		goto error_return; /* no further fixup necessary */
   4.516 +
   4.517 +	provider = sn_pci_provider[prom_bussoft_ptr->bs_asic_type];
   4.518 +	if (provider == NULL)
   4.519 +		goto error_return; /* no provider registerd for this asic */
   4.520 +
   4.521 +	bus->sysdata = controller;
   4.522 +	if (provider->bus_fixup)
   4.523 +		provider_soft = (*provider->bus_fixup) (prom_bussoft_ptr, controller);
   4.524 +	else
   4.525 +		provider_soft = NULL;
   4.526 +
   4.527 +	if (provider_soft == NULL) {
   4.528 +		/* fixup failed or not applicable */
   4.529 +		bus->sysdata = NULL;
   4.530 +		goto error_return;
   4.531 +	}
   4.532 +
   4.533 +	/*
   4.534 +	 * Setup pci_windows for legacy IO and MEM space.
   4.535 +	 * (Temporary until ACPI support is in place.)
   4.536 +	 */
   4.537 +	controller->window = kcalloc(2, sizeof(struct pci_window), GFP_KERNEL);
   4.538 +	if (controller->window == NULL)
   4.539 +		BUG();
   4.540 +	controller->window[0].offset = prom_bussoft_ptr->bs_legacy_io;
   4.541 +	controller->window[0].resource.name = "legacy_io";
   4.542 +	controller->window[0].resource.flags = IORESOURCE_IO;
   4.543 +	controller->window[0].resource.start = prom_bussoft_ptr->bs_legacy_io;
   4.544 +	controller->window[0].resource.end =
   4.545 +	    controller->window[0].resource.start + 0xffff;
   4.546 +	controller->window[0].resource.parent = &ioport_resource;
   4.547 +	controller->window[1].offset = prom_bussoft_ptr->bs_legacy_mem;
   4.548 +	controller->window[1].resource.name = "legacy_mem";
   4.549 +	controller->window[1].resource.flags = IORESOURCE_MEM;
   4.550 +	controller->window[1].resource.start = prom_bussoft_ptr->bs_legacy_mem;
   4.551 +	controller->window[1].resource.end =
   4.552 +	    controller->window[1].resource.start + (1024 * 1024) - 1;
   4.553 +	controller->window[1].resource.parent = &iomem_resource;
   4.554 +	controller->windows = 2;
   4.555 +
   4.556 +	/*
   4.557 +	 * Generic bus fixup goes here.  Don't reference prom_bussoft_ptr
   4.558 +	 * after this point.
   4.559 +	 */
   4.560 +
   4.561 +	PCI_CONTROLLER(bus)->platform_data = provider_soft;
   4.562 +	nasid = NASID_GET(SN_PCIBUS_BUSSOFT(bus)->bs_base);
   4.563 +	cnode = nasid_to_cnodeid(nasid);
   4.564 +	hubdev_info = (struct hubdev_info *)(NODEPDA(cnode)->pdinfo);
   4.565 +	SN_PCIBUS_BUSSOFT(bus)->bs_xwidget_info =
   4.566 +	    &(hubdev_info->hdi_xwidget_info[SN_PCIBUS_BUSSOFT(bus)->bs_xid]);
   4.567 +
   4.568 +	/*
   4.569 +	 * If the node information we obtained during the fixup phase is invalid
   4.570 +	 * then set controller->node to -1 (undetermined)
   4.571 +	 */
   4.572 +	if (controller->node >= num_online_nodes()) {
   4.573 +		struct pcibus_bussoft *b = SN_PCIBUS_BUSSOFT(bus);
   4.574 +
   4.575 +		printk(KERN_WARNING "Device ASIC=%u XID=%u PBUSNUM=%u"
   4.576 +				    "L_IO=%lx L_MEM=%lx BASE=%lx\n",
   4.577 +			b->bs_asic_type, b->bs_xid, b->bs_persist_busnum,
   4.578 +			b->bs_legacy_io, b->bs_legacy_mem, b->bs_base);
   4.579 +		printk(KERN_WARNING "on node %d but only %d nodes online."
   4.580 +			"Association set to undetermined.\n",
   4.581 +			controller->node, num_online_nodes());
   4.582 +		controller->node = -1;
   4.583 +	}
   4.584 +	return;
   4.585 +
   4.586 +error_return:
   4.587 +
   4.588 +	kfree(sn_controller);
   4.589 +	return;
   4.590 +}
   4.591 +
   4.592 +void sn_bus_store_sysdata(struct pci_dev *dev)
   4.593 +{
   4.594 +	struct sysdata_el *element;
   4.595 +
   4.596 +	element = kzalloc(sizeof(struct sysdata_el), GFP_KERNEL);
   4.597 +	if (!element) {
   4.598 +		dev_dbg(dev, "%s: out of memory!\n", __FUNCTION__);
   4.599 +		return;
   4.600 +	}
   4.601 +	element->sysdata = SN_PCIDEV_INFO(dev);
   4.602 +	list_add(&element->entry, &sn_sysdata_list);
   4.603 +}
   4.604 +
   4.605 +void sn_bus_free_sysdata(void)
   4.606 +{
   4.607 +	struct sysdata_el *element;
   4.608 +	struct list_head *list, *safe;
   4.609 +
   4.610 +	list_for_each_safe(list, safe, &sn_sysdata_list) {
   4.611 +		element = list_entry(list, struct sysdata_el, entry);
   4.612 +		list_del(&element->entry);
   4.613 +		list_del(&(((struct pcidev_info *)
   4.614 +			     (element->sysdata))->pdi_list));
   4.615 +		kfree(element->sysdata);
   4.616 +		kfree(element);
   4.617 +	}
   4.618 +	return;
   4.619 +}
   4.620 +
   4.621 +/*
   4.622 + * Ugly hack to get PCI setup until we have a proper ACPI namespace.
   4.623 + */
   4.624 +
   4.625 +#define PCI_BUSES_TO_SCAN 256
   4.626 +
   4.627 +static int __init sn_pci_init(void)
   4.628 +{
   4.629 +	int i, j;
   4.630 +	struct pci_dev *pci_dev = NULL;
   4.631 +
   4.632 +	if (!ia64_platform_is("sn2") || IS_RUNNING_ON_FAKE_PROM())
   4.633 +		return 0;
   4.634 +
   4.635 +	/*
   4.636 +	 * prime sn_pci_provider[].  Individial provider init routines will
   4.637 +	 * override their respective default entries.
   4.638 +	 */
   4.639 +
   4.640 +	for (i = 0; i < PCIIO_ASIC_MAX_TYPES; i++)
   4.641 +		sn_pci_provider[i] = &sn_pci_default_provider;
   4.642 +
   4.643 +	pcibr_init_provider();
   4.644 +	tioca_init_provider();
   4.645 +	tioce_init_provider();
   4.646 +
   4.647 +	/*
   4.648 +	 * This is needed to avoid bounce limit checks in the blk layer
   4.649 +	 */
   4.650 +	ia64_max_iommu_merge_mask = ~PAGE_MASK;
   4.651 +	sn_fixup_ionodes();
   4.652 +	sn_irq_lh_init();
   4.653 +	INIT_LIST_HEAD(&sn_sysdata_list);
   4.654 +	sn_init_cpei_timer();
   4.655 +
   4.656 +#ifdef CONFIG_PROC_FS
   4.657 +	register_sn_procfs();
   4.658 +#endif
   4.659 +
   4.660 +	/* busses are not known yet ... */
   4.661 +	for (i = 0; i <= max_segment_number; i++)
   4.662 +		for (j = 0; j <= max_pcibus_number; j++)
   4.663 +			sn_pci_controller_fixup(i, j, NULL);
   4.664 +
   4.665 +	/*
   4.666 +	 * Generic Linux PCI Layer has created the pci_bus and pci_dev 
   4.667 +	 * structures - time for us to add our SN PLatform specific 
   4.668 +	 * information.
   4.669 +	 */
   4.670 +
   4.671 +	while ((pci_dev =
   4.672 +		pci_get_device(PCI_ANY_ID, PCI_ANY_ID, pci_dev)) != NULL)
   4.673 +		sn_pci_fixup_slot(pci_dev);
   4.674 +
   4.675 +	sn_ioif_inited = 1;	/* sn I/O infrastructure now initialized */
   4.676 +
   4.677 +	return 0;
   4.678 +}
   4.679 +
   4.680 +/*
   4.681 + * hubdev_init_node() - Creates the HUB data structure and link them to it's 
   4.682 + *	own NODE specific data area.
   4.683 + */
   4.684 +void hubdev_init_node(nodepda_t * npda, cnodeid_t node)
   4.685 +{
   4.686 +	struct hubdev_info *hubdev_info;
   4.687 +	int size;
   4.688 +	pg_data_t *pg;
   4.689 +
   4.690 +	size = sizeof(struct hubdev_info);
   4.691 +
   4.692 +	if (node >= num_online_nodes())	/* Headless/memless IO nodes */
   4.693 +		pg = NODE_DATA(0);
   4.694 +	else
   4.695 +		pg = NODE_DATA(node);
   4.696 +
   4.697 +	hubdev_info = (struct hubdev_info *)alloc_bootmem_node(pg, size);
   4.698 +
   4.699 +	npda->pdinfo = (void *)hubdev_info;
   4.700 +}
   4.701 +
   4.702 +geoid_t
   4.703 +cnodeid_get_geoid(cnodeid_t cnode)
   4.704 +{
   4.705 +	struct hubdev_info *hubdev;
   4.706 +
   4.707 +	hubdev = (struct hubdev_info *)(NODEPDA(cnode)->pdinfo);
   4.708 +	return hubdev->hdi_geoid;
   4.709 +}
   4.710 +
   4.711 +void sn_generate_path(struct pci_bus *pci_bus, char *address)
   4.712 +{
   4.713 +	nasid_t nasid;
   4.714 +	cnodeid_t cnode;
   4.715 +	geoid_t geoid;
   4.716 +	moduleid_t moduleid;
   4.717 +	u16 bricktype;
   4.718 +
   4.719 +	nasid = NASID_GET(SN_PCIBUS_BUSSOFT(pci_bus)->bs_base);
   4.720 +	cnode = nasid_to_cnodeid(nasid);
   4.721 +	geoid = cnodeid_get_geoid(cnode);
   4.722 +	moduleid = geo_module(geoid);
   4.723 +
   4.724 +	sprintf(address, "module_%c%c%c%c%.2d",
   4.725 +		'0'+RACK_GET_CLASS(MODULE_GET_RACK(moduleid)),
   4.726 +		'0'+RACK_GET_GROUP(MODULE_GET_RACK(moduleid)),
   4.727 +		'0'+RACK_GET_NUM(MODULE_GET_RACK(moduleid)),
   4.728 +		MODULE_GET_BTCHAR(moduleid), MODULE_GET_BPOS(moduleid));
   4.729 +
   4.730 +	/* Tollhouse requires slot id to be displayed */
   4.731 +	bricktype = MODULE_GET_BTYPE(moduleid);
   4.732 +	if ((bricktype == L1_BRICKTYPE_191010) ||
   4.733 +	    (bricktype == L1_BRICKTYPE_1932))
   4.734 +			sprintf(address, "%s^%d", address, geo_slot(geoid));
   4.735 +}
   4.736 +
   4.737 +subsys_initcall(sn_pci_init);
   4.738 +EXPORT_SYMBOL(sn_pci_fixup_slot);
   4.739 +EXPORT_SYMBOL(sn_pci_unfixup_slot);
   4.740 +EXPORT_SYMBOL(sn_pci_controller_fixup);
   4.741 +EXPORT_SYMBOL(sn_bus_store_sysdata);
   4.742 +EXPORT_SYMBOL(sn_bus_free_sysdata);
   4.743 +EXPORT_SYMBOL(sn_generate_path);

     5.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     5.2 +++ b/xen/arch/ia64/linux-xen/sn/kernel/iomv.c	Wed Dec 13 11:08:40 2006 -0700
     5.3 @@ -0,0 +1,76 @@
     5.4 +/* 
     5.5 + * This file is subject to the terms and conditions of the GNU General Public
     5.6 + * License.  See the file "COPYING" in the main directory of this archive
     5.7 + * for more details.
     5.8 + *
     5.9 + * Copyright (C) 2000-2003 Silicon Graphics, Inc. All rights reserved.
    5.10 + */
    5.11 +
    5.12 +#include <linux/module.h>
    5.13 +#include <asm/io.h>
    5.14 +#include <asm/delay.h>
    5.15 +#include <asm/vga.h>
    5.16 +#include <asm/sn/nodepda.h>
    5.17 +#include <asm/sn/simulator.h>
    5.18 +#include <asm/sn/pda.h>
    5.19 +#include <asm/sn/sn_cpuid.h>
    5.20 +#include <asm/sn/shub_mmr.h>
    5.21 +
    5.22 +#define IS_LEGACY_VGA_IOPORT(p) \
    5.23 +	(((p) >= 0x3b0 && (p) <= 0x3bb) || ((p) >= 0x3c0 && (p) <= 0x3df))
    5.24 +
    5.25 +/**
    5.26 + * sn_io_addr - convert an in/out port to an i/o address
    5.27 + * @port: port to convert
    5.28 + *
    5.29 + * Legacy in/out instructions are converted to ld/st instructions
    5.30 + * on IA64.  This routine will convert a port number into a valid 
    5.31 + * SN i/o address.  Used by sn_in*() and sn_out*().
    5.32 + */
    5.33 +void *sn_io_addr(unsigned long port)
    5.34 +{
    5.35 +	if (!IS_RUNNING_ON_SIMULATOR()) {
    5.36 +		if (IS_LEGACY_VGA_IOPORT(port))
    5.37 +			port += vga_console_iobase;
    5.38 +		/* On sn2, legacy I/O ports don't point at anything */
    5.39 +		if (port < (64 * 1024))
    5.40 +			return NULL;
    5.41 +		return ((void *)(port | __IA64_UNCACHED_OFFSET));
    5.42 +	} else {
    5.43 +		/* but the simulator uses them... */
    5.44 +		unsigned long addr;
    5.45 +
    5.46 +		/*
    5.47 +		 * word align port, but need more than 10 bits
    5.48 +		 * for accessing registers in bedrock local block
    5.49 +		 * (so we don't do port&0xfff)
    5.50 +		 */
    5.51 +		addr = (is_shub2() ? 0xc00000028c000000UL : 0xc0000087cc000000UL) | ((port >> 2) << 12);
    5.52 +		if ((port >= 0x1f0 && port <= 0x1f7) || port == 0x3f6 || port == 0x3f7)
    5.53 +			addr |= port;
    5.54 +		return (void *)addr;
    5.55 +	}
    5.56 +}
    5.57 +
    5.58 +EXPORT_SYMBOL(sn_io_addr);
    5.59 +
    5.60 +/**
    5.61 + * __sn_mmiowb - I/O space memory barrier
    5.62 + *
    5.63 + * See include/asm-ia64/io.h and Documentation/DocBook/deviceiobook.tmpl
    5.64 + * for details.
    5.65 + *
    5.66 + * On SN2, we wait for the PIO_WRITE_STATUS SHub register to clear.
    5.67 + * See PV 871084 for details about the WAR about zero value.
    5.68 + *
    5.69 + */
    5.70 +void __sn_mmiowb(void)
    5.71 +{
    5.72 +	volatile unsigned long *adr = pda->pio_write_status_addr;
    5.73 +	unsigned long val = pda->pio_write_status_val;
    5.74 +
    5.75 +	while ((*adr & SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK) != val)
    5.76 +		cpu_relax();
    5.77 +}
    5.78 +
    5.79 +EXPORT_SYMBOL(__sn_mmiowb);

     6.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     6.2 +++ b/xen/arch/ia64/linux-xen/sn/kernel/irq.c	Wed Dec 13 11:08:40 2006 -0700
     6.3 @@ -0,0 +1,444 @@
     6.4 +/*
     6.5 + * Platform dependent support for SGI SN
     6.6 + *
     6.7 + * This file is subject to the terms and conditions of the GNU General Public
     6.8 + * License.  See the file "COPYING" in the main directory of this archive
     6.9 + * for more details.
    6.10 + *
    6.11 + * Copyright (c) 2000-2006 Silicon Graphics, Inc.  All Rights Reserved.
    6.12 + */
    6.13 +
    6.14 +#include <linux/irq.h>
    6.15 +#include <linux/spinlock.h>
    6.16 +#include <linux/init.h>
    6.17 +#include <asm/sn/addrs.h>
    6.18 +#include <asm/sn/arch.h>
    6.19 +#include <asm/sn/intr.h>
    6.20 +#include <asm/sn/pcibr_provider.h>
    6.21 +#include <asm/sn/pcibus_provider_defs.h>
    6.22 +#include <asm/sn/pcidev.h>
    6.23 +#include <asm/sn/shub_mmr.h>
    6.24 +#include <asm/sn/sn_sal.h>
    6.25 +
    6.26 +static void force_interrupt(int irq);
    6.27 +static void register_intr_pda(struct sn_irq_info *sn_irq_info);
    6.28 +static void unregister_intr_pda(struct sn_irq_info *sn_irq_info);
    6.29 +
    6.30 +int sn_force_interrupt_flag = 1;
    6.31 +extern int sn_ioif_inited;
    6.32 +struct list_head **sn_irq_lh;
    6.33 +static DEFINE_SPINLOCK(sn_irq_info_lock); /* non-IRQ lock */
    6.34 +
    6.35 +u64 sn_intr_alloc(nasid_t local_nasid, int local_widget,
    6.36 +				     struct sn_irq_info *sn_irq_info,
    6.37 +				     int req_irq, nasid_t req_nasid,
    6.38 +				     int req_slice)
    6.39 +{
    6.40 +	struct ia64_sal_retval ret_stuff;
    6.41 +	ret_stuff.status = 0;
    6.42 +	ret_stuff.v0 = 0;
    6.43 +
    6.44 +	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
    6.45 +			(u64) SAL_INTR_ALLOC, (u64) local_nasid,
    6.46 +			(u64) local_widget, __pa(sn_irq_info), (u64) req_irq,
    6.47 +			(u64) req_nasid, (u64) req_slice);
    6.48 +
    6.49 +	return ret_stuff.status;
    6.50 +}
    6.51 +
    6.52 +void sn_intr_free(nasid_t local_nasid, int local_widget,
    6.53 +				struct sn_irq_info *sn_irq_info)
    6.54 +{
    6.55 +	struct ia64_sal_retval ret_stuff;
    6.56 +	ret_stuff.status = 0;
    6.57 +	ret_stuff.v0 = 0;
    6.58 +
    6.59 +	SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
    6.60 +			(u64) SAL_INTR_FREE, (u64) local_nasid,
    6.61 +			(u64) local_widget, (u64) sn_irq_info->irq_irq,
    6.62 +			(u64) sn_irq_info->irq_cookie, 0, 0);
    6.63 +}
    6.64 +
    6.65 +static unsigned int sn_startup_irq(unsigned int irq)
    6.66 +{
    6.67 +	return 0;
    6.68 +}
    6.69 +
    6.70 +static void sn_shutdown_irq(unsigned int irq)
    6.71 +{
    6.72 +}
    6.73 +
    6.74 +static void sn_disable_irq(unsigned int irq)
    6.75 +{
    6.76 +}
    6.77 +
    6.78 +static void sn_enable_irq(unsigned int irq)
    6.79 +{
    6.80 +}
    6.81 +
    6.82 +static void sn_ack_irq(unsigned int irq)
    6.83 +{
    6.84 +	u64 event_occurred, mask;
    6.85 +
    6.86 +	irq = irq & 0xff;
    6.87 +	event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED));
    6.88 +	mask = event_occurred & SH_ALL_INT_MASK;
    6.89 +	HUB_S((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED_ALIAS), mask);
    6.90 +	__set_bit(irq, (volatile void *)pda->sn_in_service_ivecs);
    6.91 +
    6.92 +	move_native_irq(irq);
    6.93 +}
    6.94 +
    6.95 +static void sn_end_irq(unsigned int irq)
    6.96 +{
    6.97 +	int ivec;
    6.98 +	u64 event_occurred;
    6.99 +
   6.100 +	ivec = irq & 0xff;
   6.101 +	if (ivec == SGI_UART_VECTOR) {
   6.102 +		event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR (SH_EVENT_OCCURRED));
   6.103 +		/* If the UART bit is set here, we may have received an
   6.104 +		 * interrupt from the UART that the driver missed.  To
   6.105 +		 * make sure, we IPI ourselves to force us to look again.
   6.106 +		 */
   6.107 +		if (event_occurred & SH_EVENT_OCCURRED_UART_INT_MASK) {
   6.108 +			platform_send_ipi(smp_processor_id(), SGI_UART_VECTOR,
   6.109 +					  IA64_IPI_DM_INT, 0);
   6.110 +		}
   6.111 +	}
   6.112 +	__clear_bit(ivec, (volatile void *)pda->sn_in_service_ivecs);
   6.113 +	if (sn_force_interrupt_flag)
   6.114 +		force_interrupt(irq);
   6.115 +}
   6.116 +
   6.117 +static void sn_irq_info_free(struct rcu_head *head);
   6.118 +
   6.119 +struct sn_irq_info *sn_retarget_vector(struct sn_irq_info *sn_irq_info,
   6.120 +				       nasid_t nasid, int slice)
   6.121 +{
   6.122 +	int vector;
   6.123 +	int cpuphys;
   6.124 +	int64_t bridge;
   6.125 +	int local_widget, status;
   6.126 +	nasid_t local_nasid;
   6.127 +	struct sn_irq_info *new_irq_info;
   6.128 +	struct sn_pcibus_provider *pci_provider;
   6.129 +
   6.130 +	new_irq_info = kmalloc(sizeof(struct sn_irq_info), GFP_ATOMIC);
   6.131 +	if (new_irq_info == NULL)
   6.132 +		return NULL;
   6.133 +
   6.134 +	memcpy(new_irq_info, sn_irq_info, sizeof(struct sn_irq_info));
   6.135 +
   6.136 +	bridge = (u64) new_irq_info->irq_bridge;
   6.137 +	if (!bridge) {
   6.138 +		kfree(new_irq_info);
   6.139 +		return NULL; /* irq is not a device interrupt */
   6.140 +	}
   6.141 +
   6.142 +	local_nasid = NASID_GET(bridge);
   6.143 +
   6.144 +	if (local_nasid & 1)
   6.145 +		local_widget = TIO_SWIN_WIDGETNUM(bridge);
   6.146 +	else
   6.147 +		local_widget = SWIN_WIDGETNUM(bridge);
   6.148 +
   6.149 +	vector = sn_irq_info->irq_irq;
   6.150 +	/* Free the old PROM new_irq_info structure */
   6.151 +	sn_intr_free(local_nasid, local_widget, new_irq_info);
   6.152 +	/* Update kernels new_irq_info with new target info */
   6.153 +	unregister_intr_pda(new_irq_info);
   6.154 +
   6.155 +	/* allocate a new PROM new_irq_info struct */
   6.156 +	status = sn_intr_alloc(local_nasid, local_widget,
   6.157 +			       new_irq_info, vector,
   6.158 +			       nasid, slice);
   6.159 +
   6.160 +	/* SAL call failed */
   6.161 +	if (status) {
   6.162 +		kfree(new_irq_info);
   6.163 +		return NULL;
   6.164 +	}
   6.165 +
   6.166 +	cpuphys = nasid_slice_to_cpuid(nasid, slice);
   6.167 +	new_irq_info->irq_cpuid = cpuphys;
   6.168 +	register_intr_pda(new_irq_info);
   6.169 +
   6.170 +	pci_provider = sn_pci_provider[new_irq_info->irq_bridge_type];
   6.171 +
   6.172 +	/*
   6.173 +	 * If this represents a line interrupt, target it.  If it's
   6.174 +	 * an msi (irq_int_bit < 0), it's already targeted.
   6.175 +	 */
   6.176 +	if (new_irq_info->irq_int_bit >= 0 &&
   6.177 +	    pci_provider && pci_provider->target_interrupt)
   6.178 +		(pci_provider->target_interrupt)(new_irq_info);
   6.179 +
   6.180 +	spin_lock(&sn_irq_info_lock);
   6.181 +	list_replace_rcu(&sn_irq_info->list, &new_irq_info->list);
   6.182 +	spin_unlock(&sn_irq_info_lock);
   6.183 +	call_rcu(&sn_irq_info->rcu, sn_irq_info_free);
   6.184 +
   6.185 +#ifdef CONFIG_SMP
   6.186 +	set_irq_affinity_info((vector & 0xff), cpuphys, 0);
   6.187 +#endif
   6.188 +
   6.189 +	return new_irq_info;
   6.190 +}
   6.191 +
   6.192 +static void sn_set_affinity_irq(unsigned int irq, cpumask_t mask)
   6.193 +{
   6.194 +	struct sn_irq_info *sn_irq_info, *sn_irq_info_safe;
   6.195 +	nasid_t nasid;
   6.196 +	int slice;
   6.197 +
   6.198 +	nasid = cpuid_to_nasid(first_cpu(mask));
   6.199 +	slice = cpuid_to_slice(first_cpu(mask));
   6.200 +
   6.201 +	list_for_each_entry_safe(sn_irq_info, sn_irq_info_safe,
   6.202 +				 sn_irq_lh[irq], list)
   6.203 +		(void)sn_retarget_vector(sn_irq_info, nasid, slice);
   6.204 +}
   6.205 +
   6.206 +struct hw_interrupt_type irq_type_sn = {
   6.207 +	.name		= "SN hub",
   6.208 +	.startup	= sn_startup_irq,
   6.209 +	.shutdown	= sn_shutdown_irq,
   6.210 +	.enable		= sn_enable_irq,
   6.211 +	.disable	= sn_disable_irq,
   6.212 +	.ack		= sn_ack_irq,
   6.213 +	.end		= sn_end_irq,
   6.214 +	.set_affinity	= sn_set_affinity_irq
   6.215 +};
   6.216 +
   6.217 +unsigned int sn_local_vector_to_irq(u8 vector)
   6.218 +{
   6.219 +	return (CPU_VECTOR_TO_IRQ(smp_processor_id(), vector));
   6.220 +}
   6.221 +
   6.222 +void sn_irq_init(void)
   6.223 +{
   6.224 +	int i;
   6.225 +	irq_desc_t *base_desc = irq_desc;
   6.226 +
   6.227 +	ia64_first_device_vector = IA64_SN2_FIRST_DEVICE_VECTOR;
   6.228 +	ia64_last_device_vector = IA64_SN2_LAST_DEVICE_VECTOR;
   6.229 +
   6.230 +	for (i = 0; i < NR_IRQS; i++) {
   6.231 +		if (base_desc[i].chip == &no_irq_type) {
   6.232 +			base_desc[i].chip = &irq_type_sn;
   6.233 +		}
   6.234 +	}
   6.235 +}
   6.236 +
   6.237 +static void register_intr_pda(struct sn_irq_info *sn_irq_info)
   6.238 +{
   6.239 +	int irq = sn_irq_info->irq_irq;
   6.240 +	int cpu = sn_irq_info->irq_cpuid;
   6.241 +
   6.242 +	if (pdacpu(cpu)->sn_last_irq < irq) {
   6.243 +		pdacpu(cpu)->sn_last_irq = irq;
   6.244 +	}
   6.245 +
   6.246 +	if (pdacpu(cpu)->sn_first_irq == 0 || pdacpu(cpu)->sn_first_irq > irq)
   6.247 +		pdacpu(cpu)->sn_first_irq = irq;
   6.248 +}
   6.249 +
   6.250 +static void unregister_intr_pda(struct sn_irq_info *sn_irq_info)
   6.251 +{
   6.252 +	int irq = sn_irq_info->irq_irq;
   6.253 +	int cpu = sn_irq_info->irq_cpuid;
   6.254 +	struct sn_irq_info *tmp_irq_info;
   6.255 +	int i, foundmatch;
   6.256 +
   6.257 +	rcu_read_lock();
   6.258 +	if (pdacpu(cpu)->sn_last_irq == irq) {
   6.259 +		foundmatch = 0;
   6.260 +		for (i = pdacpu(cpu)->sn_last_irq - 1;
   6.261 +		     i && !foundmatch; i--) {
   6.262 +			list_for_each_entry_rcu(tmp_irq_info,
   6.263 +						sn_irq_lh[i],
   6.264 +						list) {
   6.265 +				if (tmp_irq_info->irq_cpuid == cpu) {
   6.266 +					foundmatch = 1;
   6.267 +					break;
   6.268 +				}
   6.269 +			}
   6.270 +		}
   6.271 +		pdacpu(cpu)->sn_last_irq = i;
   6.272 +	}
   6.273 +
   6.274 +	if (pdacpu(cpu)->sn_first_irq == irq) {
   6.275 +		foundmatch = 0;
   6.276 +		for (i = pdacpu(cpu)->sn_first_irq + 1;
   6.277 +		     i < NR_IRQS && !foundmatch; i++) {
   6.278 +			list_for_each_entry_rcu(tmp_irq_info,
   6.279 +						sn_irq_lh[i],
   6.280 +						list) {
   6.281 +				if (tmp_irq_info->irq_cpuid == cpu) {
   6.282 +					foundmatch = 1;
   6.283 +					break;
   6.284 +				}
   6.285 +			}
   6.286 +		}
   6.287 +		pdacpu(cpu)->sn_first_irq = ((i == NR_IRQS) ? 0 : i);
   6.288 +	}
   6.289 +	rcu_read_unlock();
   6.290 +}
   6.291 +
   6.292 +static void sn_irq_info_free(struct rcu_head *head)
   6.293 +{
   6.294 +	struct sn_irq_info *sn_irq_info;
   6.295 +
   6.296 +	sn_irq_info = container_of(head, struct sn_irq_info, rcu);
   6.297 +	kfree(sn_irq_info);
   6.298 +}
   6.299 +
   6.300 +void sn_irq_fixup(struct pci_dev *pci_dev, struct sn_irq_info *sn_irq_info)
   6.301 +{
   6.302 +	nasid_t nasid = sn_irq_info->irq_nasid;
   6.303 +	int slice = sn_irq_info->irq_slice;
   6.304 +	int cpu = nasid_slice_to_cpuid(nasid, slice);
   6.305 +
   6.306 +	pci_dev_get(pci_dev);
   6.307 +	sn_irq_info->irq_cpuid = cpu;
   6.308 +	sn_irq_info->irq_pciioinfo = SN_PCIDEV_INFO(pci_dev);
   6.309 +
   6.310 +	/* link it into the sn_irq[irq] list */
   6.311 +	spin_lock(&sn_irq_info_lock);
   6.312 +	list_add_rcu(&sn_irq_info->list, sn_irq_lh[sn_irq_info->irq_irq]);
   6.313 +	reserve_irq_vector(sn_irq_info->irq_irq);
   6.314 +	spin_unlock(&sn_irq_info_lock);
   6.315 +
   6.316 +	register_intr_pda(sn_irq_info);
   6.317 +}
   6.318 +
   6.319 +void sn_irq_unfixup(struct pci_dev *pci_dev)
   6.320 +{
   6.321 +	struct sn_irq_info *sn_irq_info;
   6.322 +
   6.323 +	/* Only cleanup IRQ stuff if this device has a host bus context */
   6.324 +	if (!SN_PCIDEV_BUSSOFT(pci_dev))
   6.325 +		return;
   6.326 +
   6.327 +	sn_irq_info = SN_PCIDEV_INFO(pci_dev)->pdi_sn_irq_info;
   6.328 +	if (!sn_irq_info)
   6.329 +		return;
   6.330 +	if (!sn_irq_info->irq_irq) {
   6.331 +		kfree(sn_irq_info);
   6.332 +		return;
   6.333 +	}
   6.334 +
   6.335 +	unregister_intr_pda(sn_irq_info);
   6.336 +	spin_lock(&sn_irq_info_lock);
   6.337 +	list_del_rcu(&sn_irq_info->list);
   6.338 +	spin_unlock(&sn_irq_info_lock);
   6.339 +	if (list_empty(sn_irq_lh[sn_irq_info->irq_irq]))
   6.340 +		free_irq_vector(sn_irq_info->irq_irq);
   6.341 +	call_rcu(&sn_irq_info->rcu, sn_irq_info_free);
   6.342 +	pci_dev_put(pci_dev);
   6.343 +
   6.344 +}
   6.345 +
   6.346 +static inline void
   6.347 +sn_call_force_intr_provider(struct sn_irq_info *sn_irq_info)
   6.348 +{
   6.349 +	struct sn_pcibus_provider *pci_provider;
   6.350 +
   6.351 +	pci_provider = sn_pci_provider[sn_irq_info->irq_bridge_type];
   6.352 +	if (pci_provider && pci_provider->force_interrupt)
   6.353 +		(*pci_provider->force_interrupt)(sn_irq_info);
   6.354 +}
   6.355 +
   6.356 +static void force_interrupt(int irq)
   6.357 +{
   6.358 +	struct sn_irq_info *sn_irq_info;
   6.359 +
   6.360 +	if (!sn_ioif_inited)
   6.361 +		return;
   6.362 +
   6.363 +	rcu_read_lock();
   6.364 +	list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[irq], list)
   6.365 +		sn_call_force_intr_provider(sn_irq_info);
   6.366 +
   6.367 +	rcu_read_unlock();
   6.368 +}
   6.369 +
   6.370 +/*
   6.371 + * Check for lost interrupts.  If the PIC int_status reg. says that
   6.372 + * an interrupt has been sent, but not handled, and the interrupt
   6.373 + * is not pending in either the cpu irr regs or in the soft irr regs,
   6.374 + * and the interrupt is not in service, then the interrupt may have
   6.375 + * been lost.  Force an interrupt on that pin.  It is possible that
   6.376 + * the interrupt is in flight, so we may generate a spurious interrupt,
   6.377 + * but we should never miss a real lost interrupt.
   6.378 + */
   6.379 +static void sn_check_intr(int irq, struct sn_irq_info *sn_irq_info)
   6.380 +{
   6.381 +	u64 regval;
   6.382 +	struct pcidev_info *pcidev_info;
   6.383 +	struct pcibus_info *pcibus_info;
   6.384 +
   6.385 +	/*
   6.386 +	 * Bridge types attached to TIO (anything but PIC) do not need this WAR
   6.387 +	 * since they do not target Shub II interrupt registers.  If that
   6.388 +	 * ever changes, this check needs to accomodate.
   6.389 +	 */
   6.390 +	if (sn_irq_info->irq_bridge_type != PCIIO_ASIC_TYPE_PIC)
   6.391 +		return;
   6.392 +
   6.393 +	pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
   6.394 +	if (!pcidev_info)
   6.395 +		return;
   6.396 +
   6.397 +	pcibus_info =
   6.398 +	    (struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
   6.399 +	    pdi_pcibus_info;
   6.400 +	regval = pcireg_intr_status_get(pcibus_info);
   6.401 +
   6.402 +	if (!ia64_get_irr(irq_to_vector(irq))) {
   6.403 +		if (!test_bit(irq, pda->sn_in_service_ivecs)) {
   6.404 +			regval &= 0xff;
   6.405 +			if (sn_irq_info->irq_int_bit & regval &
   6.406 +			    sn_irq_info->irq_last_intr) {
   6.407 +				regval &= ~(sn_irq_info->irq_int_bit & regval);
   6.408 +				sn_call_force_intr_provider(sn_irq_info);
   6.409 +			}
   6.410 +		}
   6.411 +	}
   6.412 +	sn_irq_info->irq_last_intr = regval;
   6.413 +}
   6.414 +
   6.415 +void sn_lb_int_war_check(void)
   6.416 +{
   6.417 +	struct sn_irq_info *sn_irq_info;
   6.418 +	int i;
   6.419 +
   6.420 +	if (!sn_ioif_inited || pda->sn_first_irq == 0)
   6.421 +		return;
   6.422 +
   6.423 +	rcu_read_lock();
   6.424 +	for (i = pda->sn_first_irq; i <= pda->sn_last_irq; i++) {
   6.425 +		list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[i], list) {
   6.426 +			sn_check_intr(i, sn_irq_info);
   6.427 +		}
   6.428 +	}
   6.429 +	rcu_read_unlock();
   6.430 +}
   6.431 +
   6.432 +void __init sn_irq_lh_init(void)
   6.433 +{
   6.434 +	int i;
   6.435 +
   6.436 +	sn_irq_lh = kmalloc(sizeof(struct list_head *) * NR_IRQS, GFP_KERNEL);
   6.437 +	if (!sn_irq_lh)
   6.438 +		panic("SN PCI INIT: Failed to allocate memory for PCI init\n");
   6.439 +
   6.440 +	for (i = 0; i < NR_IRQS; i++) {
   6.441 +		sn_irq_lh[i] = kmalloc(sizeof(struct list_head), GFP_KERNEL);
   6.442 +		if (!sn_irq_lh[i])
   6.443 +			panic("SN PCI INIT: Failed IRQ memory allocation\n");
   6.444 +
   6.445 +		INIT_LIST_HEAD(sn_irq_lh[i]);
   6.446 +	}
   6.447 +}

     7.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     7.2 +++ b/xen/arch/ia64/linux-xen/sn/kernel/setup.c	Wed Dec 13 11:08:40 2006 -0700
     7.3 @@ -0,0 +1,755 @@
     7.4 +/*
     7.5 + * This file is subject to the terms and conditions of the GNU General Public
     7.6 + * License.  See the file "COPYING" in the main directory of this archive
     7.7 + * for more details.
     7.8 + *
     7.9 + * Copyright (C) 1999,2001-2006 Silicon Graphics, Inc. All rights reserved.
    7.10 + */
    7.11 +
    7.12 +#include <linux/module.h>
    7.13 +#include <linux/init.h>
    7.14 +#include <linux/delay.h>
    7.15 +#include <linux/kernel.h>
    7.16 +#include <linux/kdev_t.h>
    7.17 +#include <linux/string.h>
    7.18 +#include <linux/screen_info.h>
    7.19 +#include <linux/console.h>
    7.20 +#include <linux/timex.h>
    7.21 +#include <linux/sched.h>
    7.22 +#include <linux/ioport.h>
    7.23 +#include <linux/mm.h>
    7.24 +#include <linux/serial.h>
    7.25 +#include <linux/irq.h>
    7.26 +#include <linux/bootmem.h>
    7.27 +#include <linux/mmzone.h>
    7.28 +#include <linux/interrupt.h>
    7.29 +#include <linux/acpi.h>
    7.30 +#include <linux/compiler.h>
    7.31 +#include <linux/sched.h>
    7.32 +#include <linux/root_dev.h>
    7.33 +#include <linux/nodemask.h>
    7.34 +#include <linux/pm.h>
    7.35 +#include <linux/efi.h>
    7.36 +
    7.37 +#include <asm/io.h>
    7.38 +#include <asm/sal.h>
    7.39 +#include <asm/machvec.h>
    7.40 +#include <asm/system.h>
    7.41 +#include <asm/processor.h>
    7.42 +#include <asm/vga.h>
    7.43 +#include <asm/sn/arch.h>
    7.44 +#include <asm/sn/addrs.h>
    7.45 +#include <asm/sn/pda.h>
    7.46 +#include <asm/sn/nodepda.h>
    7.47 +#include <asm/sn/sn_cpuid.h>
    7.48 +#include <asm/sn/simulator.h>
    7.49 +#include <asm/sn/leds.h>
    7.50 +#include <asm/sn/bte.h>
    7.51 +#include <asm/sn/shub_mmr.h>
    7.52 +#include <asm/sn/clksupport.h>
    7.53 +#include <asm/sn/sn_sal.h>
    7.54 +#include <asm/sn/geo.h>
    7.55 +#include <asm/sn/sn_feature_sets.h>
    7.56 +#include "xtalk/xwidgetdev.h"
    7.57 +#include "xtalk/hubdev.h"
    7.58 +#include <asm/sn/klconfig.h>
    7.59 +
    7.60 +
    7.61 +DEFINE_PER_CPU(struct pda_s, pda_percpu);
    7.62 +
    7.63 +#define MAX_PHYS_MEMORY		(1UL << IA64_MAX_PHYS_BITS)	/* Max physical address supported */
    7.64 +
    7.65 +extern void bte_init_node(nodepda_t *, cnodeid_t);
    7.66 +
    7.67 +extern void sn_timer_init(void);
    7.68 +extern unsigned long last_time_offset;
    7.69 +extern void (*ia64_mark_idle) (int);
    7.70 +extern void snidle(int);
    7.71 +extern unsigned long long (*ia64_printk_clock)(void);
    7.72 +
    7.73 +unsigned long sn_rtc_cycles_per_second;
    7.74 +EXPORT_SYMBOL(sn_rtc_cycles_per_second);
    7.75 +
    7.76 +DEFINE_PER_CPU(struct sn_hub_info_s, __sn_hub_info);
    7.77 +EXPORT_PER_CPU_SYMBOL(__sn_hub_info);
    7.78 +
    7.79 +DEFINE_PER_CPU(short, __sn_cnodeid_to_nasid[MAX_COMPACT_NODES]);
    7.80 +EXPORT_PER_CPU_SYMBOL(__sn_cnodeid_to_nasid);
    7.81 +
    7.82 +DEFINE_PER_CPU(struct nodepda_s *, __sn_nodepda);
    7.83 +EXPORT_PER_CPU_SYMBOL(__sn_nodepda);
    7.84 +
    7.85 +char sn_system_serial_number_string[128];
    7.86 +EXPORT_SYMBOL(sn_system_serial_number_string);
    7.87 +u64 sn_partition_serial_number;
    7.88 +EXPORT_SYMBOL(sn_partition_serial_number);
    7.89 +u8 sn_partition_id;
    7.90 +EXPORT_SYMBOL(sn_partition_id);
    7.91 +u8 sn_system_size;
    7.92 +EXPORT_SYMBOL(sn_system_size);
    7.93 +u8 sn_sharing_domain_size;
    7.94 +EXPORT_SYMBOL(sn_sharing_domain_size);
    7.95 +u8 sn_coherency_id;
    7.96 +EXPORT_SYMBOL(sn_coherency_id);
    7.97 +u8 sn_region_size;
    7.98 +EXPORT_SYMBOL(sn_region_size);
    7.99 +int sn_prom_type;	/* 0=hardware, 1=medusa/realprom, 2=medusa/fakeprom */
   7.100 +
   7.101 +short physical_node_map[MAX_NUMALINK_NODES];
   7.102 +static unsigned long sn_prom_features[MAX_PROM_FEATURE_SETS];
   7.103 +
   7.104 +EXPORT_SYMBOL(physical_node_map);
   7.105 +
   7.106 +int num_cnodes;
   7.107 +
   7.108 +static void sn_init_pdas(char **);
   7.109 +static void build_cnode_tables(void);
   7.110 +
   7.111 +static nodepda_t *nodepdaindr[MAX_COMPACT_NODES];
   7.112 +
   7.113 +/*
   7.114 + * The format of "screen_info" is strange, and due to early i386-setup
   7.115 + * code. This is just enough to make the console code think we're on a
   7.116 + * VGA color display.
   7.117 + */
   7.118 +struct screen_info sn_screen_info = {
   7.119 +	.orig_x = 0,
   7.120 +	.orig_y = 0,
   7.121 +	.orig_video_mode = 3,
   7.122 +	.orig_video_cols = 80,
   7.123 +	.orig_video_ega_bx = 3,
   7.124 +	.orig_video_lines = 25,
   7.125 +	.orig_video_isVGA = 1,
   7.126 +	.orig_video_points = 16
   7.127 +};
   7.128 +
   7.129 +/*
   7.130 + * This routine can only be used during init, since
   7.131 + * smp_boot_data is an init data structure.
   7.132 + * We have to use smp_boot_data.cpu_phys_id to find
   7.133 + * the physical id of the processor because the normal
   7.134 + * cpu_physical_id() relies on data structures that
   7.135 + * may not be initialized yet.
   7.136 + */
   7.137 +
   7.138 +static int __init pxm_to_nasid(int pxm)
   7.139 +{
   7.140 +	int i;
   7.141 +	int nid;
   7.142 +
   7.143 +	nid = pxm_to_node(pxm);
   7.144 +	for (i = 0; i < num_node_memblks; i++) {
   7.145 +		if (node_memblk[i].nid == nid) {
   7.146 +			return NASID_GET(node_memblk[i].start_paddr);
   7.147 +		}
   7.148 +	}
   7.149 +	return -1;
   7.150 +}
   7.151 +
   7.152 +/**
   7.153 + * early_sn_setup - early setup routine for SN platforms
   7.154 + *
   7.155 + * Sets up an initial console to aid debugging.  Intended primarily
   7.156 + * for bringup.  See start_kernel() in init/main.c.
   7.157 + */
   7.158 +
   7.159 +void __init early_sn_setup(void)
   7.160 +{
   7.161 +	efi_system_table_t *efi_systab;
   7.162 +	efi_config_table_t *config_tables;
   7.163 +	struct ia64_sal_systab *sal_systab;
   7.164 +	struct ia64_sal_desc_entry_point *ep;
   7.165 +	char *p;
   7.166 +	int i, j;
   7.167 +
   7.168 +	/*
   7.169 +	 * Parse enough of the SAL tables to locate the SAL entry point. Since, console
   7.170 +	 * IO on SN2 is done via SAL calls, early_printk won't work without this.
   7.171 +	 *
   7.172 +	 * This code duplicates some of the ACPI table parsing that is in efi.c & sal.c.
   7.173 +	 * Any changes to those file may have to be made hereas well.
   7.174 +	 */
   7.175 +	efi_systab = (efi_system_table_t *) __va(ia64_boot_param->efi_systab);
   7.176 +	config_tables = __va(efi_systab->tables);
   7.177 +	for (i = 0; i < efi_systab->nr_tables; i++) {
   7.178 +		if (efi_guidcmp(config_tables[i].guid, SAL_SYSTEM_TABLE_GUID) ==
   7.179 +		    0) {
   7.180 +			sal_systab = __va(config_tables[i].table);
   7.181 +			p = (char *)(sal_systab + 1);
   7.182 +			for (j = 0; j < sal_systab->entry_count; j++) {
   7.183 +				if (*p == SAL_DESC_ENTRY_POINT) {
   7.184 +					ep = (struct ia64_sal_desc_entry_point
   7.185 +					      *)p;
   7.186 +					ia64_sal_handler_init(__va
   7.187 +							      (ep->sal_proc),
   7.188 +							      __va(ep->gp));
   7.189 +					return;
   7.190 +				}
   7.191 +				p += SAL_DESC_SIZE(*p);
   7.192 +			}
   7.193 +		}
   7.194 +	}
   7.195 +	/* Uh-oh, SAL not available?? */
   7.196 +	printk(KERN_ERR "failed to find SAL entry point\n");
   7.197 +}
   7.198 +
   7.199 +extern int platform_intr_list[];
   7.200 +static int __initdata shub_1_1_found;
   7.201 +
   7.202 +/*
   7.203 + * sn_check_for_wars
   7.204 + *
   7.205 + * Set flag for enabling shub specific wars
   7.206 + */
   7.207 +
   7.208 +static inline int __init is_shub_1_1(int nasid)
   7.209 +{
   7.210 +	unsigned long id;
   7.211 +	int rev;
   7.212 +
   7.213 +	if (is_shub2())
   7.214 +		return 0;
   7.215 +	id = REMOTE_HUB_L(nasid, SH1_SHUB_ID);
   7.216 +	rev = (id & SH1_SHUB_ID_REVISION_MASK) >> SH1_SHUB_ID_REVISION_SHFT;
   7.217 +	return rev <= 2;
   7.218 +}
   7.219 +
   7.220 +static void __init sn_check_for_wars(void)
   7.221 +{
   7.222 +	int cnode;
   7.223 +
   7.224 +	if (is_shub2()) {
   7.225 +		/* none yet */
   7.226 +	} else {
   7.227 +		for_each_online_node(cnode) {
   7.228 +			if (is_shub_1_1(cnodeid_to_nasid(cnode)))
   7.229 +				shub_1_1_found = 1;
   7.230 +		}
   7.231 +	}
   7.232 +}
   7.233 +
   7.234 +/*
   7.235 + * Scan the EFI PCDP table (if it exists) for an acceptable VGA console
   7.236 + * output device.  If one exists, pick it and set sn_legacy_{io,mem} to
   7.237 + * reflect the bus offsets needed to address it.
   7.238 + *
   7.239 + * Since pcdp support in SN is not supported in the 2.4 kernel (or at least
   7.240 + * the one lbs is based on) just declare the needed structs here.
   7.241 + *
   7.242 + * Reference spec http://www.dig64.org/specifications/DIG64_PCDPv20.pdf
   7.243 + *
   7.244 + * Returns 0 if no acceptable vga is found, !0 otherwise.
   7.245 + *
   7.246 + * Note:  This stuff is duped here because Altix requires the PCDP to
   7.247 + * locate a usable VGA device due to lack of proper ACPI support.  Structures
   7.248 + * could be used from drivers/firmware/pcdp.h, but it was decided that moving
   7.249 + * this file to a more public location just for Altix use was undesireable.
   7.250 + */
   7.251 +
   7.252 +struct hcdp_uart_desc {
   7.253 +	u8	pad[45];
   7.254 +};
   7.255 +
   7.256 +struct pcdp {
   7.257 +	u8	signature[4];	/* should be 'HCDP' */
   7.258 +	u32	length;
   7.259 +	u8	rev;		/* should be >=3 for pcdp, <3 for hcdp */
   7.260 +	u8	sum;
   7.261 +	u8	oem_id[6];
   7.262 +	u64	oem_tableid;
   7.263 +	u32	oem_rev;
   7.264 +	u32	creator_id;
   7.265 +	u32	creator_rev;
   7.266 +	u32	num_type0;
   7.267 +	struct hcdp_uart_desc uart[0];	/* num_type0 of these */
   7.268 +	/* pcdp descriptors follow */
   7.269 +}  __attribute__((packed));
   7.270 +
   7.271 +struct pcdp_device_desc {
   7.272 +	u8	type;
   7.273 +	u8	primary;
   7.274 +	u16	length;
   7.275 +	u16	index;
   7.276 +	/* interconnect specific structure follows */
   7.277 +	/* device specific structure follows that */
   7.278 +}  __attribute__((packed));
   7.279 +
   7.280 +struct pcdp_interface_pci {
   7.281 +	u8	type;		/* 1 == pci */
   7.282 +	u8	reserved;
   7.283 +	u16	length;
   7.284 +	u8	segment;
   7.285 +	u8	bus;
   7.286 +	u8 	dev;
   7.287 +	u8	fun;
   7.288 +	u16	devid;
   7.289 +	u16	vendid;
   7.290 +	u32	acpi_interrupt;
   7.291 +	u64	mmio_tra;
   7.292 +	u64	ioport_tra;
   7.293 +	u8	flags;
   7.294 +	u8	translation;
   7.295 +}  __attribute__((packed));
   7.296 +
   7.297 +struct pcdp_vga_device {
   7.298 +	u8	num_eas_desc;
   7.299 +	/* ACPI Extended Address Space Desc follows */
   7.300 +}  __attribute__((packed));
   7.301 +
   7.302 +/* from pcdp_device_desc.primary */
   7.303 +#define PCDP_PRIMARY_CONSOLE	0x01
   7.304 +
   7.305 +/* from pcdp_device_desc.type */
   7.306 +#define PCDP_CONSOLE_INOUT	0x0
   7.307 +#define PCDP_CONSOLE_DEBUG	0x1
   7.308 +#define PCDP_CONSOLE_OUT	0x2
   7.309 +#define PCDP_CONSOLE_IN		0x3
   7.310 +#define PCDP_CONSOLE_TYPE_VGA	0x8
   7.311 +
   7.312 +#define PCDP_CONSOLE_VGA	(PCDP_CONSOLE_TYPE_VGA | PCDP_CONSOLE_OUT)
   7.313 +
   7.314 +/* from pcdp_interface_pci.type */
   7.315 +#define PCDP_IF_PCI		1
   7.316 +
   7.317 +/* from pcdp_interface_pci.translation */
   7.318 +#define PCDP_PCI_TRANS_IOPORT	0x02
   7.319 +#define PCDP_PCI_TRANS_MMIO	0x01
   7.320 +
   7.321 +#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
   7.322 +static void
   7.323 +sn_scan_pcdp(void)
   7.324 +{
   7.325 +	u8 *bp;
   7.326 +	struct pcdp *pcdp;
   7.327 +	struct pcdp_device_desc device;
   7.328 +	struct pcdp_interface_pci if_pci;
   7.329 +	extern struct efi efi;
   7.330 +
   7.331 +	if (efi.hcdp == EFI_INVALID_TABLE_ADDR)
   7.332 +		return;		/* no hcdp/pcdp table */
   7.333 +
   7.334 +	pcdp = __va(efi.hcdp);
   7.335 +
   7.336 +	if (pcdp->rev < 3)
   7.337 +		return;		/* only support PCDP (rev >= 3) */
   7.338 +
   7.339 +	for (bp = (u8 *)&pcdp->uart[pcdp->num_type0];
   7.340 +	     bp < (u8 *)pcdp + pcdp->length;
   7.341 +	     bp += device.length) {
   7.342 +		memcpy(&device, bp, sizeof(device));
   7.343 +		if (! (device.primary & PCDP_PRIMARY_CONSOLE))
   7.344 +			continue;	/* not primary console */
   7.345 +
   7.346 +		if (device.type != PCDP_CONSOLE_VGA)
   7.347 +			continue;	/* not VGA descriptor */
   7.348 +
   7.349 +		memcpy(&if_pci, bp+sizeof(device), sizeof(if_pci));
   7.350 +		if (if_pci.type != PCDP_IF_PCI)
   7.351 +			continue;	/* not PCI interconnect */
   7.352 +
   7.353 +		if (if_pci.translation & PCDP_PCI_TRANS_IOPORT)
   7.354 +			vga_console_iobase =
   7.355 +				if_pci.ioport_tra | __IA64_UNCACHED_OFFSET;
   7.356 +
   7.357 +		if (if_pci.translation & PCDP_PCI_TRANS_MMIO)
   7.358 +			vga_console_membase =
   7.359 +				if_pci.mmio_tra | __IA64_UNCACHED_OFFSET;
   7.360 +
   7.361 +		break; /* once we find the primary, we're done */
   7.362 +	}
   7.363 +}
   7.364 +#endif
   7.365 +
   7.366 +static unsigned long sn2_rtc_initial;
   7.367 +
   7.368 +static unsigned long long ia64_sn2_printk_clock(void)
   7.369 +{
   7.370 +	unsigned long rtc_now = rtc_time();
   7.371 +
   7.372 +	return (rtc_now - sn2_rtc_initial) *
   7.373 +		(1000000000 / sn_rtc_cycles_per_second);
   7.374 +}
   7.375 +
   7.376 +/**
   7.377 + * sn_setup - SN platform setup routine
   7.378 + * @cmdline_p: kernel command line
   7.379 + *
   7.380 + * Handles platform setup for SN machines.  This includes determining
   7.381 + * the RTC frequency (via a SAL call), initializing secondary CPUs, and
   7.382 + * setting up per-node data areas.  The console is also initialized here.
   7.383 + */
   7.384 +void __init sn_setup(char **cmdline_p)
   7.385 +{
   7.386 +	long status, ticks_per_sec, drift;
   7.387 +	u32 version = sn_sal_rev();
   7.388 +	extern void sn_cpu_init(void);
   7.389 +
   7.390 +	sn2_rtc_initial = rtc_time();
   7.391 +	ia64_sn_plat_set_error_handling_features();	// obsolete
   7.392 +	ia64_sn_set_os_feature(OSF_MCA_SLV_TO_OS_INIT_SLV);
   7.393 +	ia64_sn_set_os_feature(OSF_FEAT_LOG_SBES);
   7.394 +
   7.395 +
   7.396 +#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
   7.397 +	/*
   7.398 +	 * Handle SN vga console.
   7.399 +	 *
   7.400 +	 * SN systems do not have enough ACPI table information
   7.401 +	 * being passed from prom to identify VGA adapters and the legacy
   7.402 +	 * addresses to access them.  Until that is done, SN systems rely
   7.403 +	 * on the PCDP table to identify the primary VGA console if one
   7.404 +	 * exists.
   7.405 +	 *
   7.406 +	 * However, kernel PCDP support is optional, and even if it is built
   7.407 +	 * into the kernel, it will not be used if the boot cmdline contains
   7.408 +	 * console= directives.
   7.409 +	 *
   7.410 +	 * So, to work around this mess, we duplicate some of the PCDP code
   7.411 +	 * here so that the primary VGA console (as defined by PCDP) will
   7.412 +	 * work on SN systems even if a different console (e.g. serial) is
   7.413 +	 * selected on the boot line (or CONFIG_EFI_PCDP is off).
   7.414 +	 */
   7.415 +
   7.416 +	if (! vga_console_membase)
   7.417 +		sn_scan_pcdp();
   7.418 +
   7.419 +	if (vga_console_membase) {
   7.420 +		/* usable vga ... make tty0 the preferred default console */
   7.421 +		if (!strstr(*cmdline_p, "console="))
   7.422 +			add_preferred_console("tty", 0, NULL);
   7.423 +	} else {
   7.424 +		printk(KERN_DEBUG "SGI: Disabling VGA console\n");
   7.425 +		if (!strstr(*cmdline_p, "console="))
   7.426 +			add_preferred_console("ttySG", 0, NULL);
   7.427 +#ifdef CONFIG_DUMMY_CONSOLE
   7.428 +		conswitchp = &dummy_con;
   7.429 +#else
   7.430 +		conswitchp = NULL;
   7.431 +#endif				/* CONFIG_DUMMY_CONSOLE */
   7.432 +	}
   7.433 +#endif				/* def(CONFIG_VT) && def(CONFIG_VGA_CONSOLE) */
   7.434 +
   7.435 +	MAX_DMA_ADDRESS = PAGE_OFFSET + MAX_PHYS_MEMORY;
   7.436 +
   7.437 +	/*
   7.438 +	 * Build the tables for managing cnodes.
   7.439 +	 */
   7.440 +	build_cnode_tables();
   7.441 +
   7.442 +	status =
   7.443 +	    ia64_sal_freq_base(SAL_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec,
   7.444 +			       &drift);
   7.445 +	if (status != 0 || ticks_per_sec < 100000) {
   7.446 +		printk(KERN_WARNING
   7.447 +		       "unable to determine platform RTC clock frequency, guessing.\n");
   7.448 +		/* PROM gives wrong value for clock freq. so guess */
   7.449 +		sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
   7.450 +	} else
   7.451 +		sn_rtc_cycles_per_second = ticks_per_sec;
   7.452 +
   7.453 +	platform_intr_list[ACPI_INTERRUPT_CPEI] = IA64_CPE_VECTOR;
   7.454 +
   7.455 +	ia64_printk_clock = ia64_sn2_printk_clock;
   7.456 +
   7.457 +	printk("SGI SAL version %x.%02x\n", version >> 8, version & 0x00FF);
   7.458 +
   7.459 +	/*
   7.460 +	 * we set the default root device to /dev/hda
   7.461 +	 * to make simulation easy
   7.462 +	 */
   7.463 +	ROOT_DEV = Root_HDA1;
   7.464 +
   7.465 +	/*
   7.466 +	 * Create the PDAs and NODEPDAs for all the cpus.
   7.467 +	 */
   7.468 +	sn_init_pdas(cmdline_p);
   7.469 +
   7.470 +	ia64_mark_idle = &snidle;
   7.471 +
   7.472 +	/*
   7.473 +	 * For the bootcpu, we do this here. All other cpus will make the
   7.474 +	 * call as part of cpu_init in slave cpu initialization.
   7.475 +	 */
   7.476 +	sn_cpu_init();
   7.477 +
   7.478 +#ifdef CONFIG_SMP
   7.479 +	init_smp_config();
   7.480 +#endif
   7.481 +	screen_info = sn_screen_info;
   7.482 +
   7.483 +	sn_timer_init();
   7.484 +
   7.485 +	/*
   7.486 +	 * set pm_power_off to a SAL call to allow
   7.487 +	 * sn machines to power off. The SAL call can be replaced
   7.488 +	 * by an ACPI interface call when ACPI is fully implemented
   7.489 +	 * for sn.
   7.490 +	 */
   7.491 +	pm_power_off = ia64_sn_power_down;
   7.492 +	current->thread.flags |= IA64_THREAD_MIGRATION;
   7.493 +}
   7.494 +
   7.495 +/**
   7.496 + * sn_init_pdas - setup node data areas
   7.497 + *
   7.498 + * One time setup for Node Data Area.  Called by sn_setup().
   7.499 + */
   7.500 +static void __init sn_init_pdas(char **cmdline_p)
   7.501 +{
   7.502 +	cnodeid_t cnode;
   7.503 +
   7.504 +	/*
   7.505 +	 * Allocate & initalize the nodepda for each node.
   7.506 +	 */
   7.507 +	for_each_online_node(cnode) {
   7.508 +		nodepdaindr[cnode] =
   7.509 +		    alloc_bootmem_node(NODE_DATA(cnode), sizeof(nodepda_t));
   7.510 +		memset(nodepdaindr[cnode], 0, sizeof(nodepda_t));
   7.511 +		memset(nodepdaindr[cnode]->phys_cpuid, -1,
   7.512 +		    sizeof(nodepdaindr[cnode]->phys_cpuid));
   7.513 +		spin_lock_init(&nodepdaindr[cnode]->ptc_lock);
   7.514 +	}
   7.515 +
   7.516 +	/*
   7.517 +	 * Allocate & initialize nodepda for TIOs.  For now, put them on node 0.
   7.518 +	 */
   7.519 +	for (cnode = num_online_nodes(); cnode < num_cnodes; cnode++) {
   7.520 +		nodepdaindr[cnode] =
   7.521 +		    alloc_bootmem_node(NODE_DATA(0), sizeof(nodepda_t));
   7.522 +		memset(nodepdaindr[cnode], 0, sizeof(nodepda_t));
   7.523 +	}
   7.524 +
   7.525 +	/*
   7.526 +	 * Now copy the array of nodepda pointers to each nodepda.
   7.527 +	 */
   7.528 +	for (cnode = 0; cnode < num_cnodes; cnode++)
   7.529 +		memcpy(nodepdaindr[cnode]->pernode_pdaindr, nodepdaindr,
   7.530 +		       sizeof(nodepdaindr));
   7.531 +
   7.532 +	/*
   7.533 +	 * Set up IO related platform-dependent nodepda fields.
   7.534 +	 * The following routine actually sets up the hubinfo struct
   7.535 +	 * in nodepda.
   7.536 +	 */
   7.537 +	for_each_online_node(cnode) {
   7.538 +		bte_init_node(nodepdaindr[cnode], cnode);
   7.539 +	}
   7.540 +
   7.541 +	/*
   7.542 +	 * Initialize the per node hubdev.  This includes IO Nodes and
   7.543 +	 * headless/memless nodes.
   7.544 +	 */
   7.545 +	for (cnode = 0; cnode < num_cnodes; cnode++) {
   7.546 +		hubdev_init_node(nodepdaindr[cnode], cnode);
   7.547 +	}
   7.548 +}
   7.549 +
   7.550 +/**
   7.551 + * sn_cpu_init - initialize per-cpu data areas
   7.552 + * @cpuid: cpuid of the caller
   7.553 + *
   7.554 + * Called during cpu initialization on each cpu as it starts.
   7.555 + * Currently, initializes the per-cpu data area for SNIA.
   7.556 + * Also sets up a few fields in the nodepda.  Also known as
   7.557 + * platform_cpu_init() by the ia64 machvec code.
   7.558 + */
   7.559 +void __cpuinit sn_cpu_init(void)
   7.560 +{
   7.561 +	int cpuid;
   7.562 +	int cpuphyid;
   7.563 +	int nasid;
   7.564 +	int subnode;
   7.565 +	int slice;
   7.566 +	int cnode;
   7.567 +	int i;
   7.568 +	static int wars_have_been_checked;
   7.569 +
   7.570 +	cpuid = smp_processor_id();
   7.571 +	if (cpuid == 0 && IS_MEDUSA()) {
   7.572 +		if (ia64_sn_is_fake_prom())
   7.573 +			sn_prom_type = 2;
   7.574 +		else
   7.575 +			sn_prom_type = 1;
   7.576 +		printk(KERN_INFO "Running on medusa with %s PROM\n",
   7.577 +		       (sn_prom_type == 1) ? "real" : "fake");
   7.578 +	}
   7.579 +
   7.580 +	memset(pda, 0, sizeof(pda));
   7.581 +	if (ia64_sn_get_sn_info(0, &sn_hub_info->shub2,
   7.582 +				&sn_hub_info->nasid_bitmask,
   7.583 +				&sn_hub_info->nasid_shift,
   7.584 +				&sn_system_size, &sn_sharing_domain_size,
   7.585 +				&sn_partition_id, &sn_coherency_id,
   7.586 +				&sn_region_size))
   7.587 +		BUG();
   7.588 +	sn_hub_info->as_shift = sn_hub_info->nasid_shift - 2;
   7.589 +
   7.590 +	/*
   7.591 +	 * Don't check status. The SAL call is not supported on all PROMs
   7.592 +	 * but a failure is harmless.
   7.593 +	 */
   7.594 +	(void) ia64_sn_set_cpu_number(cpuid);
   7.595 +
   7.596 +	/*
   7.597 +	 * The boot cpu makes this call again after platform initialization is
   7.598 +	 * complete.
   7.599 +	 */
   7.600 +	if (nodepdaindr[0] == NULL)
   7.601 +		return;
   7.602 +
   7.603 +	for (i = 0; i < MAX_PROM_FEATURE_SETS; i++)
   7.604 +		if (ia64_sn_get_prom_feature_set(i, &sn_prom_features[i]) != 0)
   7.605 +			break;
   7.606 +
   7.607 +	cpuphyid = get_sapicid();
   7.608 +
   7.609 +	if (ia64_sn_get_sapic_info(cpuphyid, &nasid, &subnode, &slice))
   7.610 +		BUG();
   7.611 +
   7.612 +	for (i=0; i < MAX_NUMNODES; i++) {
   7.613 +		if (nodepdaindr[i]) {
   7.614 +			nodepdaindr[i]->phys_cpuid[cpuid].nasid = nasid;
   7.615 +			nodepdaindr[i]->phys_cpuid[cpuid].slice = slice;
   7.616 +			nodepdaindr[i]->phys_cpuid[cpuid].subnode = subnode;
   7.617 +		}
   7.618 +	}
   7.619 +
   7.620 +	cnode = nasid_to_cnodeid(nasid);
   7.621 +
   7.622 +	sn_nodepda = nodepdaindr[cnode];
   7.623 +
   7.624 +	pda->led_address =
   7.625 +	    (typeof(pda->led_address)) (LED0 + (slice << LED_CPU_SHIFT));
   7.626 +	pda->led_state = LED_ALWAYS_SET;
   7.627 +	pda->hb_count = HZ / 2;
   7.628 +	pda->hb_state = 0;
   7.629 +	pda->idle_flag = 0;
   7.630 +
   7.631 +	if (cpuid != 0) {
   7.632 +		/* copy cpu 0's sn_cnodeid_to_nasid table to this cpu's */
   7.633 +		memcpy(sn_cnodeid_to_nasid,
   7.634 +		       (&per_cpu(__sn_cnodeid_to_nasid, 0)),
   7.635 +		       sizeof(__ia64_per_cpu_var(__sn_cnodeid_to_nasid)));
   7.636 +	}
   7.637 +
   7.638 +	/*
   7.639 +	 * Check for WARs.
   7.640 +	 * Only needs to be done once, on BSP.
   7.641 +	 * Has to be done after loop above, because it uses this cpu's
   7.642 +	 * sn_cnodeid_to_nasid table which was just initialized if this
   7.643 +	 * isn't cpu 0.
   7.644 +	 * Has to be done before assignment below.
   7.645 +	 */
   7.646 +	if (!wars_have_been_checked) {
   7.647 +		sn_check_for_wars();
   7.648 +		wars_have_been_checked = 1;
   7.649 +	}
   7.650 +	sn_hub_info->shub_1_1_found = shub_1_1_found;
   7.651 +
   7.652 +	/*
   7.653 +	 * Set up addresses of PIO/MEM write status registers.
   7.654 +	 */
   7.655 +	{
   7.656 +		u64 pio1[] = {SH1_PIO_WRITE_STATUS_0, 0, SH1_PIO_WRITE_STATUS_1, 0};
   7.657 +		u64 pio2[] = {SH2_PIO_WRITE_STATUS_0, SH2_PIO_WRITE_STATUS_2,
   7.658 +			SH2_PIO_WRITE_STATUS_1, SH2_PIO_WRITE_STATUS_3};
   7.659 +		u64 *pio;
   7.660 +		pio = is_shub1() ? pio1 : pio2;
   7.661 +		pda->pio_write_status_addr =
   7.662 +		   (volatile unsigned long *)GLOBAL_MMR_ADDR(nasid, pio[slice]);
   7.663 +		pda->pio_write_status_val = is_shub1() ? SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK : 0;
   7.664 +	}
   7.665 +
   7.666 +	/*
   7.667 +	 * WAR addresses for SHUB 1.x.
   7.668 +	 */
   7.669 +	if (local_node_data->active_cpu_count++ == 0 && is_shub1()) {
   7.670 +		int buddy_nasid;
   7.671 +		buddy_nasid =
   7.672 +		    cnodeid_to_nasid(numa_node_id() ==
   7.673 +				     num_online_nodes() - 1 ? 0 : numa_node_id() + 1);
   7.674 +		pda->pio_shub_war_cam_addr =
   7.675 +		    (volatile unsigned long *)GLOBAL_MMR_ADDR(nasid,
   7.676 +							      SH1_PI_CAM_CONTROL);
   7.677 +	}
   7.678 +}
   7.679 +
   7.680 +/*
   7.681 + * Build tables for converting between NASIDs and cnodes.
   7.682 + */
   7.683 +static inline int __init board_needs_cnode(int type)
   7.684 +{
   7.685 +	return (type == KLTYPE_SNIA || type == KLTYPE_TIO);
   7.686 +}
   7.687 +
   7.688 +void __init build_cnode_tables(void)
   7.689 +{
   7.690 +	int nasid;
   7.691 +	int node;
   7.692 +	lboard_t *brd;
   7.693 +
   7.694 +	memset(physical_node_map, -1, sizeof(physical_node_map));
   7.695 +	memset(sn_cnodeid_to_nasid, -1,
   7.696 +			sizeof(__ia64_per_cpu_var(__sn_cnodeid_to_nasid)));
   7.697 +
   7.698 +	/*
   7.699 +	 * First populate the tables with C/M bricks. This ensures that
   7.700 +	 * cnode == node for all C & M bricks.
   7.701 +	 */
   7.702 +	for_each_online_node(node) {
   7.703 +		nasid = pxm_to_nasid(node_to_pxm(node));
   7.704 +		sn_cnodeid_to_nasid[node] = nasid;
   7.705 +		physical_node_map[nasid] = node;
   7.706 +	}
   7.707 +
   7.708 +	/*
   7.709 +	 * num_cnodes is total number of C/M/TIO bricks. Because of the 256 node
   7.710 +	 * limit on the number of nodes, we can't use the generic node numbers 
   7.711 +	 * for this. Note that num_cnodes is incremented below as TIOs or
   7.712 +	 * headless/memoryless nodes are discovered.
   7.713 +	 */
   7.714 +	num_cnodes = num_online_nodes();
   7.715 +
   7.716 +	/* fakeprom does not support klgraph */
   7.717 +	if (IS_RUNNING_ON_FAKE_PROM())
   7.718 +		return;
   7.719 +
   7.720 +	/* Find TIOs & headless/memoryless nodes and add them to the tables */
   7.721 +	for_each_online_node(node) {
   7.722 +		kl_config_hdr_t *klgraph_header;
   7.723 +		nasid = cnodeid_to_nasid(node);
   7.724 +		klgraph_header = ia64_sn_get_klconfig_addr(nasid);
   7.725 +		if (klgraph_header == NULL)
   7.726 +			BUG();
   7.727 +		brd = NODE_OFFSET_TO_LBOARD(nasid, klgraph_header->ch_board_info);
   7.728 +		while (brd) {
   7.729 +			if (board_needs_cnode(brd->brd_type) && physical_node_map[brd->brd_nasid] < 0) {
   7.730 +				sn_cnodeid_to_nasid[num_cnodes] = brd->brd_nasid;
   7.731 +				physical_node_map[brd->brd_nasid] = num_cnodes++;
   7.732 +			}
   7.733 +			brd = find_lboard_next(brd);
   7.734 +		}
   7.735 +	}
   7.736 +}
   7.737 +
   7.738 +int
   7.739 +nasid_slice_to_cpuid(int nasid, int slice)
   7.740 +{
   7.741 +	long cpu;
   7.742 +
   7.743 +	for (cpu = 0; cpu < NR_CPUS; cpu++)
   7.744 +		if (cpuid_to_nasid(cpu) == nasid &&
   7.745 +					cpuid_to_slice(cpu) == slice)
   7.746 +			return cpu;
   7.747 +
   7.748 +	return -1;
   7.749 +}
   7.750 +
   7.751 +int sn_prom_feature_available(int id)
   7.752 +{
   7.753 +	if (id >= BITS_PER_LONG * MAX_PROM_FEATURE_SETS)
   7.754 +		return 0;
   7.755 +	return test_bit(id, sn_prom_features);
   7.756 +}
   7.757 +EXPORT_SYMBOL(sn_prom_feature_available);
   7.758 +

     8.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     8.2 +++ b/xen/arch/ia64/linux-xen/sn/kernel/sn2_smp.c	Wed Dec 13 11:08:40 2006 -0700
     8.3 @@ -0,0 +1,489 @@
     8.4 +/*
     8.5 + * SN2 Platform specific SMP Support
     8.6 + *
     8.7 + * This file is subject to the terms and conditions of the GNU General Public
     8.8 + * License.  See the file "COPYING" in the main directory of this archive
     8.9 + * for more details.
    8.10 + *
    8.11 + * Copyright (C) 2000-2006 Silicon Graphics, Inc. All rights reserved.
    8.12 + */
    8.13 +
    8.14 +#include <linux/init.h>
    8.15 +#include <linux/kernel.h>
    8.16 +#include <linux/spinlock.h>
    8.17 +#include <linux/threads.h>
    8.18 +#include <linux/sched.h>
    8.19 +#include <linux/smp.h>
    8.20 +#include <linux/interrupt.h>
    8.21 +#include <linux/irq.h>
    8.22 +#include <linux/mmzone.h>
    8.23 +#include <linux/module.h>
    8.24 +#include <linux/bitops.h>
    8.25 +#include <linux/nodemask.h>
    8.26 +#include <linux/proc_fs.h>
    8.27 +#include <linux/seq_file.h>
    8.28 +
    8.29 +#include <asm/processor.h>
    8.30 +#include <asm/irq.h>
    8.31 +#include <asm/sal.h>
    8.32 +#include <asm/system.h>
    8.33 +#include <asm/delay.h>
    8.34 +#include <asm/io.h>
    8.35 +#include <asm/smp.h>
    8.36 +#include <asm/tlb.h>
    8.37 +#include <asm/numa.h>
    8.38 +#include <asm/hw_irq.h>
    8.39 +#include <asm/current.h>
    8.40 +#include <asm/sn/sn_cpuid.h>
    8.41 +#include <asm/sn/sn_sal.h>
    8.42 +#include <asm/sn/addrs.h>
    8.43 +#include <asm/sn/shub_mmr.h>
    8.44 +#include <asm/sn/nodepda.h>
    8.45 +#include <asm/sn/rw_mmr.h>
    8.46 +
    8.47 +DEFINE_PER_CPU(struct ptc_stats, ptcstats);
    8.48 +DECLARE_PER_CPU(struct ptc_stats, ptcstats);
    8.49 +
    8.50 +static  __cacheline_aligned DEFINE_SPINLOCK(sn2_global_ptc_lock);
    8.51 +
    8.52 +extern unsigned long
    8.53 +sn2_ptc_deadlock_recovery_core(volatile unsigned long *, unsigned long,
    8.54 +			       volatile unsigned long *, unsigned long,
    8.55 +			       volatile unsigned long *, unsigned long);
    8.56 +void
    8.57 +sn2_ptc_deadlock_recovery(short *, short, short, int,
    8.58 +			  volatile unsigned long *, unsigned long,
    8.59 +			  volatile unsigned long *, unsigned long);
    8.60 +
    8.61 +/*
    8.62 + * Note: some is the following is captured here to make degugging easier
    8.63 + * (the macros make more sense if you see the debug patch - not posted)
    8.64 + */
    8.65 +#define sn2_ptctest	0
    8.66 +#define local_node_uses_ptc_ga(sh1)	((sh1) ? 1 : 0)
    8.67 +#define max_active_pio(sh1)		((sh1) ? 32 : 7)
    8.68 +#define reset_max_active_on_deadlock()	1
    8.69 +#define PTC_LOCK(sh1)			((sh1) ? &sn2_global_ptc_lock : &sn_nodepda->ptc_lock)
    8.70 +
    8.71 +struct ptc_stats {
    8.72 +	unsigned long ptc_l;
    8.73 +	unsigned long change_rid;
    8.74 +	unsigned long shub_ptc_flushes;
    8.75 +	unsigned long nodes_flushed;
    8.76 +	unsigned long deadlocks;
    8.77 +	unsigned long deadlocks2;
    8.78 +	unsigned long lock_itc_clocks;
    8.79 +	unsigned long shub_itc_clocks;
    8.80 +	unsigned long shub_itc_clocks_max;
    8.81 +	unsigned long shub_ptc_flushes_not_my_mm;
    8.82 +};
    8.83 +
    8.84 +#define sn2_ptctest	0
    8.85 +
    8.86 +static inline unsigned long wait_piowc(void)
    8.87 +{
    8.88 +	volatile unsigned long *piows;
    8.89 +	unsigned long zeroval, ws;
    8.90 +
    8.91 +	piows = pda->pio_write_status_addr;
    8.92 +	zeroval = pda->pio_write_status_val;
    8.93 +	do {
    8.94 +		cpu_relax();
    8.95 +	} while (((ws = *piows) & SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK) != zeroval);
    8.96 +	return (ws & SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK) != 0;
    8.97 +}
    8.98 +
    8.99 +/**
   8.100 + * sn_migrate - SN-specific task migration actions
   8.101 + * @task: Task being migrated to new CPU
   8.102 + *
   8.103 + * SN2 PIO writes from separate CPUs are not guaranteed to arrive in order.
   8.104 + * Context switching user threads which have memory-mapped MMIO may cause
   8.105 + * PIOs to issue from seperate CPUs, thus the PIO writes must be drained
   8.106 + * from the previous CPU's Shub before execution resumes on the new CPU.
   8.107 + */
   8.108 +void sn_migrate(struct task_struct *task)
   8.109 +{
   8.110 +	pda_t *last_pda = pdacpu(task_thread_info(task)->last_cpu);
   8.111 +	volatile unsigned long *adr = last_pda->pio_write_status_addr;
   8.112 +	unsigned long val = last_pda->pio_write_status_val;
   8.113 +
   8.114 +	/* Drain PIO writes from old CPU's Shub */
   8.115 +	while (unlikely((*adr & SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK)
   8.116 +			!= val))
   8.117 +		cpu_relax();
   8.118 +}
   8.119 +
   8.120 +void sn_tlb_migrate_finish(struct mm_struct *mm)
   8.121 +{
   8.122 +	/* flush_tlb_mm is inefficient if more than 1 users of mm */
   8.123 +	if (mm == current->mm && mm && atomic_read(&mm->mm_users) == 1)
   8.124 +		flush_tlb_mm(mm);
   8.125 +}
   8.126 +
   8.127 +/**
   8.128 + * sn2_global_tlb_purge - globally purge translation cache of virtual address range
   8.129 + * @mm: mm_struct containing virtual address range
   8.130 + * @start: start of virtual address range
   8.131 + * @end: end of virtual address range
   8.132 + * @nbits: specifies number of bytes to purge per instruction (num = 1<<(nbits & 0xfc))
   8.133 + *
   8.134 + * Purges the translation caches of all processors of the given virtual address
   8.135 + * range.
   8.136 + *
   8.137 + * Note:
   8.138 + * 	- cpu_vm_mask is a bit mask that indicates which cpus have loaded the context.
   8.139 + * 	- cpu_vm_mask is converted into a nodemask of the nodes containing the
   8.140 + * 	  cpus in cpu_vm_mask.
   8.141 + *	- if only one bit is set in cpu_vm_mask & it is the current cpu & the
   8.142 + *	  process is purging its own virtual address range, then only the
   8.143 + *	  local TLB needs to be flushed. This flushing can be done using
   8.144 + *	  ptc.l. This is the common case & avoids the global spinlock.
   8.145 + *	- if multiple cpus have loaded the context, then flushing has to be
   8.146 + *	  done with ptc.g/MMRs under protection of the global ptc_lock.
   8.147 + */
   8.148 +
   8.149 +void
   8.150 +sn2_global_tlb_purge(struct mm_struct *mm, unsigned long start,
   8.151 +		     unsigned long end, unsigned long nbits)
   8.152 +{
   8.153 +	int i, ibegin, shub1, cnode, mynasid, cpu, lcpu = 0, nasid;
   8.154 +	int mymm = (mm == current->active_mm && mm == current->mm);
   8.155 +	int use_cpu_ptcga;
   8.156 +	volatile unsigned long *ptc0, *ptc1;
   8.157 +	unsigned long itc, itc2, flags, data0 = 0, data1 = 0, rr_value, old_rr = 0;
   8.158 +	short nasids[MAX_NUMNODES], nix;
   8.159 +	nodemask_t nodes_flushed;
   8.160 +	int active, max_active, deadlock;
   8.161 +
   8.162 +	nodes_clear(nodes_flushed);
   8.163 +	i = 0;
   8.164 +
   8.165 +	for_each_cpu_mask(cpu, mm->cpu_vm_mask) {
   8.166 +		cnode = cpu_to_node(cpu);
   8.167 +		node_set(cnode, nodes_flushed);
   8.168 +		lcpu = cpu;
   8.169 +		i++;
   8.170 +	}
   8.171 +
   8.172 +	if (i == 0)
   8.173 +		return;
   8.174 +
   8.175 +	preempt_disable();
   8.176 +
   8.177 +	if (likely(i == 1 && lcpu == smp_processor_id() && mymm)) {
   8.178 +		do {
   8.179 +			ia64_ptcl(start, nbits << 2);
   8.180 +			start += (1UL << nbits);
   8.181 +		} while (start < end);
   8.182 +		ia64_srlz_i();
   8.183 +		__get_cpu_var(ptcstats).ptc_l++;
   8.184 +		preempt_enable();
   8.185 +		return;
   8.186 +	}
   8.187 +
   8.188 +	if (atomic_read(&mm->mm_users) == 1 && mymm) {
   8.189 +		flush_tlb_mm(mm);
   8.190 +		__get_cpu_var(ptcstats).change_rid++;
   8.191 +		preempt_enable();
   8.192 +		return;
   8.193 +	}
   8.194 +
   8.195 +	itc = ia64_get_itc();
   8.196 +	nix = 0;
   8.197 +	for_each_node_mask(cnode, nodes_flushed)
   8.198 +		nasids[nix++] = cnodeid_to_nasid(cnode);
   8.199 +
   8.200 +	rr_value = (mm->context << 3) | REGION_NUMBER(start);
   8.201 +
   8.202 +	shub1 = is_shub1();
   8.203 +	if (shub1) {
   8.204 +		data0 = (1UL << SH1_PTC_0_A_SHFT) |
   8.205 +		    	(nbits << SH1_PTC_0_PS_SHFT) |
   8.206 +			(rr_value << SH1_PTC_0_RID_SHFT) |
   8.207 +		    	(1UL << SH1_PTC_0_START_SHFT);
   8.208 +		ptc0 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH1_PTC_0);
   8.209 +		ptc1 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH1_PTC_1);
   8.210 +	} else {
   8.211 +		data0 = (1UL << SH2_PTC_A_SHFT) |
   8.212 +			(nbits << SH2_PTC_PS_SHFT) |
   8.213 +		    	(1UL << SH2_PTC_START_SHFT);
   8.214 +		ptc0 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH2_PTC + 
   8.215 +			(rr_value << SH2_PTC_RID_SHFT));
   8.216 +		ptc1 = NULL;
   8.217 +	}
   8.218 +	
   8.219 +
   8.220 +	mynasid = get_nasid();
   8.221 +	use_cpu_ptcga = local_node_uses_ptc_ga(shub1);
   8.222 +	max_active = max_active_pio(shub1);
   8.223 +
   8.224 +	itc = ia64_get_itc();
   8.225 +	spin_lock_irqsave(PTC_LOCK(shub1), flags);
   8.226 +	itc2 = ia64_get_itc();
   8.227 +
   8.228 +	__get_cpu_var(ptcstats).lock_itc_clocks += itc2 - itc;
   8.229 +	__get_cpu_var(ptcstats).shub_ptc_flushes++;
   8.230 +	__get_cpu_var(ptcstats).nodes_flushed += nix;
   8.231 +	if (!mymm)
   8.232 +		 __get_cpu_var(ptcstats).shub_ptc_flushes_not_my_mm++;
   8.233 +
   8.234 +	if (use_cpu_ptcga && !mymm) {
   8.235 +		old_rr = ia64_get_rr(start);
   8.236 +		ia64_set_rr(start, (old_rr & 0xff) | (rr_value << 8));
   8.237 +		ia64_srlz_d();
   8.238 +	}
   8.239 +
   8.240 +	wait_piowc();
   8.241 +	do {
   8.242 +		if (shub1)
   8.243 +			data1 = start | (1UL << SH1_PTC_1_START_SHFT);
   8.244 +		else
   8.245 +			data0 = (data0 & ~SH2_PTC_ADDR_MASK) | (start & SH2_PTC_ADDR_MASK);
   8.246 +		deadlock = 0;
   8.247 +		active = 0;
   8.248 +		for (ibegin = 0, i = 0; i < nix; i++) {
   8.249 +			nasid = nasids[i];
   8.250 +			if (use_cpu_ptcga && unlikely(nasid == mynasid)) {
   8.251 +				ia64_ptcga(start, nbits << 2);
   8.252 +				ia64_srlz_i();
   8.253 +			} else {
   8.254 +				ptc0 = CHANGE_NASID(nasid, ptc0);
   8.255 +				if (ptc1)
   8.256 +					ptc1 = CHANGE_NASID(nasid, ptc1);
   8.257 +				pio_atomic_phys_write_mmrs(ptc0, data0, ptc1, data1);
   8.258 +				active++;
   8.259 +			}
   8.260 +			if (active >= max_active || i == (nix - 1)) {
   8.261 +				if ((deadlock = wait_piowc())) {
   8.262 +					sn2_ptc_deadlock_recovery(nasids, ibegin, i, mynasid, ptc0, data0, ptc1, data1);
   8.263 +					if (reset_max_active_on_deadlock())
   8.264 +						max_active = 1;
   8.265 +				}
   8.266 +				active = 0;
   8.267 +				ibegin = i + 1;
   8.268 +			}
   8.269 +		}
   8.270 +		start += (1UL << nbits);
   8.271 +	} while (start < end);
   8.272 +
   8.273 +	itc2 = ia64_get_itc() - itc2;
   8.274 +	__get_cpu_var(ptcstats).shub_itc_clocks += itc2;
   8.275 +	if (itc2 > __get_cpu_var(ptcstats).shub_itc_clocks_max)
   8.276 +		__get_cpu_var(ptcstats).shub_itc_clocks_max = itc2;
   8.277 +
   8.278 +	if (old_rr) {
   8.279 +		ia64_set_rr(start, old_rr);
   8.280 +		ia64_srlz_d();
   8.281 +	}
   8.282 +
   8.283 +	spin_unlock_irqrestore(PTC_LOCK(shub1), flags);
   8.284 +
   8.285 +	preempt_enable();
   8.286 +}
   8.287 +
   8.288 +/*
   8.289 + * sn2_ptc_deadlock_recovery
   8.290 + *
   8.291 + * Recover from PTC deadlocks conditions. Recovery requires stepping thru each 
   8.292 + * TLB flush transaction.  The recovery sequence is somewhat tricky & is
   8.293 + * coded in assembly language.
   8.294 + */
   8.295 +
   8.296 +void
   8.297 +sn2_ptc_deadlock_recovery(short *nasids, short ib, short ie, int mynasid,
   8.298 +			  volatile unsigned long *ptc0, unsigned long data0,
   8.299 +			  volatile unsigned long *ptc1, unsigned long data1)
   8.300 +{
   8.301 +	short nasid, i;
   8.302 +	unsigned long *piows, zeroval, n;
   8.303 +
   8.304 +	__get_cpu_var(ptcstats).deadlocks++;
   8.305 +
   8.306 +	piows = (unsigned long *) pda->pio_write_status_addr;
   8.307 +	zeroval = pda->pio_write_status_val;
   8.308 +
   8.309 +
   8.310 +	for (i=ib; i <= ie; i++) {
   8.311 +		nasid = nasids[i];
   8.312 +		if (local_node_uses_ptc_ga(is_shub1()) && nasid == mynasid)
   8.313 +			continue;
   8.314 +		ptc0 = CHANGE_NASID(nasid, ptc0);
   8.315 +		if (ptc1)
   8.316 +			ptc1 = CHANGE_NASID(nasid, ptc1);
   8.317 +
   8.318 +		n = sn2_ptc_deadlock_recovery_core(ptc0, data0, ptc1, data1, piows, zeroval);
   8.319 +		__get_cpu_var(ptcstats).deadlocks2 += n;
   8.320 +	}
   8.321 +
   8.322 +}
   8.323 +
   8.324 +/**
   8.325 + * sn_send_IPI_phys - send an IPI to a Nasid and slice
   8.326 + * @nasid: nasid to receive the interrupt (may be outside partition)
   8.327 + * @physid: physical cpuid to receive the interrupt.
   8.328 + * @vector: command to send
   8.329 + * @delivery_mode: delivery mechanism
   8.330 + *
   8.331 + * Sends an IPI (interprocessor interrupt) to the processor specified by
   8.332 + * @physid
   8.333 + *
   8.334 + * @delivery_mode can be one of the following
   8.335 + *
   8.336 + * %IA64_IPI_DM_INT - pend an interrupt
   8.337 + * %IA64_IPI_DM_PMI - pend a PMI
   8.338 + * %IA64_IPI_DM_NMI - pend an NMI
   8.339 + * %IA64_IPI_DM_INIT - pend an INIT interrupt
   8.340 + */
   8.341 +void sn_send_IPI_phys(int nasid, long physid, int vector, int delivery_mode)
   8.342 +{
   8.343 +	long val;
   8.344 +	unsigned long flags = 0;
   8.345 +	volatile long *p;
   8.346 +
   8.347 +	p = (long *)GLOBAL_MMR_PHYS_ADDR(nasid, SH_IPI_INT);
   8.348 +	val = (1UL << SH_IPI_INT_SEND_SHFT) |
   8.349 +	    (physid << SH_IPI_INT_PID_SHFT) |
   8.350 +	    ((long)delivery_mode << SH_IPI_INT_TYPE_SHFT) |
   8.351 +	    ((long)vector << SH_IPI_INT_IDX_SHFT) |
   8.352 +	    (0x000feeUL << SH_IPI_INT_BASE_SHFT);
   8.353 +
   8.354 +	mb();
   8.355 +	if (enable_shub_wars_1_1()) {
   8.356 +		spin_lock_irqsave(&sn2_global_ptc_lock, flags);
   8.357 +	}
   8.358 +	pio_phys_write_mmr(p, val);
   8.359 +	if (enable_shub_wars_1_1()) {
   8.360 +		wait_piowc();
   8.361 +		spin_unlock_irqrestore(&sn2_global_ptc_lock, flags);
   8.362 +	}
   8.363 +
   8.364 +}
   8.365 +
   8.366 +EXPORT_SYMBOL(sn_send_IPI_phys);
   8.367 +
   8.368 +/**
   8.369 + * sn2_send_IPI - send an IPI to a processor
   8.370 + * @cpuid: target of the IPI
   8.371 + * @vector: command to send
   8.372 + * @delivery_mode: delivery mechanism
   8.373 + * @redirect: redirect the IPI?
   8.374 + *
   8.375 + * Sends an IPI (InterProcessor Interrupt) to the processor specified by
   8.376 + * @cpuid.  @vector specifies the command to send, while @delivery_mode can 
   8.377 + * be one of the following
   8.378 + *
   8.379 + * %IA64_IPI_DM_INT - pend an interrupt
   8.380 + * %IA64_IPI_DM_PMI - pend a PMI
   8.381 + * %IA64_IPI_DM_NMI - pend an NMI
   8.382 + * %IA64_IPI_DM_INIT - pend an INIT interrupt
   8.383 + */
   8.384 +void sn2_send_IPI(int cpuid, int vector, int delivery_mode, int redirect)
   8.385 +{
   8.386 +	long physid;
   8.387 +	int nasid;
   8.388 +
   8.389 +	physid = cpu_physical_id(cpuid);
   8.390 +	nasid = cpuid_to_nasid(cpuid);
   8.391 +
   8.392 +	/* the following is used only when starting cpus at boot time */
   8.393 +	if (unlikely(nasid == -1))
   8.394 +		ia64_sn_get_sapic_info(physid, &nasid, NULL, NULL);
   8.395 +
   8.396 +	sn_send_IPI_phys(nasid, physid, vector, delivery_mode);
   8.397 +}
   8.398 +
   8.399 +#ifdef CONFIG_PROC_FS
   8.400 +
   8.401 +#define PTC_BASENAME	"sgi_sn/ptc_statistics"
   8.402 +
   8.403 +static void *sn2_ptc_seq_start(struct seq_file *file, loff_t * offset)
   8.404 +{
   8.405 +	if (*offset < NR_CPUS)
   8.406 +		return offset;
   8.407 +	return NULL;
   8.408 +}
   8.409 +
   8.410 +static void *sn2_ptc_seq_next(struct seq_file *file, void *data, loff_t * offset)
   8.411 +{
   8.412 +	(*offset)++;
   8.413 +	if (*offset < NR_CPUS)
   8.414 +		return offset;
   8.415 +	return NULL;
   8.416 +}
   8.417 +
   8.418 +static void sn2_ptc_seq_stop(struct seq_file *file, void *data)
   8.419 +{
   8.420 +}
   8.421 +
   8.422 +static int sn2_ptc_seq_show(struct seq_file *file, void *data)
   8.423 +{
   8.424 +	struct ptc_stats *stat;
   8.425 +	int cpu;
   8.426 +
   8.427 +	cpu = *(loff_t *) data;
   8.428 +
   8.429 +	if (!cpu) {
   8.430 +		seq_printf(file,
   8.431 +			   "# cpu ptc_l newrid ptc_flushes nodes_flushed deadlocks lock_nsec shub_nsec shub_nsec_max not_my_mm deadlock2\n");
   8.432 +		seq_printf(file, "# ptctest %d\n", sn2_ptctest);
   8.433 +	}
   8.434 +
   8.435 +	if (cpu < NR_CPUS && cpu_online(cpu)) {
   8.436 +		stat = &per_cpu(ptcstats, cpu);
   8.437 +		seq_printf(file, "cpu %d %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld\n", cpu, stat->ptc_l,
   8.438 +				stat->change_rid, stat->shub_ptc_flushes, stat->nodes_flushed,
   8.439 +				stat->deadlocks,
   8.440 +				1000 * stat->lock_itc_clocks / per_cpu(cpu_info, cpu).cyc_per_usec,
   8.441 +				1000 * stat->shub_itc_clocks / per_cpu(cpu_info, cpu).cyc_per_usec,
   8.442 +				1000 * stat->shub_itc_clocks_max / per_cpu(cpu_info, cpu).cyc_per_usec,
   8.443 +				stat->shub_ptc_flushes_not_my_mm,
   8.444 +				stat->deadlocks2);
   8.445 +	}
   8.446 +	return 0;
   8.447 +}
   8.448 +
   8.449 +static struct seq_operations sn2_ptc_seq_ops = {
   8.450 +	.start = sn2_ptc_seq_start,
   8.451 +	.next = sn2_ptc_seq_next,
   8.452 +	.stop = sn2_ptc_seq_stop,
   8.453 +	.show = sn2_ptc_seq_show
   8.454 +};
   8.455 +
   8.456 +static int sn2_ptc_proc_open(struct inode *inode, struct file *file)
   8.457 +{
   8.458 +	return seq_open(file, &sn2_ptc_seq_ops);
   8.459 +}
   8.460 +
   8.461 +static struct file_operations proc_sn2_ptc_operations = {
   8.462 +	.open = sn2_ptc_proc_open,
   8.463 +	.read = seq_read,
   8.464 +	.llseek = seq_lseek,
   8.465 +	.release = seq_release,
   8.466 +};
   8.467 +
   8.468 +static struct proc_dir_entry *proc_sn2_ptc;
   8.469 +
   8.470 +static int __init sn2_ptc_init(void)
   8.471 +{
   8.472 +	if (!ia64_platform_is("sn2"))
   8.473 +		return 0;
   8.474 +
   8.475 +	if (!(proc_sn2_ptc = create_proc_entry(PTC_BASENAME, 0444, NULL))) {
   8.476 +		printk(KERN_ERR "unable to create %s proc entry", PTC_BASENAME);
   8.477 +		return -EINVAL;
   8.478 +	}
   8.479 +	proc_sn2_ptc->proc_fops = &proc_sn2_ptc_operations;
   8.480 +	spin_lock_init(&sn2_global_ptc_lock);
   8.481 +	return 0;
   8.482 +}
   8.483 +
   8.484 +static void __exit sn2_ptc_exit(void)
   8.485 +{
   8.486 +	remove_proc_entry(PTC_BASENAME, NULL);
   8.487 +}
   8.488 +
   8.489 +module_init(sn2_ptc_init);
   8.490 +module_exit(sn2_ptc_exit);
   8.491 +#endif /* CONFIG_PROC_FS */
   8.492 +

     9.1 --- a/xen/arch/ia64/linux/Makefile	Tue Dec 12 15:25:02 2006 -0700
     9.2 +++ b/xen/arch/ia64/linux/Makefile	Wed Dec 13 11:08:40 2006 -0700
     9.3 @@ -23,6 +23,7 @@ obj-y += __udivdi3.o
     9.4  obj-y += __moddi3.o
     9.5  obj-y += __umoddi3.o
     9.6  obj-y += carta_random.o
     9.7 +obj-y += io.o
     9.8  
     9.9  ## variants of divide/modulo
    9.10  ## see files in xen/arch/ia64/linux/lib (linux/arch/ia64/lib)

    10.1 --- a/xen/arch/ia64/linux/README.origin	Tue Dec 12 15:25:02 2006 -0700
    10.2 +++ b/xen/arch/ia64/linux/README.origin	Wed Dec 13 11:08:40 2006 -0700
    10.3 @@ -27,3 +27,6 @@ strlen.S		-> linux/arch/ia64/lib/strlen.
    10.4  
    10.5  # The files below are from Linux-2.6.16.33
    10.6  carta_random.S		-> linux/arch/ia64/lib/carta_random.S
    10.7 +
    10.8 +# The files below are from Linux-2.6.19
    10.9 +io.c			-> linux/arch/ia64/lib/io.c

    11.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    11.2 +++ b/xen/arch/ia64/linux/dig/Makefile	Wed Dec 13 11:08:40 2006 -0700
    11.3 @@ -0,0 +1,1 @@
    11.4 +obj-y += machvec.o

    12.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    12.2 +++ b/xen/arch/ia64/linux/dig/README.origin	Wed Dec 13 11:08:40 2006 -0700
    12.3 @@ -0,0 +1,7 @@
    12.4 +Source files in this directory are identical copies of linux-2.6.19 files:
    12.5 +
    12.6 +NOTE: DO NOT commit changes to these files!   If a file
    12.7 +needs to be changed, move it to ../linux-xen and follow
    12.8 +the instructions in the README there.
    12.9 +
   12.10 +machvec.c		-> linux/arch/ia64/dig/machvec.c

    13.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    13.2 +++ b/xen/arch/ia64/linux/dig/machvec.c	Wed Dec 13 11:08:40 2006 -0700
    13.3 @@ -0,0 +1,3 @@
    13.4 +#define MACHVEC_PLATFORM_NAME		dig
    13.5 +#define MACHVEC_PLATFORM_HEADER		<asm/machvec_dig.h>
    13.6 +#include <asm/machvec_init.h>

    14.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    14.2 +++ b/xen/arch/ia64/linux/hp/Makefile	Wed Dec 13 11:08:40 2006 -0700
    14.3 @@ -0,0 +1,1 @@
    14.4 +subdir-y += zx1

    15.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    15.2 +++ b/xen/arch/ia64/linux/hp/zx1/Makefile	Wed Dec 13 11:08:40 2006 -0700
    15.3 @@ -0,0 +1,1 @@
    15.4 +obj-y += hpzx1_machvec.o

    16.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    16.2 +++ b/xen/arch/ia64/linux/hp/zx1/README.origin	Wed Dec 13 11:08:40 2006 -0700
    16.3 @@ -0,0 +1,7 @@
    16.4 +Source files in this directory are identical copies of linux-2.6.19 files:
    16.5 +
    16.6 +NOTE: DO NOT commit changes to these files!   If a file
    16.7 +needs to be changed, move it to ../linux-xen and follow
    16.8 +the instructions in the README there.
    16.9 +
   16.10 +hpzx1_machvec.c		-> linux/arch/ia64/hp/zx1/hpzx1_machvec.c

    17.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    17.2 +++ b/xen/arch/ia64/linux/hp/zx1/hpzx1_machvec.c	Wed Dec 13 11:08:40 2006 -0700
    17.3 @@ -0,0 +1,3 @@
    17.4 +#define MACHVEC_PLATFORM_NAME		hpzx1
    17.5 +#define MACHVEC_PLATFORM_HEADER		<asm/machvec_hpzx1.h>
    17.6 +#include <asm/machvec_init.h>

    18.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    18.2 +++ b/xen/arch/ia64/linux/io.c	Wed Dec 13 11:08:40 2006 -0700
    18.3 @@ -0,0 +1,164 @@
    18.4 +#include <linux/module.h>
    18.5 +#include <linux/types.h>
    18.6 +
    18.7 +#include <asm/io.h>
    18.8 +
    18.9 +/*
   18.10 + * Copy data from IO memory space to "real" memory space.
   18.11 + * This needs to be optimized.
   18.12 + */
   18.13 +void memcpy_fromio(void *to, const volatile void __iomem *from, long count)
   18.14 +{
   18.15 +	char *dst = to;
   18.16 +
   18.17 +	while (count) {
   18.18 +		count--;
   18.19 +		*dst++ = readb(from++);
   18.20 +	}
   18.21 +}
   18.22 +EXPORT_SYMBOL(memcpy_fromio);
   18.23 +
   18.24 +/*
   18.25 + * Copy data from "real" memory space to IO memory space.
   18.26 + * This needs to be optimized.
   18.27 + */
   18.28 +void memcpy_toio(volatile void __iomem *to, const void *from, long count)
   18.29 +{
   18.30 +	const char *src = from;
   18.31 +
   18.32 +	while (count) {
   18.33 +		count--;
   18.34 +		writeb(*src++, to++);
   18.35 +	}
   18.36 +}
   18.37 +EXPORT_SYMBOL(memcpy_toio);
   18.38 +
   18.39 +/*
   18.40 + * "memset" on IO memory space.
   18.41 + * This needs to be optimized.
   18.42 + */
   18.43 +void memset_io(volatile void __iomem *dst, int c, long count)
   18.44 +{
   18.45 +	unsigned char ch = (char)(c & 0xff);
   18.46 +
   18.47 +	while (count) {
   18.48 +		count--;
   18.49 +		writeb(ch, dst);
   18.50 +		dst++;
   18.51 +	}
   18.52 +}
   18.53 +EXPORT_SYMBOL(memset_io);
   18.54 +
   18.55 +#ifdef CONFIG_IA64_GENERIC
   18.56 +
   18.57 +#undef __ia64_inb
   18.58 +#undef __ia64_inw
   18.59 +#undef __ia64_inl
   18.60 +#undef __ia64_outb
   18.61 +#undef __ia64_outw
   18.62 +#undef __ia64_outl
   18.63 +#undef __ia64_readb
   18.64 +#undef __ia64_readw
   18.65 +#undef __ia64_readl
   18.66 +#undef __ia64_readq
   18.67 +#undef __ia64_readb_relaxed
   18.68 +#undef __ia64_readw_relaxed
   18.69 +#undef __ia64_readl_relaxed
   18.70 +#undef __ia64_readq_relaxed
   18.71 +#undef __ia64_writeb
   18.72 +#undef __ia64_writew
   18.73 +#undef __ia64_writel
   18.74 +#undef __ia64_writeq
   18.75 +#undef __ia64_mmiowb
   18.76 +
   18.77 +unsigned int
   18.78 +__ia64_inb (unsigned long port)
   18.79 +{
   18.80 +	return ___ia64_inb(port);
   18.81 +}
   18.82 +
   18.83 +unsigned int
   18.84 +__ia64_inw (unsigned long port)
   18.85 +{
   18.86 +	return ___ia64_inw(port);
   18.87 +}
   18.88 +
   18.89 +unsigned int
   18.90 +__ia64_inl (unsigned long port)
   18.91 +{
   18.92 +	return ___ia64_inl(port);
   18.93 +}
   18.94 +
   18.95 +void
   18.96 +__ia64_outb (unsigned char val, unsigned long port)
   18.97 +{
   18.98 +	___ia64_outb(val, port);
   18.99 +}
  18.100 +
  18.101 +void
  18.102 +__ia64_outw (unsigned short val, unsigned long port)
  18.103 +{
  18.104 +	___ia64_outw(val, port);
  18.105 +}
  18.106 +
  18.107 +void
  18.108 +__ia64_outl (unsigned int val, unsigned long port)
  18.109 +{
  18.110 +	___ia64_outl(val, port);
  18.111 +}
  18.112 +
  18.113 +unsigned char
  18.114 +__ia64_readb (void __iomem *addr)
  18.115 +{
  18.116 +	return ___ia64_readb (addr);
  18.117 +}
  18.118 +
  18.119 +unsigned short
  18.120 +__ia64_readw (void __iomem *addr)
  18.121 +{
  18.122 +	return ___ia64_readw (addr);
  18.123 +}
  18.124 +
  18.125 +unsigned int
  18.126 +__ia64_readl (void __iomem *addr)
  18.127 +{
  18.128 +	return ___ia64_readl (addr);
  18.129 +}
  18.130 +
  18.131 +unsigned long
  18.132 +__ia64_readq (void __iomem *addr)
  18.133 +{
  18.134 +	return ___ia64_readq (addr);
  18.135 +}
  18.136 +
  18.137 +unsigned char
  18.138 +__ia64_readb_relaxed (void __iomem *addr)
  18.139 +{
  18.140 +	return ___ia64_readb (addr);
  18.141 +}
  18.142 +
  18.143 +unsigned short
  18.144 +__ia64_readw_relaxed (void __iomem *addr)
  18.145 +{
  18.146 +	return ___ia64_readw (addr);
  18.147 +}
  18.148 +
  18.149 +unsigned int
  18.150 +__ia64_readl_relaxed (void __iomem *addr)
  18.151 +{
  18.152 +	return ___ia64_readl (addr);
  18.153 +}
  18.154 +
  18.155 +unsigned long
  18.156 +__ia64_readq_relaxed (void __iomem *addr)
  18.157 +{
  18.158 +	return ___ia64_readq (addr);
  18.159 +}
  18.160 +
  18.161 +void
  18.162 +__ia64_mmiowb(void)
  18.163 +{
  18.164 +	___ia64_mmiowb();
  18.165 +}
  18.166 +
  18.167 +#endif /* CONFIG_IA64_GENERIC */

    19.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    19.2 +++ b/xen/arch/ia64/linux/sn/Makefile	Wed Dec 13 11:08:40 2006 -0700
    19.3 @@ -0,0 +1,2 @@
    19.4 +subdir-y += kernel
    19.5 +subdir-y += pci

    20.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    20.2 +++ b/xen/arch/ia64/linux/sn/kernel/Makefile	Wed Dec 13 11:08:40 2006 -0700
    20.3 @@ -0,0 +1,3 @@
    20.4 +obj-y += machvec.o
    20.5 +obj-y += pio_phys.o
    20.6 +obj-y += ptc_deadlock.o

    21.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    21.2 +++ b/xen/arch/ia64/linux/sn/kernel/README.origin	Wed Dec 13 11:08:40 2006 -0700
    21.3 @@ -0,0 +1,9 @@
    21.4 +Source files in this directory are identical copies of linux-2.6.19 files:
    21.5 +
    21.6 +NOTE: DO NOT commit changes to these files!   If a file
    21.7 +needs to be changed, move it to ../linux-xen and follow
    21.8 +the instructions in the README there.
    21.9 +
   21.10 +machvec.c		-> linux/arch/ia64/sn/kernel/machvec.c
   21.11 +pio_phys.S		-> linux/arch/ia64/sn/kernel/pio_phys.S
   21.12 +ptc_deadlock.S		-> linux/arch/ia64/sn/kernel/sn2/ptc_deadlock.S

    22.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    22.2 +++ b/xen/arch/ia64/linux/sn/kernel/machvec.c	Wed Dec 13 11:08:40 2006 -0700
    22.3 @@ -0,0 +1,11 @@
    22.4 +/*
    22.5 + * This file is subject to the terms and conditions of the GNU General Public
    22.6 + * License.  See the file "COPYING" in the main directory of this archive
    22.7 + * for more details.
    22.8 + *
    22.9 + * Copyright (c) 2002-2003 Silicon Graphics, Inc.  All Rights Reserved.
   22.10 + */
   22.11 +
   22.12 +#define MACHVEC_PLATFORM_NAME	sn2
   22.13 +#define MACHVEC_PLATFORM_HEADER	<asm/machvec_sn2.h>
   22.14 +#include <asm/machvec_init.h>

    23.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    23.2 +++ b/xen/arch/ia64/linux/sn/kernel/pio_phys.S	Wed Dec 13 11:08:40 2006 -0700
    23.3 @@ -0,0 +1,71 @@
    23.4 +/*
    23.5 + * This file is subject to the terms and conditions of the GNU General Public
    23.6 + * License.  See the file "COPYING" in the main directory of this archive
    23.7 + * for more details.
    23.8 + *
    23.9 + * Copyright (C) 2000-2005 Silicon Graphics, Inc. All rights reserved.
   23.10 + *
   23.11 + * This file contains macros used to access MMR registers via
   23.12 + * uncached physical addresses.
   23.13 + *      pio_phys_read_mmr  - read an MMR
   23.14 + *      pio_phys_write_mmr - write an MMR
   23.15 + *      pio_atomic_phys_write_mmrs - atomically write 1 or 2 MMRs with psr.ic=0
   23.16 + *              Second MMR will be skipped if address is NULL
   23.17 + *
   23.18 + * Addresses passed to these routines should be uncached physical addresses
   23.19 + * 	ie., 0x80000....
   23.20 + */
   23.21 +
   23.22 +
   23.23 +
   23.24 +#include <asm/asmmacro.h>
   23.25 +#include <asm/page.h>
   23.26 +
   23.27 +GLOBAL_ENTRY(pio_phys_read_mmr)
   23.28 +	.prologue
   23.29 +	.regstk 1,0,0,0
   23.30 +	.body
   23.31 +	mov r2=psr
   23.32 +	rsm psr.i | psr.dt
   23.33 +	;;
   23.34 +	srlz.d
   23.35 +	ld8.acq r8=[r32]
   23.36 +	;;
   23.37 +	mov psr.l=r2;;
   23.38 +	srlz.d
   23.39 +	br.ret.sptk.many rp
   23.40 +END(pio_phys_read_mmr)
   23.41 +
   23.42 +GLOBAL_ENTRY(pio_phys_write_mmr)
   23.43 +	.prologue
   23.44 +	.regstk 2,0,0,0
   23.45 +	.body
   23.46 +	mov r2=psr
   23.47 +	rsm psr.i | psr.dt
   23.48 +	;;
   23.49 +	srlz.d
   23.50 +	st8.rel [r32]=r33
   23.51 +	;;
   23.52 +	mov psr.l=r2;;
   23.53 +	srlz.d
   23.54 +	br.ret.sptk.many rp
   23.55 +END(pio_phys_write_mmr)
   23.56 +
   23.57 +GLOBAL_ENTRY(pio_atomic_phys_write_mmrs)
   23.58 +	.prologue
   23.59 +	.regstk 4,0,0,0
   23.60 +	.body
   23.61 +	mov r2=psr
   23.62 +	cmp.ne p9,p0=r34,r0;
   23.63 +	rsm psr.i | psr.dt | psr.ic
   23.64 +	;;
   23.65 +	srlz.d
   23.66 +	st8.rel [r32]=r33
   23.67 +(p9)	st8.rel [r34]=r35
   23.68 +	;;
   23.69 +	mov psr.l=r2;;
   23.70 +	srlz.d
   23.71 +	br.ret.sptk.many rp
   23.72 +END(pio_atomic_phys_write_mmrs)
   23.73 +
   23.74 +

    24.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    24.2 +++ b/xen/arch/ia64/linux/sn/kernel/ptc_deadlock.S	Wed Dec 13 11:08:40 2006 -0700
    24.3 @@ -0,0 +1,92 @@
    24.4 +/* 
    24.5 + * This file is subject to the terms and conditions of the GNU General Public
    24.6 + * License.  See the file "COPYING" in the main directory of this archive
    24.7 + * for more details.
    24.8 + *
    24.9 + * Copyright (C) 2000-2005 Silicon Graphics, Inc. All rights reserved.
   24.10 + */
   24.11 +
   24.12 +#include <asm/types.h>
   24.13 +#include <asm/sn/shub_mmr.h>
   24.14 +
   24.15 +#define DEADLOCKBIT	SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_SHFT
   24.16 +#define WRITECOUNTMASK	SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK
   24.17 +#define ALIAS_OFFSET	8
   24.18 +
   24.19 +
   24.20 +	.global	sn2_ptc_deadlock_recovery_core
   24.21 +	.proc  	sn2_ptc_deadlock_recovery_core
   24.22 +
   24.23 +sn2_ptc_deadlock_recovery_core:
   24.24 +	.regstk 6,0,0,0
   24.25 +
   24.26 +	ptc0  	 = in0
   24.27 +	data0 	 = in1
   24.28 +	ptc1  	 = in2
   24.29 +	data1 	 = in3
   24.30 +	piowc 	 = in4
   24.31 +	zeroval  = in5
   24.32 +	piowcphy = r30
   24.33 +	psrsave  = r2
   24.34 +	scr1	 = r16
   24.35 +	scr2	 = r17
   24.36 +	mask	 = r18
   24.37 +
   24.38 +
   24.39 +	extr.u	piowcphy=piowc,0,61;;	// Convert piowc to uncached physical address
   24.40 +	dep	piowcphy=-1,piowcphy,63,1
   24.41 +	movl	mask=WRITECOUNTMASK
   24.42 +	mov	r8=r0
   24.43 +
   24.44 +1:
   24.45 +	cmp.ne  p8,p9=r0,ptc1		// Test for shub type (ptc1 non-null on shub1)
   24.46 +					// p8 = 1 if shub1, p9 = 1 if shub2
   24.47 +
   24.48 +	add	scr2=ALIAS_OFFSET,piowc	// Address of WRITE_STATUS alias register 
   24.49 +	mov	scr1=7;;		// Clear DEADLOCK, WRITE_ERROR, MULTI_WRITE_ERROR
   24.50 +(p8)	st8.rel	[scr2]=scr1;;
   24.51 +(p9)	ld8.acq	scr1=[scr2];;
   24.52 +
   24.53 +5:	ld8.acq	scr1=[piowc];;		// Wait for PIOs to complete.
   24.54 +	hint	@pause
   24.55 +	and	scr2=scr1,mask;;	// mask of writecount bits
   24.56 +	cmp.ne	p6,p0=zeroval,scr2
   24.57 +(p6)	br.cond.sptk 5b
   24.58 +	
   24.59 +
   24.60 +
   24.61 +	////////////// BEGIN PHYSICAL MODE ////////////////////
   24.62 +	mov psrsave=psr			// Disable IC (no PMIs)
   24.63 +	rsm psr.i | psr.dt | psr.ic;;
   24.64 +	srlz.i;;
   24.65 +
   24.66 +	st8.rel [ptc0]=data0		// Write PTC0 & wait for completion.
   24.67 +
   24.68 +5:	ld8.acq	scr1=[piowcphy];;	// Wait for PIOs to complete.
   24.69 +	hint	@pause
   24.70 +	and	scr2=scr1,mask;;	// mask of writecount bits
   24.71 +	cmp.ne	p6,p0=zeroval,scr2
   24.72 +(p6)	br.cond.sptk 5b;;
   24.73 +
   24.74 +	tbit.nz	p8,p7=scr1,DEADLOCKBIT;;// Test for DEADLOCK
   24.75 +(p7)	cmp.ne p7,p0=r0,ptc1;;		// Test for non-null ptc1
   24.76 +	
   24.77 +(p7)	st8.rel [ptc1]=data1;;		// Now write PTC1.
   24.78 +
   24.79 +5:	ld8.acq	scr1=[piowcphy];;	// Wait for PIOs to complete.
   24.80 +	hint	@pause
   24.81 +	and	scr2=scr1,mask;;	// mask of writecount bits
   24.82 +	cmp.ne	p6,p0=zeroval,scr2
   24.83 +(p6)	br.cond.sptk 5b
   24.84 +	
   24.85 +	tbit.nz	p8,p0=scr1,DEADLOCKBIT;;// Test for DEADLOCK
   24.86 +
   24.87 +	mov psr.l=psrsave;;		// Reenable IC
   24.88 +	srlz.i;;
   24.89 +	////////////// END   PHYSICAL MODE ////////////////////
   24.90 +
   24.91 +(p8)	add	r8=1,r8
   24.92 +(p8)	br.cond.spnt 1b;;		// Repeat if DEADLOCK occurred.
   24.93 +
   24.94 +	br.ret.sptk	rp
   24.95 +	.endp sn2_ptc_deadlock_recovery_core

    25.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    25.2 +++ b/xen/arch/ia64/linux/sn/pci/Makefile	Wed Dec 13 11:08:40 2006 -0700
    25.3 @@ -0,0 +1,1 @@
    25.4 +subdir-y += pcibr

    26.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    26.2 +++ b/xen/arch/ia64/linux/sn/pci/pcibr/Makefile	Wed Dec 13 11:08:40 2006 -0700
    26.3 @@ -0,0 +1,1 @@
    26.4 +obj-y += pcibr_reg.o

    27.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    27.2 +++ b/xen/arch/ia64/linux/sn/pci/pcibr/README.origin	Wed Dec 13 11:08:40 2006 -0700
    27.3 @@ -0,0 +1,7 @@
    27.4 +Source files in this directory are identical copies of linux-2.6.19 files:
    27.5 +
    27.6 +NOTE: DO NOT commit changes to these files!   If a file
    27.7 +needs to be changed, move it to ../linux-xen and follow
    27.8 +the instructions in the README there.
    27.9 +
   27.10 +pcibr_reg.c		-> linux/arch/ia64/sn/pci/pcibr/pcibr_reg.c

    28.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    28.2 +++ b/xen/arch/ia64/linux/sn/pci/pcibr/pcibr_reg.c	Wed Dec 13 11:08:40 2006 -0700
    28.3 @@ -0,0 +1,285 @@
    28.4 +/*
    28.5 + * This file is subject to the terms and conditions of the GNU General Public
    28.6 + * License.  See the file "COPYING" in the main directory of this archive
    28.7 + * for more details.
    28.8 + *
    28.9 + * Copyright (C) 2004 Silicon Graphics, Inc. All rights reserved.
   28.10 + */
   28.11 +
   28.12 +#include <linux/interrupt.h>
   28.13 +#include <linux/types.h>
   28.14 +#include <asm/sn/io.h>
   28.15 +#include <asm/sn/pcibr_provider.h>
   28.16 +#include <asm/sn/pcibus_provider_defs.h>
   28.17 +#include <asm/sn/pcidev.h>
   28.18 +#include <asm/sn/pic.h>
   28.19 +#include <asm/sn/tiocp.h>
   28.20 +
   28.21 +union br_ptr {
   28.22 +	struct tiocp tio;
   28.23 +	struct pic pic;
   28.24 +};
   28.25 +
   28.26 +/*
   28.27 + * Control Register Access -- Read/Write                            0000_0020
   28.28 + */
   28.29 +void pcireg_control_bit_clr(struct pcibus_info *pcibus_info, u64 bits)
   28.30 +{
   28.31 +	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
   28.32 +
   28.33 +	if (pcibus_info) {
   28.34 +		switch (pcibus_info->pbi_bridge_type) {
   28.35 +		case PCIBR_BRIDGETYPE_TIOCP:
   28.36 +			__sn_clrq_relaxed(&ptr->tio.cp_control, bits);
   28.37 +			break;
   28.38 +		case PCIBR_BRIDGETYPE_PIC:
   28.39 +			__sn_clrq_relaxed(&ptr->pic.p_wid_control, bits);
   28.40 +			break;
   28.41 +		default:
   28.42 +			panic
   28.43 +			    ("pcireg_control_bit_clr: unknown bridgetype bridge 0x%p",
   28.44 +			     ptr);
   28.45 +		}
   28.46 +	}
   28.47 +}
   28.48 +
   28.49 +void pcireg_control_bit_set(struct pcibus_info *pcibus_info, u64 bits)
   28.50 +{
   28.51 +	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
   28.52 +
   28.53 +	if (pcibus_info) {
   28.54 +		switch (pcibus_info->pbi_bridge_type) {
   28.55 +		case PCIBR_BRIDGETYPE_TIOCP:
   28.56 +			__sn_setq_relaxed(&ptr->tio.cp_control, bits);
   28.57 +			break;
   28.58 +		case PCIBR_BRIDGETYPE_PIC:
   28.59 +			__sn_setq_relaxed(&ptr->pic.p_wid_control, bits);
   28.60 +			break;
   28.61 +		default:
   28.62 +			panic
   28.63 +			    ("pcireg_control_bit_set: unknown bridgetype bridge 0x%p",
   28.64 +			     ptr);
   28.65 +		}
   28.66 +	}
   28.67 +}
   28.68 +
   28.69 +/*
   28.70 + * PCI/PCIX Target Flush Register Access -- Read Only		    0000_0050
   28.71 + */
   28.72 +u64 pcireg_tflush_get(struct pcibus_info *pcibus_info)
   28.73 +{
   28.74 +	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
   28.75 +	u64 ret = 0;
   28.76 +
   28.77 +	if (pcibus_info) {
   28.78 +		switch (pcibus_info->pbi_bridge_type) {
   28.79 +		case PCIBR_BRIDGETYPE_TIOCP:
   28.80 +			ret = __sn_readq_relaxed(&ptr->tio.cp_tflush);
   28.81 +			break;
   28.82 +		case PCIBR_BRIDGETYPE_PIC:
   28.83 +			ret = __sn_readq_relaxed(&ptr->pic.p_wid_tflush);
   28.84 +			break;
   28.85 +		default:
   28.86 +			panic
   28.87 +			    ("pcireg_tflush_get: unknown bridgetype bridge 0x%p",
   28.88 +			     ptr);
   28.89 +		}
   28.90 +	}
   28.91 +
   28.92 +	/* Read of the Target Flush should always return zero */
   28.93 +	if (ret != 0)
   28.94 +		panic("pcireg_tflush_get:Target Flush failed\n");
   28.95 +
   28.96 +	return ret;
   28.97 +}
   28.98 +
   28.99 +/*
  28.100 + * Interrupt Status Register Access -- Read Only		    0000_0100
  28.101 + */
  28.102 +u64 pcireg_intr_status_get(struct pcibus_info * pcibus_info)
  28.103 +{
  28.104 +	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
  28.105 +	u64 ret = 0;
  28.106 +
  28.107 +	if (pcibus_info) {
  28.108 +		switch (pcibus_info->pbi_bridge_type) {
  28.109 +		case PCIBR_BRIDGETYPE_TIOCP:
  28.110 +			ret = __sn_readq_relaxed(&ptr->tio.cp_int_status);
  28.111 +			break;
  28.112 +		case PCIBR_BRIDGETYPE_PIC:
  28.113 +			ret = __sn_readq_relaxed(&ptr->pic.p_int_status);
  28.114 +			break;
  28.115 +		default:
  28.116 +			panic
  28.117 +			    ("pcireg_intr_status_get: unknown bridgetype bridge 0x%p",
  28.118 +			     ptr);
  28.119 +		}
  28.120 +	}
  28.121 +	return ret;
  28.122 +}
  28.123 +
  28.124 +/*
  28.125 + * Interrupt Enable Register Access -- Read/Write                   0000_0108
  28.126 + */
  28.127 +void pcireg_intr_enable_bit_clr(struct pcibus_info *pcibus_info, u64 bits)
  28.128 +{
  28.129 +	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
  28.130 +
  28.131 +	if (pcibus_info) {
  28.132 +		switch (pcibus_info->pbi_bridge_type) {
  28.133 +		case PCIBR_BRIDGETYPE_TIOCP:
  28.134 +			__sn_clrq_relaxed(&ptr->tio.cp_int_enable, bits);
  28.135 +			break;
  28.136 +		case PCIBR_BRIDGETYPE_PIC:
  28.137 +			__sn_clrq_relaxed(&ptr->pic.p_int_enable, bits);
  28.138 +			break;
  28.139 +		default:
  28.140 +			panic
  28.141 +			    ("pcireg_intr_enable_bit_clr: unknown bridgetype bridge 0x%p",
  28.142 +			     ptr);
  28.143 +		}
  28.144 +	}
  28.145 +}
  28.146 +
  28.147 +void pcireg_intr_enable_bit_set(struct pcibus_info *pcibus_info, u64 bits)
  28.148 +{
  28.149 +	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
  28.150 +
  28.151 +	if (pcibus_info) {
  28.152 +		switch (pcibus_info->pbi_bridge_type) {
  28.153 +		case PCIBR_BRIDGETYPE_TIOCP:
  28.154 +			__sn_setq_relaxed(&ptr->tio.cp_int_enable, bits);
  28.155 +			break;
  28.156 +		case PCIBR_BRIDGETYPE_PIC:
  28.157 +			__sn_setq_relaxed(&ptr->pic.p_int_enable, bits);
  28.158 +			break;
  28.159 +		default:
  28.160 +			panic
  28.161 +			    ("pcireg_intr_enable_bit_set: unknown bridgetype bridge 0x%p",
  28.162 +			     ptr);
  28.163 +		}
  28.164 +	}
  28.165 +}
  28.166 +
  28.167 +/*
  28.168 + * Intr Host Address Register (int_addr) -- Read/Write  0000_0130 - 0000_0168
  28.169 + */
  28.170 +void pcireg_intr_addr_addr_set(struct pcibus_info *pcibus_info, int int_n,
  28.171 +			       u64 addr)
  28.172 +{
  28.173 +	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
  28.174 +
  28.175 +	if (pcibus_info) {
  28.176 +		switch (pcibus_info->pbi_bridge_type) {
  28.177 +		case PCIBR_BRIDGETYPE_TIOCP:
  28.178 +			__sn_clrq_relaxed(&ptr->tio.cp_int_addr[int_n],
  28.179 +			    TIOCP_HOST_INTR_ADDR);
  28.180 +			__sn_setq_relaxed(&ptr->tio.cp_int_addr[int_n],
  28.181 +			    (addr & TIOCP_HOST_INTR_ADDR));
  28.182 +			break;
  28.183 +		case PCIBR_BRIDGETYPE_PIC:
  28.184 +			__sn_clrq_relaxed(&ptr->pic.p_int_addr[int_n],
  28.185 +			    PIC_HOST_INTR_ADDR);
  28.186 +			__sn_setq_relaxed(&ptr->pic.p_int_addr[int_n],
  28.187 +			    (addr & PIC_HOST_INTR_ADDR));
  28.188 +			break;
  28.189 +		default:
  28.190 +			panic
  28.191 +			    ("pcireg_intr_addr_addr_get: unknown bridgetype bridge 0x%p",
  28.192 +			     ptr);
  28.193 +		}
  28.194 +	}
  28.195 +}
  28.196 +
  28.197 +/*
  28.198 + * Force Interrupt Register Access -- Write Only	0000_01C0 - 0000_01F8
  28.199 + */
  28.200 +void pcireg_force_intr_set(struct pcibus_info *pcibus_info, int int_n)
  28.201 +{
  28.202 +	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
  28.203 +
  28.204 +	if (pcibus_info) {
  28.205 +		switch (pcibus_info->pbi_bridge_type) {
  28.206 +		case PCIBR_BRIDGETYPE_TIOCP:
  28.207 +			writeq(1, &ptr->tio.cp_force_pin[int_n]);
  28.208 +			break;
  28.209 +		case PCIBR_BRIDGETYPE_PIC:
  28.210 +			writeq(1, &ptr->pic.p_force_pin[int_n]);
  28.211 +			break;
  28.212 +		default:
  28.213 +			panic
  28.214 +			    ("pcireg_force_intr_set: unknown bridgetype bridge 0x%p",
  28.215 +			     ptr);
  28.216 +		}
  28.217 +	}
  28.218 +}
  28.219 +
  28.220 +/*
  28.221 + * Device(x) Write Buffer Flush Reg Access -- Read Only 0000_0240 - 0000_0258
  28.222 + */
  28.223 +u64 pcireg_wrb_flush_get(struct pcibus_info *pcibus_info, int device)
  28.224 +{
  28.225 +	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
  28.226 +	u64 ret = 0;
  28.227 +
  28.228 +	if (pcibus_info) {
  28.229 +		switch (pcibus_info->pbi_bridge_type) {
  28.230 +		case PCIBR_BRIDGETYPE_TIOCP:
  28.231 +			ret =
  28.232 +			    __sn_readq_relaxed(&ptr->tio.cp_wr_req_buf[device]);
  28.233 +			break;
  28.234 +		case PCIBR_BRIDGETYPE_PIC:
  28.235 +			ret =
  28.236 +			    __sn_readq_relaxed(&ptr->pic.p_wr_req_buf[device]);
  28.237 +			break;
  28.238 +		default:
  28.239 +		      panic("pcireg_wrb_flush_get: unknown bridgetype bridge 0x%p", ptr);
  28.240 +		}
  28.241 +
  28.242 +	}
  28.243 +	/* Read of the Write Buffer Flush should always return zero */
  28.244 +	return ret;
  28.245 +}
  28.246 +
  28.247 +void pcireg_int_ate_set(struct pcibus_info *pcibus_info, int ate_index,
  28.248 +			u64 val)
  28.249 +{
  28.250 +	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
  28.251 +
  28.252 +	if (pcibus_info) {
  28.253 +		switch (pcibus_info->pbi_bridge_type) {
  28.254 +		case PCIBR_BRIDGETYPE_TIOCP:
  28.255 +			writeq(val, &ptr->tio.cp_int_ate_ram[ate_index]);
  28.256 +			break;
  28.257 +		case PCIBR_BRIDGETYPE_PIC:
  28.258 +			writeq(val, &ptr->pic.p_int_ate_ram[ate_index]);
  28.259 +			break;
  28.260 +		default:
  28.261 +			panic
  28.262 +			    ("pcireg_int_ate_set: unknown bridgetype bridge 0x%p",
  28.263 +			     ptr);
  28.264 +		}
  28.265 +	}
  28.266 +}
  28.267 +
  28.268 +u64 __iomem *pcireg_int_ate_addr(struct pcibus_info *pcibus_info, int ate_index)
  28.269 +{
  28.270 +	union br_ptr __iomem *ptr = (union br_ptr __iomem *)pcibus_info->pbi_buscommon.bs_base;
  28.271 +	u64 __iomem *ret = NULL;
  28.272 +
  28.273 +	if (pcibus_info) {
  28.274 +		switch (pcibus_info->pbi_bridge_type) {
  28.275 +		case PCIBR_BRIDGETYPE_TIOCP:
  28.276 +			ret = &ptr->tio.cp_int_ate_ram[ate_index];
  28.277 +			break;
  28.278 +		case PCIBR_BRIDGETYPE_PIC:
  28.279 +			ret = &ptr->pic.p_int_ate_ram[ate_index];
  28.280 +			break;
  28.281 +		default:
  28.282 +			panic
  28.283 +			    ("pcireg_int_ate_addr: unknown bridgetype bridge 0x%p",
  28.284 +			     ptr);
  28.285 +		}
  28.286 +	}
  28.287 +	return ret;
  28.288 +}

    29.1 --- a/xen/include/asm-ia64/linux-null/linux/ioport.h	Tue Dec 12 15:25:02 2006 -0700
    29.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    29.3 @@ -1,1 +0,0 @@
    29.4 -/* This file is intentionally left empty. */

    30.1 --- a/xen/include/asm-ia64/linux-xen/asm/README.origin	Tue Dec 12 15:25:02 2006 -0700
    30.2 +++ b/xen/include/asm-ia64/linux-xen/asm/README.origin	Wed Dec 13 11:08:40 2006 -0700
    30.3 @@ -34,3 +34,9 @@ iosapic.h		-> linux/include/asm-ia64/ios
    30.4  # The files below are from Linux-2.6.16.33
    30.5  perfmon.h		-> linux/include/asm-ia64/perfmon.h
    30.6  perfmon_default_smpl.h	-> linux/include/asm-ia64/perfmon_default_smpl.h
    30.7 +
    30.8 +# The files below are from Linux-2.6.19
    30.9 +machvec_dig.h		-> linux/include/asm-ia64/machvec_dig.h
   30.10 +machvec_sn2.h		-> linux/include/asm-ia64/machvec_sn2.h
   30.11 +machvec_hpzx1.h		-> linux/include/asm-ia64/machvec_hpzx1.h
   30.12 +machvec_pci.h		-> linux/include/asm-ia64/pci.h

    31.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    31.2 +++ b/xen/include/asm-ia64/linux-xen/asm/machvec_dig.h	Wed Dec 13 11:08:40 2006 -0700
    31.3 @@ -0,0 +1,16 @@
    31.4 +#ifndef _ASM_IA64_MACHVEC_DIG_h
    31.5 +#define _ASM_IA64_MACHVEC_DIG_h
    31.6 +
    31.7 +extern ia64_mv_setup_t dig_setup;
    31.8 +
    31.9 +/*
   31.10 + * This stuff has dual use!
   31.11 + *
   31.12 + * For a generic kernel, the macros are used to initialize the
   31.13 + * platform's machvec structure.  When compiling a non-generic kernel,
   31.14 + * the macros are used directly.
   31.15 + */
   31.16 +#define platform_name		"dig"
   31.17 +#define platform_setup		dig_setup
   31.18 +
   31.19 +#endif /* _ASM_IA64_MACHVEC_DIG_h */

    32.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    32.2 +++ b/xen/include/asm-ia64/linux-xen/asm/machvec_hpzx1.h	Wed Dec 13 11:08:40 2006 -0700
    32.3 @@ -0,0 +1,37 @@
    32.4 +#ifndef _ASM_IA64_MACHVEC_HPZX1_h
    32.5 +#define _ASM_IA64_MACHVEC_HPZX1_h
    32.6 +
    32.7 +extern ia64_mv_setup_t			dig_setup;
    32.8 +extern ia64_mv_dma_alloc_coherent	sba_alloc_coherent;
    32.9 +extern ia64_mv_dma_free_coherent	sba_free_coherent;
   32.10 +extern ia64_mv_dma_map_single		sba_map_single;
   32.11 +extern ia64_mv_dma_unmap_single		sba_unmap_single;
   32.12 +extern ia64_mv_dma_map_sg		sba_map_sg;
   32.13 +extern ia64_mv_dma_unmap_sg		sba_unmap_sg;
   32.14 +extern ia64_mv_dma_supported		sba_dma_supported;
   32.15 +extern ia64_mv_dma_mapping_error	sba_dma_mapping_error;
   32.16 +
   32.17 +/*
   32.18 + * This stuff has dual use!
   32.19 + *
   32.20 + * For a generic kernel, the macros are used to initialize the
   32.21 + * platform's machvec structure.  When compiling a non-generic kernel,
   32.22 + * the macros are used directly.
   32.23 + */
   32.24 +#define platform_name				"hpzx1"
   32.25 +#define platform_setup				dig_setup
   32.26 +#define platform_dma_init			machvec_noop
   32.27 +#define platform_dma_alloc_coherent		sba_alloc_coherent
   32.28 +#define platform_dma_free_coherent		sba_free_coherent
   32.29 +#define platform_dma_map_single			sba_map_single
   32.30 +#define platform_dma_unmap_single		sba_unmap_single
   32.31 +#define platform_dma_map_sg			sba_map_sg
   32.32 +#define platform_dma_unmap_sg			sba_unmap_sg
   32.33 +#define platform_dma_sync_single_for_cpu	machvec_dma_sync_single
   32.34 +#define platform_dma_sync_sg_for_cpu		machvec_dma_sync_sg
   32.35 +#define platform_dma_sync_single_for_device	machvec_dma_sync_single
   32.36 +#define platform_dma_sync_sg_for_device		machvec_dma_sync_sg
   32.37 +#define platform_dma_supported			sba_dma_supported
   32.38 +#define platform_dma_mapping_error		sba_dma_mapping_error
   32.39 +
   32.40 +#endif /* _ASM_IA64_MACHVEC_HPZX1_h */

    33.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    33.2 +++ b/xen/include/asm-ia64/linux-xen/asm/machvec_sn2.h	Wed Dec 13 11:08:40 2006 -0700
    33.3 @@ -0,0 +1,133 @@
    33.4 +/*
    33.5 + * Copyright (c) 2002-2003,2006 Silicon Graphics, Inc.  All Rights Reserved.
    33.6 + * 
    33.7 + * This program is free software; you can redistribute it and/or modify it 
    33.8 + * under the terms of version 2 of the GNU General Public License 
    33.9 + * as published by the Free Software Foundation.
   33.10 + * 
   33.11 + * This program is distributed in the hope that it would be useful, but 
   33.12 + * WITHOUT ANY WARRANTY; without even the implied warranty of 
   33.13 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
   33.14 + * 
   33.15 + * Further, this software is distributed without any warranty that it is 
   33.16 + * free of the rightful claim of any third person regarding infringement 
   33.17 + * or the like.  Any license provided herein, whether implied or 
   33.18 + * otherwise, applies only to this software file.  Patent licenses, if 
   33.19 + * any, provided herein do not apply to combinations of this program with 
   33.20 + * other software, or any other product whatsoever.
   33.21 + * 
   33.22 + * You should have received a copy of the GNU General Public 
   33.23 + * License along with this program; if not, write the Free Software 
   33.24 + * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
   33.25 + * 
   33.26 + * For further information regarding this notice, see: 
   33.27 + * 
   33.28 + * http://oss.sgi.com/projects/GenInfo/NoticeExplan
   33.29 + */
   33.30 +
   33.31 +#ifndef _ASM_IA64_MACHVEC_SN2_H
   33.32 +#define _ASM_IA64_MACHVEC_SN2_H
   33.33 +
   33.34 +extern ia64_mv_setup_t sn_setup;
   33.35 +extern ia64_mv_cpu_init_t sn_cpu_init;
   33.36 +extern ia64_mv_irq_init_t sn_irq_init;
   33.37 +extern ia64_mv_send_ipi_t sn2_send_IPI;
   33.38 +extern ia64_mv_timer_interrupt_t sn_timer_interrupt;
   33.39 +extern ia64_mv_global_tlb_purge_t sn2_global_tlb_purge;
   33.40 +extern ia64_mv_tlb_migrate_finish_t	sn_tlb_migrate_finish;
   33.41 +extern ia64_mv_local_vector_to_irq sn_local_vector_to_irq;
   33.42 +extern ia64_mv_pci_get_legacy_mem_t sn_pci_get_legacy_mem;
   33.43 +extern ia64_mv_pci_legacy_read_t sn_pci_legacy_read;
   33.44 +extern ia64_mv_pci_legacy_write_t sn_pci_legacy_write;
   33.45 +extern ia64_mv_inb_t __sn_inb;
   33.46 +extern ia64_mv_inw_t __sn_inw;
   33.47 +extern ia64_mv_inl_t __sn_inl;
   33.48 +extern ia64_mv_outb_t __sn_outb;
   33.49 +extern ia64_mv_outw_t __sn_outw;
   33.50 +extern ia64_mv_outl_t __sn_outl;
   33.51 +extern ia64_mv_mmiowb_t __sn_mmiowb;
   33.52 +extern ia64_mv_readb_t __sn_readb;
   33.53 +extern ia64_mv_readw_t __sn_readw;
   33.54 +extern ia64_mv_readl_t __sn_readl;
   33.55 +extern ia64_mv_readq_t __sn_readq;
   33.56 +extern ia64_mv_readb_t __sn_readb_relaxed;
   33.57 +extern ia64_mv_readw_t __sn_readw_relaxed;
   33.58 +extern ia64_mv_readl_t __sn_readl_relaxed;
   33.59 +extern ia64_mv_readq_t __sn_readq_relaxed;
   33.60 +extern ia64_mv_dma_alloc_coherent	sn_dma_alloc_coherent;
   33.61 +extern ia64_mv_dma_free_coherent	sn_dma_free_coherent;
   33.62 +extern ia64_mv_dma_map_single		sn_dma_map_single;
   33.63 +extern ia64_mv_dma_unmap_single		sn_dma_unmap_single;
   33.64 +extern ia64_mv_dma_map_sg		sn_dma_map_sg;
   33.65 +extern ia64_mv_dma_unmap_sg		sn_dma_unmap_sg;
   33.66 +extern ia64_mv_dma_sync_single_for_cpu	sn_dma_sync_single_for_cpu;
   33.67 +extern ia64_mv_dma_sync_sg_for_cpu	sn_dma_sync_sg_for_cpu;
   33.68 +extern ia64_mv_dma_sync_single_for_device sn_dma_sync_single_for_device;
   33.69 +extern ia64_mv_dma_sync_sg_for_device	sn_dma_sync_sg_for_device;
   33.70 +extern ia64_mv_dma_mapping_error	sn_dma_mapping_error;
   33.71 +extern ia64_mv_dma_supported		sn_dma_supported;
   33.72 +extern ia64_mv_migrate_t		sn_migrate;
   33.73 +extern ia64_mv_setup_msi_irq_t		sn_setup_msi_irq;
   33.74 +extern ia64_mv_teardown_msi_irq_t	sn_teardown_msi_irq;
   33.75 +
   33.76 +
   33.77 +/*
   33.78 + * This stuff has dual use!
   33.79 + *
   33.80 + * For a generic kernel, the macros are used to initialize the
   33.81 + * platform's machvec structure.  When compiling a non-generic kernel,
   33.82 + * the macros are used directly.
   33.83 + */
   33.84 +#define platform_name			"sn2"
   33.85 +#define platform_setup			sn_setup
   33.86 +#define platform_cpu_init		sn_cpu_init
   33.87 +#define platform_irq_init		sn_irq_init
   33.88 +#define platform_send_ipi		sn2_send_IPI
   33.89 +#define platform_timer_interrupt	sn_timer_interrupt
   33.90 +#define platform_global_tlb_purge       sn2_global_tlb_purge
   33.91 +#define platform_tlb_migrate_finish	sn_tlb_migrate_finish
   33.92 +#define platform_pci_fixup		sn_pci_fixup
   33.93 +#define platform_inb			__sn_inb
   33.94 +#define platform_inw			__sn_inw
   33.95 +#define platform_inl			__sn_inl
   33.96 +#define platform_outb			__sn_outb
   33.97 +#define platform_outw			__sn_outw
   33.98 +#define platform_outl			__sn_outl
   33.99 +#define platform_mmiowb			__sn_mmiowb
  33.100 +#define platform_readb			__sn_readb
  33.101 +#define platform_readw			__sn_readw
  33.102 +#define platform_readl			__sn_readl
  33.103 +#define platform_readq			__sn_readq
  33.104 +#define platform_readb_relaxed		__sn_readb_relaxed
  33.105 +#define platform_readw_relaxed		__sn_readw_relaxed
  33.106 +#define platform_readl_relaxed		__sn_readl_relaxed
  33.107 +#define platform_readq_relaxed		__sn_readq_relaxed
  33.108 +#define platform_local_vector_to_irq	sn_local_vector_to_irq
  33.109 +#define platform_pci_get_legacy_mem	sn_pci_get_legacy_mem
  33.110 +#define platform_pci_legacy_read	sn_pci_legacy_read
  33.111 +#define platform_pci_legacy_write	sn_pci_legacy_write
  33.112 +#define platform_dma_init		machvec_noop
  33.113 +#define platform_dma_alloc_coherent	sn_dma_alloc_coherent
  33.114 +#define platform_dma_free_coherent	sn_dma_free_coherent
  33.115 +#define platform_dma_map_single		sn_dma_map_single
  33.116 +#define platform_dma_unmap_single	sn_dma_unmap_single
  33.117 +#define platform_dma_map_sg		sn_dma_map_sg
  33.118 +#define platform_dma_unmap_sg		sn_dma_unmap_sg
  33.119 +#define platform_dma_sync_single_for_cpu sn_dma_sync_single_for_cpu
  33.120 +#define platform_dma_sync_sg_for_cpu	sn_dma_sync_sg_for_cpu
  33.121 +#define platform_dma_sync_single_for_device sn_dma_sync_single_for_device
  33.122 +#define platform_dma_sync_sg_for_device	sn_dma_sync_sg_for_device
  33.123 +#define platform_dma_mapping_error		sn_dma_mapping_error
  33.124 +#define platform_dma_supported		sn_dma_supported
  33.125 +#define platform_migrate		sn_migrate
  33.126 +#ifdef CONFIG_PCI_MSI
  33.127 +#define platform_setup_msi_irq		sn_setup_msi_irq
  33.128 +#define platform_teardown_msi_irq	sn_teardown_msi_irq
  33.129 +#else
  33.130 +#define platform_setup_msi_irq		((ia64_mv_setup_msi_irq_t*)NULL)
  33.131 +#define platform_teardown_msi_irq	((ia64_mv_teardown_msi_irq_t*)NULL)
  33.132 +#endif
  33.133 +
  33.134 +#include <asm/sn/io.h>
  33.135 +
  33.136 +#endif /* _ASM_IA64_MACHVEC_SN2_H */

    34.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    34.2 +++ b/xen/include/asm-ia64/linux-xen/asm/pci.h	Wed Dec 13 11:08:40 2006 -0700
    34.3 @@ -0,0 +1,174 @@
    34.4 +#ifndef _ASM_IA64_PCI_H
    34.5 +#define _ASM_IA64_PCI_H
    34.6 +
    34.7 +#include <linux/mm.h>
    34.8 +#include <linux/slab.h>
    34.9 +#include <linux/spinlock.h>
   34.10 +#include <linux/string.h>
   34.11 +#include <linux/types.h>
   34.12 +
   34.13 +#include <asm/io.h>
   34.14 +#include <asm/scatterlist.h>
   34.15 +
   34.16 +/*
   34.17 + * Can be used to override the logic in pci_scan_bus for skipping already-configured bus
   34.18 + * numbers - to be used for buggy BIOSes or architectures with incomplete PCI setup by the
   34.19 + * loader.
   34.20 + */
   34.21 +#define pcibios_assign_all_busses()     0
   34.22 +#define pcibios_scan_all_fns(a, b)	0
   34.23 +
   34.24 +#define PCIBIOS_MIN_IO		0x1000
   34.25 +#define PCIBIOS_MIN_MEM		0x10000000
   34.26 +
   34.27 +void pcibios_config_init(void);
   34.28 +
   34.29 +struct pci_dev;
   34.30 +
   34.31 +/*
   34.32 + * PCI_DMA_BUS_IS_PHYS should be set to 1 if there is _necessarily_ a direct correspondence
   34.33 + * between device bus addresses and CPU physical addresses.  Platforms with a hardware I/O
   34.34 + * MMU _must_ turn this off to suppress the bounce buffer handling code in the block and
   34.35 + * network device layers.  Platforms with separate bus address spaces _must_ turn this off
   34.36 + * and provide a device DMA mapping implementation that takes care of the necessary
   34.37 + * address translation.
   34.38 + *
   34.39 + * For now, the ia64 platforms which may have separate/multiple bus address spaces all
   34.40 + * have I/O MMUs which support the merging of physically discontiguous buffers, so we can
   34.41 + * use that as the sole factor to determine the setting of PCI_DMA_BUS_IS_PHYS.
   34.42 + */
   34.43 +extern unsigned long ia64_max_iommu_merge_mask;
   34.44 +#define PCI_DMA_BUS_IS_PHYS	(ia64_max_iommu_merge_mask == ~0UL)
   34.45 +
   34.46 +static inline void
   34.47 +pcibios_set_master (struct pci_dev *dev)
   34.48 +{
   34.49 +	/* No special bus mastering setup handling */
   34.50 +}
   34.51 +
   34.52 +static inline void
   34.53 +pcibios_penalize_isa_irq (int irq, int active)
   34.54 +{
   34.55 +	/* We don't do dynamic PCI IRQ allocation */
   34.56 +}
   34.57 +
   34.58 +#define HAVE_ARCH_PCI_MWI 1
   34.59 +extern int pcibios_prep_mwi (struct pci_dev *);
   34.60 +
   34.61 +#include <asm-generic/pci-dma-compat.h>
   34.62 +
   34.63 +/* pci_unmap_{single,page} is not a nop, thus... */
   34.64 +#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)	\
   34.65 +	dma_addr_t ADDR_NAME;
   34.66 +#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)		\
   34.67 +	__u32 LEN_NAME;
   34.68 +#define pci_unmap_addr(PTR, ADDR_NAME)			\
   34.69 +	((PTR)->ADDR_NAME)
   34.70 +#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)		\
   34.71 +	(((PTR)->ADDR_NAME) = (VAL))
   34.72 +#define pci_unmap_len(PTR, LEN_NAME)			\
   34.73 +	((PTR)->LEN_NAME)
   34.74 +#define pci_unmap_len_set(PTR, LEN_NAME, VAL)		\
   34.75 +	(((PTR)->LEN_NAME) = (VAL))
   34.76 +
   34.77 +/* The ia64 platform always supports 64-bit addressing. */
   34.78 +#define pci_dac_dma_supported(pci_dev, mask)		(1)
   34.79 +#define pci_dac_page_to_dma(dev,pg,off,dir)		((dma_addr_t) page_to_bus(pg) + (off))
   34.80 +#define pci_dac_dma_to_page(dev,dma_addr)		(virt_to_page(bus_to_virt(dma_addr)))
   34.81 +#define pci_dac_dma_to_offset(dev,dma_addr)		offset_in_page(dma_addr)
   34.82 +#define pci_dac_dma_sync_single_for_cpu(dev,dma_addr,len,dir)	do { } while (0)
   34.83 +#define pci_dac_dma_sync_single_for_device(dev,dma_addr,len,dir)	do { mb(); } while (0)
   34.84 +
   34.85 +#define sg_dma_len(sg)		((sg)->dma_length)
   34.86 +#define sg_dma_address(sg)	((sg)->dma_address)
   34.87 +
   34.88 +#ifdef CONFIG_PCI
   34.89 +static inline void pci_dma_burst_advice(struct pci_dev *pdev,
   34.90 +					enum pci_dma_burst_strategy *strat,
   34.91 +					unsigned long *strategy_parameter)
   34.92 +{
   34.93 +	unsigned long cacheline_size;
   34.94 +	u8 byte;
   34.95 +
   34.96 +	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
   34.97 +	if (byte == 0)
   34.98 +		cacheline_size = 1024;
   34.99 +	else
  34.100 +		cacheline_size = (int) byte * 4;
  34.101 +
  34.102 +	*strat = PCI_DMA_BURST_MULTIPLE;
  34.103 +	*strategy_parameter = cacheline_size;
  34.104 +}
  34.105 +#endif
  34.106 +
  34.107 +#define HAVE_PCI_MMAP
  34.108 +extern int pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
  34.109 +				enum pci_mmap_state mmap_state, int write_combine);
  34.110 +#define HAVE_PCI_LEGACY
  34.111 +extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
  34.112 +				      struct vm_area_struct *vma);
  34.113 +extern ssize_t pci_read_legacy_io(struct kobject *kobj, char *buf, loff_t off,
  34.114 +				  size_t count);
  34.115 +extern ssize_t pci_write_legacy_io(struct kobject *kobj, char *buf, loff_t off,
  34.116 +				   size_t count);
  34.117 +extern int pci_mmap_legacy_mem(struct kobject *kobj,
  34.118 +			       struct bin_attribute *attr,
  34.119 +			       struct vm_area_struct *vma);
  34.120 +
  34.121 +#define pci_get_legacy_mem platform_pci_get_legacy_mem
  34.122 +#define pci_legacy_read platform_pci_legacy_read
  34.123 +#define pci_legacy_write platform_pci_legacy_write
  34.124 +
  34.125 +struct pci_window {
  34.126 +	struct resource resource;
  34.127 +	u64 offset;
  34.128 +};
  34.129 +
  34.130 +struct pci_controller {
  34.131 +	void *acpi_handle;
  34.132 +	void *iommu;
  34.133 +	int segment;
  34.134 +	int node;		/* nearest node with memory or -1 for global allocation */
  34.135 +
  34.136 +	unsigned int windows;
  34.137 +	struct pci_window *window;
  34.138 +
  34.139 +	void *platform_data;
  34.140 +};
  34.141 +
  34.142 +#define PCI_CONTROLLER(busdev) ((struct pci_controller *) busdev->sysdata)
  34.143 +#define pci_domain_nr(busdev)    (PCI_CONTROLLER(busdev)->segment)
  34.144 +
  34.145 +extern struct pci_ops pci_root_ops;
  34.146 +
  34.147 +static inline int pci_proc_domain(struct pci_bus *bus)
  34.148 +{
  34.149 +	return (pci_domain_nr(bus) != 0);
  34.150 +}
  34.151 +
  34.152 +static inline void pcibios_add_platform_entries(struct pci_dev *dev)
  34.153 +{
  34.154 +}
  34.155 +
  34.156 +extern void pcibios_resource_to_bus(struct pci_dev *dev,
  34.157 +		struct pci_bus_region *region, struct resource *res);
  34.158 +
  34.159 +extern void pcibios_bus_to_resource(struct pci_dev *dev,
  34.160 +		struct resource *res, struct pci_bus_region *region);
  34.161 +
  34.162 +static inline struct resource *
  34.163 +pcibios_select_root(struct pci_dev *pdev, struct resource *res)
  34.164 +{
  34.165 +	struct resource *root = NULL;
  34.166 +
  34.167 +	if (res->flags & IORESOURCE_IO)
  34.168 +		root = &ioport_resource;
  34.169 +	if (res->flags & IORESOURCE_MEM)
  34.170 +		root = &iomem_resource;
  34.171 +
  34.172 +	return root;
  34.173 +}
  34.174 +
  34.175 +#define pcibios_scan_all_fns(a, b)	0
  34.176 +
  34.177 +#endif /* _ASM_IA64_PCI_H */

    35.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    35.2 +++ b/xen/include/asm-ia64/linux-xen/asm/sn/README.origin	Wed Dec 13 11:08:40 2006 -0700
    35.3 @@ -0,0 +1,16 @@
    35.4 +# Source files in this directory are near-identical copies of linux-2.6.19
    35.5 +# files:
    35.6 +
    35.7 +# NOTE: ALL changes to these files should be clearly marked
    35.8 +# (e.g. with #ifdef XEN or XEN in a comment) so that they can be
    35.9 +# easily updated to future versions of the corresponding Linux files.
   35.10 +
   35.11 +addrs.h			-> linux/include/asm-ia64/sn/addrs.h
   35.12 +arch.h			-> linux/include/asm-ia64/sn/arch.h
   35.13 +hubdev.h		-> linux/arch/ia64/sn/include/xtalk/hubdev.h
   35.14 +intr.h			-> linux/include/asm-ia64/sn/intr.h
   35.15 +io.h			-> linux/include/asm-ia64/sn/io.h
   35.16 +nodepda.h		-> linux/include/asm-ia64/sn/nodepda.h
   35.17 +pcibr_provider.h	-> linux/include/asm-ia64/sn/pcibr_provider.h
   35.18 +rw_mmr.h		-> linux/include/asm-ia64/sn/rw_mmr.h
   35.19 +types.h			-> linux/include/asm-ia64/sn/types.h

    36.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    36.2 +++ b/xen/include/asm-ia64/linux-xen/asm/sn/addrs.h	Wed Dec 13 11:08:40 2006 -0700
    36.3 @@ -0,0 +1,299 @@
    36.4 +/*
    36.5 + * This file is subject to the terms and conditions of the GNU General Public
    36.6 + * License.  See the file "COPYING" in the main directory of this archive
    36.7 + * for more details.
    36.8 + *
    36.9 + * Copyright (c) 1992-1999,2001-2005 Silicon Graphics, Inc. All rights reserved.
   36.10 + */
   36.11 +
   36.12 +#ifndef _ASM_IA64_SN_ADDRS_H
   36.13 +#define _ASM_IA64_SN_ADDRS_H
   36.14 +
   36.15 +#include <asm/percpu.h>
   36.16 +#include <asm/sn/types.h>
   36.17 +#include <asm/sn/arch.h>
   36.18 +#include <asm/sn/pda.h>
   36.19 +
   36.20 +/*
   36.21 + *  Memory/SHUB Address Format:
   36.22 + *  +-+---------+--+--------------+
   36.23 + *  |0|  NASID  |AS| NodeOffset   |
   36.24 + *  +-+---------+--+--------------+
   36.25 + *
   36.26 + *  NASID: (low NASID bit is 0) Memory and SHUB MMRs
   36.27 + *   AS: 2-bit Address Space Identifier. Used only if low NASID bit is 0
   36.28 + *     00: Local Resources and MMR space
   36.29 + *           Top bit of NodeOffset
   36.30 + *               0: Local resources space
   36.31 + *                  node id:
   36.32 + *                        0: IA64/NT compatibility space
   36.33 + *                        2: Local MMR Space
   36.34 + *                        4: Local memory, regardless of local node id
   36.35 + *               1: Global MMR space
   36.36 + *     01: GET space.
   36.37 + *     10: AMO space.
   36.38 + *     11: Cacheable memory space.
   36.39 + *
   36.40 + *   NodeOffset: byte offset
   36.41 + *
   36.42 + *
   36.43 + *  TIO address format:
   36.44 + *  +-+----------+--+--------------+
   36.45 + *  |0|  NASID   |AS| Nodeoffset   |
   36.46 + *  +-+----------+--+--------------+
   36.47 + *
   36.48 + *  NASID: (low NASID bit is 1) TIO
   36.49 + *   AS: 2-bit Chiplet Identifier
   36.50 + *     00: TIO LB (Indicates TIO MMR access.)
   36.51 + *     01: TIO ICE (indicates coretalk space access.)
   36.52 + * 
   36.53 + *   NodeOffset: top bit must be set.
   36.54 + *
   36.55 + *
   36.56 + * Note that in both of the above address formats, the low
   36.57 + * NASID bit indicates if the reference is to the SHUB or TIO MMRs.
   36.58 + */
   36.59 +
   36.60 +
   36.61 +/*
   36.62 + * Define basic shift & mask constants for manipulating NASIDs and AS values.
   36.63 + */
   36.64 +#define NASID_BITMASK		(sn_hub_info->nasid_bitmask)
   36.65 +#define NASID_SHIFT		(sn_hub_info->nasid_shift)
   36.66 +#define AS_SHIFT		(sn_hub_info->as_shift)
   36.67 +#define AS_BITMASK		0x3UL
   36.68 +
   36.69 +#define NASID_MASK              ((u64)NASID_BITMASK << NASID_SHIFT)
   36.70 +#define AS_MASK			((u64)AS_BITMASK << AS_SHIFT)
   36.71 +
   36.72 +
   36.73 +/*
   36.74 + * AS values. These are the same on both SHUB1 & SHUB2.
   36.75 + */
   36.76 +#define AS_GET_VAL		1UL
   36.77 +#define AS_AMO_VAL		2UL
   36.78 +#define AS_CAC_VAL		3UL
   36.79 +#define AS_GET_SPACE		(AS_GET_VAL << AS_SHIFT)
   36.80 +#define AS_AMO_SPACE		(AS_AMO_VAL << AS_SHIFT)
   36.81 +#define AS_CAC_SPACE		(AS_CAC_VAL << AS_SHIFT)
   36.82 +
   36.83 +
   36.84 +/* 
   36.85 + * Virtual Mode Local & Global MMR space.  
   36.86 + */
   36.87 +#define SH1_LOCAL_MMR_OFFSET	0x8000000000UL
   36.88 +#define SH2_LOCAL_MMR_OFFSET	0x0200000000UL
   36.89 +#define LOCAL_MMR_OFFSET	(is_shub2() ? SH2_LOCAL_MMR_OFFSET : SH1_LOCAL_MMR_OFFSET)
   36.90 +#define LOCAL_MMR_SPACE		(__IA64_UNCACHED_OFFSET | LOCAL_MMR_OFFSET)
   36.91 +#define LOCAL_PHYS_MMR_SPACE	(RGN_BASE(RGN_HPAGE) | LOCAL_MMR_OFFSET)
   36.92 +
   36.93 +#define SH1_GLOBAL_MMR_OFFSET	0x0800000000UL
   36.94 +#define SH2_GLOBAL_MMR_OFFSET	0x0300000000UL
   36.95 +#define GLOBAL_MMR_OFFSET	(is_shub2() ? SH2_GLOBAL_MMR_OFFSET : SH1_GLOBAL_MMR_OFFSET)
   36.96 +#define GLOBAL_MMR_SPACE	(__IA64_UNCACHED_OFFSET | GLOBAL_MMR_OFFSET)
   36.97 +
   36.98 +/*
   36.99 + * Physical mode addresses
  36.100 + */
  36.101 +#define GLOBAL_PHYS_MMR_SPACE	(RGN_BASE(RGN_HPAGE) | GLOBAL_MMR_OFFSET)
  36.102 +
  36.103 +
  36.104 +/*
  36.105 + * Clear region & AS bits.
  36.106 + */
  36.107 +#define TO_PHYS_MASK		(~(RGN_BITS | AS_MASK))
  36.108 +
  36.109 +
  36.110 +/*
  36.111 + * Misc NASID manipulation.
  36.112 + */
  36.113 +#define NASID_SPACE(n)		((u64)(n) << NASID_SHIFT)
  36.114 +#define REMOTE_ADDR(n,a)	(NASID_SPACE(n) | (a))
  36.115 +#define NODE_OFFSET(x)		((x) & (NODE_ADDRSPACE_SIZE - 1))
  36.116 +#define NODE_ADDRSPACE_SIZE     (1UL << AS_SHIFT)
  36.117 +#define NASID_GET(x)		(int) (((u64) (x) >> NASID_SHIFT) & NASID_BITMASK)
  36.118 +#define LOCAL_MMR_ADDR(a)	(LOCAL_MMR_SPACE | (a))
  36.119 +#define GLOBAL_MMR_ADDR(n,a)	(GLOBAL_MMR_SPACE | REMOTE_ADDR(n,a))
  36.120 +#define GLOBAL_MMR_PHYS_ADDR(n,a) (GLOBAL_PHYS_MMR_SPACE | REMOTE_ADDR(n,a))
  36.121 +#define GLOBAL_CAC_ADDR(n,a)	(CAC_BASE | REMOTE_ADDR(n,a))
  36.122 +#define CHANGE_NASID(n,x)	((void *)(((u64)(x) & ~NASID_MASK) | NASID_SPACE(n)))
  36.123 +#define IS_TIO_NASID(n)		((n) & 1)
  36.124 +
  36.125 +
  36.126 +/* non-II mmr's start at top of big window space (4G) */
  36.127 +#define BWIN_TOP		0x0000000100000000UL
  36.128 +
  36.129 +/*
  36.130 + * general address defines
  36.131 + */
  36.132 +#define CAC_BASE		(PAGE_OFFSET | AS_CAC_SPACE)
  36.133 +#define AMO_BASE		(__IA64_UNCACHED_OFFSET | AS_AMO_SPACE)
  36.134 +#define AMO_PHYS_BASE		(RGN_BASE(RGN_HPAGE) | AS_AMO_SPACE)
  36.135 +#define GET_BASE		(PAGE_OFFSET | AS_GET_SPACE)
  36.136 +
  36.137 +/*
  36.138 + * Convert Memory addresses between various addressing modes.
  36.139 + */
  36.140 +#define TO_PHYS(x)		(TO_PHYS_MASK & (x))
  36.141 +#define TO_CAC(x)		(CAC_BASE     | TO_PHYS(x))
  36.142 +#ifdef CONFIG_SGI_SN
  36.143 +#define TO_AMO(x)		(AMO_BASE     | TO_PHYS(x))
  36.144 +#define TO_GET(x)		(GET_BASE     | TO_PHYS(x))
  36.145 +#else
  36.146 +#define TO_AMO(x)		({ BUG(); x; })
  36.147 +#define TO_GET(x)		({ BUG(); x; })
  36.148 +#endif
  36.149 +
  36.150 +/*
  36.151 + * Covert from processor physical address to II/TIO physical address:
  36.152 + *	II - squeeze out the AS bits
  36.153 + *	TIO- requires a chiplet id in bits 38-39.  For DMA to memory,
  36.154 + *           the chiplet id is zero.  If we implement TIO-TIO dma, we might need
  36.155 + *           to insert a chiplet id into this macro.  However, it is our belief
  36.156 + *           right now that this chiplet id will be ICE, which is also zero.
  36.157 + */
  36.158 +#define SH1_TIO_PHYS_TO_DMA(x) 						\
  36.159 +	((((u64)(NASID_GET(x))) << 40) | NODE_OFFSET(x))
  36.160 +
  36.161 +#define SH2_NETWORK_BANK_OFFSET(x) 					\
  36.162 +        ((u64)(x) & ((1UL << (sn_hub_info->nasid_shift - 4)) -1))
  36.163 +
  36.164 +#define SH2_NETWORK_BANK_SELECT(x) 					\
  36.165 +        ((((u64)(x) & (0x3UL << (sn_hub_info->nasid_shift - 4)))	\
  36.166 +        	>> (sn_hub_info->nasid_shift - 4)) << 36)
  36.167 +
  36.168 +#define SH2_NETWORK_ADDRESS(x) 						\
  36.169 +	(SH2_NETWORK_BANK_OFFSET(x) | SH2_NETWORK_BANK_SELECT(x))
  36.170 +
  36.171 +#define SH2_TIO_PHYS_TO_DMA(x) 						\
  36.172 +        (((u64)(NASID_GET(x)) << 40) | 	SH2_NETWORK_ADDRESS(x))
  36.173 +
  36.174 +#define PHYS_TO_TIODMA(x)						\
  36.175 +	(is_shub1() ? SH1_TIO_PHYS_TO_DMA(x) : SH2_TIO_PHYS_TO_DMA(x))
  36.176 +
  36.177 +#define PHYS_TO_DMA(x)							\
  36.178 +	((((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x))
  36.179 +
  36.180 +
  36.181 +/*
  36.182 + * Macros to test for address type.
  36.183 + */
  36.184 +#define IS_AMO_ADDRESS(x)	(((u64)(x) & (RGN_BITS | AS_MASK)) == AMO_BASE)
  36.185 +#define IS_AMO_PHYS_ADDRESS(x)	(((u64)(x) & (RGN_BITS | AS_MASK)) == AMO_PHYS_BASE)
  36.186 +
  36.187 +
  36.188 +/*
  36.189 + * The following definitions pertain to the IO special address
  36.190 + * space.  They define the location of the big and little windows
  36.191 + * of any given node.
  36.192 + */
  36.193 +#define BWIN_SIZE_BITS			29	/* big window size: 512M */
  36.194 +#define TIO_BWIN_SIZE_BITS		30	/* big window size: 1G */
  36.195 +#define NODE_SWIN_BASE(n, w)		((w == 0) ? NODE_BWIN_BASE((n), SWIN0_BIGWIN) \
  36.196 +		: RAW_NODE_SWIN_BASE(n, w))
  36.197 +#define TIO_SWIN_BASE(n, w) 		(TIO_IO_BASE(n) + \
  36.198 +					    ((u64) (w) << TIO_SWIN_SIZE_BITS))
  36.199 +#define NODE_IO_BASE(n)			(GLOBAL_MMR_SPACE | NASID_SPACE(n))
  36.200 +#define TIO_IO_BASE(n)                  (__IA64_UNCACHED_OFFSET | NASID_SPACE(n))
  36.201 +#define BWIN_SIZE			(1UL << BWIN_SIZE_BITS)
  36.202 +#define NODE_BWIN_BASE0(n)		(NODE_IO_BASE(n) + BWIN_SIZE)
  36.203 +#define NODE_BWIN_BASE(n, w)		(NODE_BWIN_BASE0(n) + ((u64) (w) << BWIN_SIZE_BITS))
  36.204 +#define RAW_NODE_SWIN_BASE(n, w)	(NODE_IO_BASE(n) + ((u64) (w) << SWIN_SIZE_BITS))
  36.205 +#define BWIN_WIDGET_MASK		0x7
  36.206 +#define BWIN_WINDOWNUM(x)		(((x) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
  36.207 +#define SH1_IS_BIG_WINDOW_ADDR(x)	((x) & BWIN_TOP)
  36.208 +
  36.209 +#define TIO_BWIN_WINDOW_SELECT_MASK	0x7
  36.210 +#define TIO_BWIN_WINDOWNUM(x)		(((x) >> TIO_BWIN_SIZE_BITS) & TIO_BWIN_WINDOW_SELECT_MASK)
  36.211 +
  36.212 +#define TIO_HWIN_SHIFT_BITS		33
  36.213 +#define TIO_HWIN(x)			(NODE_OFFSET(x) >> TIO_HWIN_SHIFT_BITS)
  36.214 +
  36.215 +/*
  36.216 + * The following definitions pertain to the IO special address
  36.217 + * space.  They define the location of the big and little windows
  36.218 + * of any given node.
  36.219 + */
  36.220 +
  36.221 +#define SWIN_SIZE_BITS			24
  36.222 +#define	SWIN_WIDGET_MASK		0xF
  36.223 +
  36.224 +#define TIO_SWIN_SIZE_BITS		28
  36.225 +#define TIO_SWIN_SIZE			(1UL << TIO_SWIN_SIZE_BITS)
  36.226 +#define TIO_SWIN_WIDGET_MASK		0x3
  36.227 +
  36.228 +/*
  36.229 + * Convert smallwindow address to xtalk address.
  36.230 + *
  36.231 + * 'addr' can be physical or virtual address, but will be converted
  36.232 + * to Xtalk address in the range 0 -> SWINZ_SIZEMASK
  36.233 + */
  36.234 +#define	SWIN_WIDGETNUM(x)		(((x)  >> SWIN_SIZE_BITS) & SWIN_WIDGET_MASK)
  36.235 +#define TIO_SWIN_WIDGETNUM(x)		(((x)  >> TIO_SWIN_SIZE_BITS) & TIO_SWIN_WIDGET_MASK)
  36.236 +
  36.237 +
  36.238 +/*
  36.239 + * The following macros produce the correct base virtual address for
  36.240 + * the hub registers. The REMOTE_HUB_* macro produce
  36.241 + * the address for the specified hub's registers.  The intent is
  36.242 + * that the appropriate PI, MD, NI, or II register would be substituted
  36.243 + * for x.
  36.244 + *
  36.245 + *   WARNING:
  36.246 + *	When certain Hub chip workaround are defined, it's not sufficient
  36.247 + *	to dereference the *_HUB_ADDR() macros.  You should instead use
  36.248 + *	HUB_L() and HUB_S() if you must deal with pointers to hub registers.
  36.249 + *	Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S().
  36.250 + *	They're always safe.
  36.251 + */
  36.252 +/* Shub1 TIO & MMR addressing macros */
  36.253 +#define SH1_TIO_IOSPACE_ADDR(n,x)					\
  36.254 +	GLOBAL_MMR_ADDR(n,x)
  36.255 +
  36.256 +#define SH1_REMOTE_BWIN_MMR(n,x)					\
  36.257 +	GLOBAL_MMR_ADDR(n,x)
  36.258 +
  36.259 +#define SH1_REMOTE_SWIN_MMR(n,x)					\
  36.260 +	(NODE_SWIN_BASE(n,1) + 0x800000UL + (x))
  36.261 +
  36.262 +#define SH1_REMOTE_MMR(n,x)						\
  36.263 +	(SH1_IS_BIG_WINDOW_ADDR(x) ? SH1_REMOTE_BWIN_MMR(n,x) :		\
  36.264 +	 	SH1_REMOTE_SWIN_MMR(n,x))
  36.265 +
  36.266 +/* Shub1 TIO & MMR addressing macros */
  36.267 +#define SH2_TIO_IOSPACE_ADDR(n,x)					\
  36.268 +	((__IA64_UNCACHED_OFFSET | REMOTE_ADDR(n,x) | 1UL << (NASID_SHIFT - 2)))
  36.269 +
  36.270 +#define SH2_REMOTE_MMR(n,x)						\
  36.271 +	GLOBAL_MMR_ADDR(n,x)
  36.272 +
  36.273 +
  36.274 +/* TIO & MMR addressing macros that work on both shub1 & shub2 */
  36.275 +#define TIO_IOSPACE_ADDR(n,x)						\
  36.276 +	((u64 *)(is_shub1() ? SH1_TIO_IOSPACE_ADDR(n,x) :		\
  36.277 +		 SH2_TIO_IOSPACE_ADDR(n,x)))
  36.278 +
  36.279 +#define SH_REMOTE_MMR(n,x)						\
  36.280 +	(is_shub1() ? SH1_REMOTE_MMR(n,x) : SH2_REMOTE_MMR(n,x))
  36.281 +
  36.282 +#define REMOTE_HUB_ADDR(n,x)						\
  36.283 +	(IS_TIO_NASID(n) ?  ((volatile u64*)TIO_IOSPACE_ADDR(n,x)) :	\
  36.284 +	 ((volatile u64*)SH_REMOTE_MMR(n,x)))
  36.285 +
  36.286 +
  36.287 +#define HUB_L(x)			(*((volatile typeof(*x) *)x))
  36.288 +#define	HUB_S(x,d)			(*((volatile typeof(*x) *)x) = (d))
  36.289 +
  36.290 +#define REMOTE_HUB_L(n, a)		HUB_L(REMOTE_HUB_ADDR((n), (a)))
  36.291 +#define REMOTE_HUB_S(n, a, d)		HUB_S(REMOTE_HUB_ADDR((n), (a)), (d))
  36.292 +
  36.293 +/*
  36.294 + * Coretalk address breakdown
  36.295 + */
  36.296 +#define CTALK_NASID_SHFT		40
  36.297 +#define CTALK_NASID_MASK		(0x3FFFULL << CTALK_NASID_SHFT)
  36.298 +#define CTALK_CID_SHFT			38
  36.299 +#define CTALK_CID_MASK			(0x3ULL << CTALK_CID_SHFT)
  36.300 +#define CTALK_NODE_OFFSET		0x3FFFFFFFFF
  36.301 +
  36.302 +#endif /* _ASM_IA64_SN_ADDRS_H */