ia64/xen-unstable

changeset 619:c085fac641e2

bitkeeper revision 1.346 (3f12d24eDP51QT3SN0jrYvODuq4Qhw)

Merge labyrinth.cl.cam.ac.uk:/auto/groups/xeno/BK/xeno.bk
into labyrinth.cl.cam.ac.uk:/auto/anfs/scratch/labyrinth/iap10/xeno-clone/xeno.bk
author iap10@labyrinth.cl.cam.ac.uk
date Mon Jul 14 15:54:54 2003 +0000 (2003-07-14)
parents 18c36f61f4cd c7557b3832b9
children 130cefbcfdc4
files .rootkeys tools/internal/dom0_defs.h xen/arch/i386/apic.c xen/arch/i386/entry.S xen/arch/i386/io_apic.c xen/arch/i386/nmi.c xen/arch/i386/setup.c xen/arch/i386/traps.c xen/include/asm-i386/hardirq.h xen/include/asm-i386/msr.h xen/include/xeno/irq_cpustat.h
line diff
     1.1 --- a/.rootkeys	Mon Jul 14 14:29:46 2003 +0000
     1.2 +++ b/.rootkeys	Mon Jul 14 15:54:54 2003 +0000
     1.3 @@ -159,6 +159,7 @@ 3ddb79bc1uNlAtc-84Ioq4qfcnI_CQ xen/arch/
     1.4  3ddb79bdqfIcjkz_h9Hvtp8Tk_19Zw xen/arch/i386/irq.c
     1.5  3ddb79bcHwuCQDjBICDTSis52hWguw xen/arch/i386/mm.c
     1.6  3ddb79bdS4UeWWXDH-FaBKqcpMFcnw xen/arch/i386/mpparse.c
     1.7 +3f12cff65EV3qOG2j37Qm0ShgvXGRw xen/arch/i386/nmi.c
     1.8  3ddb79bcnL-_Dtsbtjgxl7vJU3vBiQ xen/arch/i386/pci-dma.c
     1.9  3ddb79bdeJ7_86z03yTAPIeeywOg3Q xen/arch/i386/pci-i386.c
    1.10  3ddb79bdIKgipvGoqExEQ7jawfVowA xen/arch/i386/pci-i386.h
     2.1 --- a/tools/internal/dom0_defs.h	Mon Jul 14 14:29:46 2003 +0000
     2.2 +++ b/tools/internal/dom0_defs.h	Mon Jul 14 15:54:54 2003 +0000
     2.3 @@ -14,7 +14,14 @@
     2.4  #include <errno.h>
     2.5  #include <string.h>
     2.6  
     2.7 -#include <asm/types.h>
     2.8 +typedef unsigned char      u8;
     2.9 +typedef unsigned short     u16;
    2.10 +typedef unsigned long      u32;
    2.11 +typedef unsigned long long u64;
    2.12 +typedef signed char        s8;
    2.13 +typedef signed short       s16;
    2.14 +typedef signed long        s32;
    2.15 +typedef signed long long   s64;
    2.16  
    2.17  #include "mem_defs.h"
    2.18  #include <asm-xeno/proc_cmd.h>
    2.19 @@ -29,7 +36,7 @@
    2.20  
    2.21  static inline int do_privcmd(unsigned int cmd, unsigned long data)
    2.22  {
    2.23 -    int fd;
    2.24 +    int fd, ret;
    2.25  
    2.26      if ( (fd = open("/proc/xeno/privcmd", O_RDWR)) < 0 )
    2.27      {
    2.28 @@ -37,7 +44,7 @@ static inline int do_privcmd(unsigned in
    2.29          return -1;
    2.30      }
    2.31  
    2.32 -    if ( ioctl(fd, cmd, data) < 0 )
    2.33 +    if ( (ret = ioctl(fd, cmd, data)) < 0 )
    2.34      {
    2.35  #ifndef SILENT_ERRORS_FROM_XEN
    2.36          PERROR("Error when executing privileged control ioctl");
    2.37 @@ -47,7 +54,7 @@ static inline int do_privcmd(unsigned in
    2.38      }
    2.39  
    2.40      close(fd);
    2.41 -    return 0;
    2.42 +    return ret;
    2.43  }
    2.44  
    2.45  static inline int xldev_to_physdev(int xldev)
     3.1 --- a/xen/arch/i386/apic.c	Mon Jul 14 14:29:46 2003 +0000
     3.2 +++ b/xen/arch/i386/apic.c	Mon Jul 14 15:54:54 2003 +0000
     3.3 @@ -353,6 +353,9 @@ void __init setup_local_APIC (void)
     3.4      } else {
     3.5          printk("No ESR for 82489DX.\n");
     3.6      }
     3.7 +
     3.8 +	if (nmi_watchdog == NMI_LOCAL_APIC)
     3.9 +		setup_apic_nmi_watchdog();
    3.10  }
    3.11  
    3.12  
    3.13 @@ -413,6 +416,8 @@ static int __init detect_init_APIC (void
    3.14      set_bit(X86_FEATURE_APIC, &boot_cpu_data.x86_capability);
    3.15      mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
    3.16      boot_cpu_physical_apicid = 0;
    3.17 +	if (nmi_watchdog != NMI_NONE)
    3.18 +		nmi_watchdog = NMI_LOCAL_APIC;
    3.19  
    3.20      printk("Found and enabled local APIC!\n");
    3.21      apic_pm_init1();
     4.1 --- a/xen/arch/i386/entry.S	Mon Jul 14 14:29:46 2003 +0000
     4.2 +++ b/xen/arch/i386/entry.S	Mon Jul 14 15:54:54 2003 +0000
     4.3 @@ -131,7 +131,7 @@ CF_MASK		= 0x00000001
     4.4  IF_MASK		= 0x00000200
     4.5  NT_MASK		= 0x00004000
     4.6  
     4.7 -#define SAVE_ALL \
     4.8 +#define SAVE_ALL_NOSTI \
     4.9  	cld; \
    4.10  	pushl %gs; \
    4.11  	pushl %fs; \
    4.12 @@ -146,8 +146,11 @@ NT_MASK		= 0x00004000
    4.13  	pushl %ebx; \
    4.14  	movl $(__HYPERVISOR_DS),%edx; \
    4.15  	movl %edx,%ds; \
    4.16 -	movl %edx,%es; \
    4.17 -        sti; 
    4.18 +	movl %edx,%es;
    4.19 +
    4.20 +#define SAVE_ALL \
    4.21 +	SAVE_ALL_NOSTI \
    4.22 +	sti;
    4.23  
    4.24  #define RESTORE_ALL	\
    4.25  	popl %ebx;	\
    4.26 @@ -554,7 +557,7 @@ ENTRY(debug)
    4.27  
    4.28  ENTRY(nmi)
    4.29  	pushl %eax
    4.30 -	SAVE_ALL
    4.31 +	SAVE_ALL_NOSTI
    4.32  	movl %esp,%edx
    4.33  	pushl $0
    4.34  	pushl %edx
     5.1 --- a/xen/arch/i386/io_apic.c	Mon Jul 14 14:29:46 2003 +0000
     5.2 +++ b/xen/arch/i386/io_apic.c	Mon Jul 14 15:54:54 2003 +0000
     5.3 @@ -34,8 +34,6 @@
     5.4  
     5.5  #ifdef CONFIG_X86_IO_APIC
     5.6  
     5.7 -static unsigned int nmi_watchdog;  /* XXXX XEN */
     5.8 -
     5.9  #undef APIC_LOCKUP_DEBUG
    5.10  
    5.11  #define APIC_LOCKUP_DEBUG
    5.12 @@ -1641,15 +1639,8 @@ static inline void check_timer(void)
    5.13  		 * Ok, does IRQ0 through the IOAPIC work?
    5.14  		 */
    5.15  		unmask_IO_APIC_irq(0);
    5.16 -		if (timer_irq_works()) {
    5.17 -			if (nmi_watchdog == NMI_IO_APIC) {
    5.18 -				disable_8259A_irq(0);
    5.19 -				setup_nmi();
    5.20 -				enable_8259A_irq(0);
    5.21 -				// XXX Xen check_nmi_watchdog();
    5.22 -			}
    5.23 +		if (timer_irq_works())
    5.24  			return;
    5.25 -		}
    5.26  		clear_IO_APIC_pin(0, pin1);
    5.27  		printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
    5.28  	}
    5.29 @@ -1667,10 +1658,6 @@ static inline void check_timer(void)
    5.30  				replace_pin_at_irq(0, 0, pin1, 0, pin2);
    5.31  			else
    5.32  				add_pin_to_irq(0, 0, pin2);
    5.33 -			if (nmi_watchdog == NMI_IO_APIC) {
    5.34 -				setup_nmi();
    5.35 -				// XXX Xen check_nmi_watchdog();
    5.36 -			}
    5.37  			return;
    5.38  		}
    5.39  		/*
    5.40 @@ -1680,11 +1667,6 @@ static inline void check_timer(void)
    5.41  	}
    5.42  	printk(" failed.\n");
    5.43  
    5.44 -	if (nmi_watchdog) {
    5.45 -		printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
    5.46 -		nmi_watchdog = 0;
    5.47 -	}
    5.48 -
    5.49  	printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
    5.50  
    5.51  	disable_8259A_irq(0);
     6.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     6.2 +++ b/xen/arch/i386/nmi.c	Mon Jul 14 15:54:54 2003 +0000
     6.3 @@ -0,0 +1,275 @@
     6.4 +/*
     6.5 + *  linux/arch/i386/nmi.c
     6.6 + *
     6.7 + *  NMI watchdog support on APIC systems
     6.8 + *
     6.9 + *  Started by Ingo Molnar <mingo@redhat.com>
    6.10 + *
    6.11 + *  Fixes:
    6.12 + *  Mikael Pettersson	: AMD K7 support for local APIC NMI watchdog.
    6.13 + *  Mikael Pettersson	: Power Management for local APIC NMI watchdog.
    6.14 + *  Mikael Pettersson	: Pentium 4 support for local APIC NMI watchdog.
    6.15 + */
    6.16 +
    6.17 +#include <linux/config.h>
    6.18 +#include <linux/init.h>
    6.19 +#include <linux/lib.h>
    6.20 +#include <linux/mm.h>
    6.21 +#include <linux/irq.h>
    6.22 +#include <linux/delay.h>
    6.23 +#include <linux/interrupt.h>
    6.24 +#include <linux/time.h>
    6.25 +#include <linux/timex.h>
    6.26 +#include <linux/sched.h>
    6.27 +
    6.28 +#include <asm/mc146818rtc.h>
    6.29 +#include <asm/smp.h>
    6.30 +#include <asm/msr.h>
    6.31 +#include <asm/mpspec.h>
    6.32 +
    6.33 +#undef Dprintk
    6.34 +#define Dprintk(x...) printk(x)
    6.35 +
    6.36 +unsigned int nmi_watchdog = NMI_LOCAL_APIC;
    6.37 +static unsigned int nmi_hz = HZ;
    6.38 +unsigned int nmi_perfctr_msr;	/* the MSR to reset in NMI handler */
    6.39 +extern void show_registers(struct pt_regs *regs);
    6.40 +
    6.41 +#define K7_EVNTSEL_ENABLE	(1 << 22)
    6.42 +#define K7_EVNTSEL_INT		(1 << 20)
    6.43 +#define K7_EVNTSEL_OS		(1 << 17)
    6.44 +#define K7_EVNTSEL_USR		(1 << 16)
    6.45 +#define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING	0x76
    6.46 +#define K7_NMI_EVENT		K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
    6.47 +
    6.48 +#define P6_EVNTSEL0_ENABLE	(1 << 22)
    6.49 +#define P6_EVNTSEL_INT		(1 << 20)
    6.50 +#define P6_EVNTSEL_OS		(1 << 17)
    6.51 +#define P6_EVNTSEL_USR		(1 << 16)
    6.52 +#define P6_EVENT_CPU_CLOCKS_NOT_HALTED	0x79
    6.53 +#define P6_NMI_EVENT		P6_EVENT_CPU_CLOCKS_NOT_HALTED
    6.54 +
    6.55 +#define MSR_P4_MISC_ENABLE	0x1A0
    6.56 +#define MSR_P4_MISC_ENABLE_PERF_AVAIL	(1<<7)
    6.57 +#define MSR_P4_MISC_ENABLE_PEBS_UNAVAIL	(1<<12)
    6.58 +#define MSR_P4_PERFCTR0		0x300
    6.59 +#define MSR_P4_CCCR0		0x360
    6.60 +#define P4_ESCR_EVENT_SELECT(N)	((N)<<25)
    6.61 +#define P4_ESCR_OS		(1<<3)
    6.62 +#define P4_ESCR_USR		(1<<2)
    6.63 +#define P4_CCCR_OVF_PMI		(1<<26)
    6.64 +#define P4_CCCR_THRESHOLD(N)	((N)<<20)
    6.65 +#define P4_CCCR_COMPLEMENT	(1<<19)
    6.66 +#define P4_CCCR_COMPARE		(1<<18)
    6.67 +#define P4_CCCR_REQUIRED	(3<<16)
    6.68 +#define P4_CCCR_ESCR_SELECT(N)	((N)<<13)
    6.69 +#define P4_CCCR_ENABLE		(1<<12)
    6.70 +/* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
    6.71 +   CRU_ESCR0 (with any non-null event selector) through a complemented
    6.72 +   max threshold. [IA32-Vol3, Section 14.9.9] */
    6.73 +#define MSR_P4_IQ_COUNTER0	0x30C
    6.74 +#define MSR_P4_IQ_CCCR0		0x36C
    6.75 +#define MSR_P4_CRU_ESCR0	0x3B8
    6.76 +#define P4_NMI_CRU_ESCR0	(P4_ESCR_EVENT_SELECT(0x3F)|P4_ESCR_OS|P4_ESCR_USR)
    6.77 +#define P4_NMI_IQ_CCCR0	\
    6.78 +	(P4_CCCR_OVF_PMI|P4_CCCR_THRESHOLD(15)|P4_CCCR_COMPLEMENT|	\
    6.79 +	 P4_CCCR_COMPARE|P4_CCCR_REQUIRED|P4_CCCR_ESCR_SELECT(4)|P4_CCCR_ENABLE)
    6.80 +
    6.81 +int __init check_nmi_watchdog (void)
    6.82 +{
    6.83 +    unsigned int prev_nmi_count[NR_CPUS];
    6.84 +    int j, cpu;
    6.85 +    
    6.86 +    printk("testing NMI watchdog ---\n");
    6.87 +
    6.88 +    for (j = 0; j < smp_num_cpus; j++) {
    6.89 +        cpu = cpu_logical_map(j);
    6.90 +        prev_nmi_count[cpu] = irq_stat[cpu].__nmi_count;
    6.91 +    }
    6.92 +    sti();
    6.93 +    mdelay((10*1000)/nmi_hz); /* wait 10 ticks */
    6.94 +
    6.95 +    for (j = 0; j < smp_num_cpus; j++) {
    6.96 +        cpu = cpu_logical_map(j);
    6.97 +        if (nmi_count(cpu) - prev_nmi_count[cpu] <= 5)
    6.98 +            printk("CPU#%d: NMI stuck? (Hyperthread secondary CPU?)\n", cpu);
    6.99 +        else
   6.100 +            printk("CPU#%d: NMI okay\n", cpu);
   6.101 +    }
   6.102 +
   6.103 +    /* now that we know it works we can reduce NMI frequency to
   6.104 +       something more reasonable; makes a difference in some configs */
   6.105 +    if (nmi_watchdog == NMI_LOCAL_APIC)
   6.106 +        nmi_hz = 1;
   6.107 +
   6.108 +    return 0;
   6.109 +}
   6.110 +
   6.111 +static inline void nmi_pm_init(void) { }
   6.112 +#define __pminit	__init
   6.113 +
   6.114 +/*
   6.115 + * Activate the NMI watchdog via the local APIC.
   6.116 + * Original code written by Keith Owens.
   6.117 + */
   6.118 +
   6.119 +static void __pminit clear_msr_range(unsigned int base, unsigned int n)
   6.120 +{
   6.121 +    unsigned int i;
   6.122 +
   6.123 +    for(i = 0; i < n; ++i)
   6.124 +        wrmsr(base+i, 0, 0);
   6.125 +}
   6.126 +
   6.127 +static void __pminit setup_k7_watchdog(void)
   6.128 +{
   6.129 +    unsigned int evntsel;
   6.130 +
   6.131 +    nmi_perfctr_msr = MSR_K7_PERFCTR0;
   6.132 +
   6.133 +    clear_msr_range(MSR_K7_EVNTSEL0, 4);
   6.134 +    clear_msr_range(MSR_K7_PERFCTR0, 4);
   6.135 +
   6.136 +    evntsel = K7_EVNTSEL_INT
   6.137 +        | K7_EVNTSEL_OS
   6.138 +        | K7_EVNTSEL_USR
   6.139 +        | K7_NMI_EVENT;
   6.140 +
   6.141 +    wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
   6.142 +    Dprintk("setting K7_PERFCTR0 to %08lx\n", -(cpu_khz/nmi_hz*1000));
   6.143 +    wrmsr(MSR_K7_PERFCTR0, -(cpu_khz/nmi_hz*1000), -1);
   6.144 +    apic_write(APIC_LVTPC, APIC_DM_NMI);
   6.145 +    evntsel |= K7_EVNTSEL_ENABLE;
   6.146 +    wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
   6.147 +}
   6.148 +
   6.149 +static void __pminit setup_p6_watchdog(void)
   6.150 +{
   6.151 +    unsigned int evntsel;
   6.152 +
   6.153 +    nmi_perfctr_msr = MSR_P6_PERFCTR0;
   6.154 +
   6.155 +    clear_msr_range(MSR_P6_EVNTSEL0, 2);
   6.156 +    clear_msr_range(MSR_P6_PERFCTR0, 2);
   6.157 +
   6.158 +    evntsel = P6_EVNTSEL_INT
   6.159 +        | P6_EVNTSEL_OS
   6.160 +        | P6_EVNTSEL_USR
   6.161 +        | P6_NMI_EVENT;
   6.162 +
   6.163 +    wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
   6.164 +    Dprintk("setting P6_PERFCTR0 to %08lx\n", -(cpu_khz/nmi_hz*1000));
   6.165 +    wrmsr(MSR_P6_PERFCTR0, -(cpu_khz/nmi_hz*1000), 0);
   6.166 +    apic_write(APIC_LVTPC, APIC_DM_NMI);
   6.167 +    evntsel |= P6_EVNTSEL0_ENABLE;
   6.168 +    wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
   6.169 +}
   6.170 +
   6.171 +static int __pminit setup_p4_watchdog(void)
   6.172 +{
   6.173 +    unsigned int misc_enable, dummy;
   6.174 +
   6.175 +    rdmsr(MSR_P4_MISC_ENABLE, misc_enable, dummy);
   6.176 +    if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
   6.177 +        return 0;
   6.178 +
   6.179 +    nmi_perfctr_msr = MSR_P4_IQ_COUNTER0;
   6.180 +
   6.181 +    if (!(misc_enable & MSR_P4_MISC_ENABLE_PEBS_UNAVAIL))
   6.182 +        clear_msr_range(0x3F1, 2);
   6.183 +    /* MSR 0x3F0 seems to have a default value of 0xFC00, but current
   6.184 +       docs doesn't fully define it, so leave it alone for now. */
   6.185 +    clear_msr_range(0x3A0, 31);
   6.186 +    clear_msr_range(0x3C0, 6);
   6.187 +    clear_msr_range(0x3C8, 6);
   6.188 +    clear_msr_range(0x3E0, 2);
   6.189 +    clear_msr_range(MSR_P4_CCCR0, 18);
   6.190 +    clear_msr_range(MSR_P4_PERFCTR0, 18);
   6.191 +
   6.192 +    wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0);
   6.193 +    wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0);
   6.194 +    Dprintk("setting P4_IQ_COUNTER0 to 0x%08lx\n", -(cpu_khz/nmi_hz*1000));
   6.195 +    wrmsr(MSR_P4_IQ_COUNTER0, -(cpu_khz/nmi_hz*1000), -1);
   6.196 +    apic_write(APIC_LVTPC, APIC_DM_NMI);
   6.197 +    wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0, 0);
   6.198 +    return 1;
   6.199 +}
   6.200 +
   6.201 +void __pminit setup_apic_nmi_watchdog (void)
   6.202 +{
   6.203 +    switch (boot_cpu_data.x86_vendor) {
   6.204 +    case X86_VENDOR_AMD:
   6.205 +        if (boot_cpu_data.x86 != 6 && boot_cpu_data.x86 != 15)
   6.206 +            return;
   6.207 +        setup_k7_watchdog();
   6.208 +        break;
   6.209 +    case X86_VENDOR_INTEL:
   6.210 +        switch (boot_cpu_data.x86) {
   6.211 +        case 6:
   6.212 +            setup_p6_watchdog();
   6.213 +            break;
   6.214 +        case 15:
   6.215 +            if (!setup_p4_watchdog())
   6.216 +                return;
   6.217 +            break;
   6.218 +        default:
   6.219 +            return;
   6.220 +        }
   6.221 +        break;
   6.222 +    default:
   6.223 +        return;
   6.224 +    }
   6.225 +    nmi_pm_init();
   6.226 +}
   6.227 +
   6.228 +
   6.229 +static unsigned int
   6.230 +last_irq_sums [NR_CPUS],
   6.231 +    alert_counter [NR_CPUS];
   6.232 +
   6.233 +void touch_nmi_watchdog (void)
   6.234 +{
   6.235 +    int i;
   6.236 +    for (i = 0; i < smp_num_cpus; i++)
   6.237 +        alert_counter[i] = 0;
   6.238 +}
   6.239 +
   6.240 +void nmi_watchdog_tick (struct pt_regs * regs)
   6.241 +{
   6.242 +    extern spinlock_t console_lock;
   6.243 +    extern void die(const char * str, struct pt_regs * regs, long err);
   6.244 +    extern void putchar_serial(unsigned char c);
   6.245 +
   6.246 +    int sum, cpu = smp_processor_id();
   6.247 +
   6.248 +    sum = apic_timer_irqs[cpu];
   6.249 +    
   6.250 +    if (last_irq_sums[cpu] == sum) {
   6.251 +        /*
   6.252 +         * Ayiee, looks like this CPU is stuck ... wait a few IRQs (5 seconds) 
   6.253 +         * before doing the oops ...
   6.254 +         */
   6.255 +        alert_counter[cpu]++;
   6.256 +        if (alert_counter[cpu] == 5*nmi_hz) {
   6.257 +            console_lock = SPIN_LOCK_UNLOCKED;
   6.258 +            die("NMI Watchdog detected LOCKUP on CPU", regs, cpu);
   6.259 +        }
   6.260 +    } else {
   6.261 +        last_irq_sums[cpu] = sum;
   6.262 +        alert_counter[cpu] = 0;
   6.263 +    }
   6.264 +
   6.265 +    if (nmi_perfctr_msr) {
   6.266 +        if (nmi_perfctr_msr == MSR_P4_IQ_COUNTER0) {
   6.267 +            /*
   6.268 +             * P4 quirks: - An overflown perfctr will assert its interrupt
   6.269 +             *   until the OVF flag in its CCCR is cleared. - LVTPC is masked 
   6.270 +             * on interrupt and must be
   6.271 +             *   unmasked by the LVTPC handler.
   6.272 +             */
   6.273 +            wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0, 0);
   6.274 +            apic_write(APIC_LVTPC, APIC_DM_NMI);
   6.275 +        }
   6.276 +        wrmsr(nmi_perfctr_msr, -(cpu_khz/nmi_hz*1000), -1);
   6.277 +    }
   6.278 +}
     7.1 --- a/xen/arch/i386/setup.c	Mon Jul 14 14:29:46 2003 +0000
     7.2 +++ b/xen/arch/i386/setup.c	Mon Jul 14 15:54:54 2003 +0000
     7.3 @@ -148,7 +148,8 @@ void __init identify_cpu(struct cpuinfo_
     7.4              c->x86_capability[2] = cpuid_edx(0x80860001);
     7.5      }
     7.6  
     7.7 -    printk("CPU: Before vendor init, caps: %08x %08x %08x, vendor = %d\n",
     7.8 +    printk("CPU%d: Before vendor init, caps: %08x %08x %08x, vendor = %d\n",
     7.9 +           smp_processor_id(),
    7.10             c->x86_capability[0],
    7.11             c->x86_capability[1],
    7.12             c->x86_capability[2],
    7.13 @@ -345,13 +346,15 @@ void __init start_of_day(void)
    7.14  #endif
    7.15      initialize_keytable(); /* call back handling for key codes      */
    7.16  
    7.17 -	disable_pit();		/* not needed anymore */
    7.18 -	ac_timer_init();    /* init accurate timers */
    7.19 -	init_xeno_time();	/* initialise the time */
    7.20 -	schedulers_start(); /* start scheduler for each CPU */
    7.21 +    disable_pit();		/* not needed anymore */
    7.22 +    ac_timer_init();    /* init accurate timers */
    7.23 +    init_xeno_time();	/* initialise the time */
    7.24 +    schedulers_start(); /* start scheduler for each CPU */
    7.25  
    7.26      sti();
    7.27  
    7.28 +    check_nmi_watchdog();
    7.29 +
    7.30      zap_low_mappings();
    7.31      kmem_cache_init();
    7.32      kmem_cache_sizes_init(max_page);
    7.33 @@ -369,7 +372,6 @@ void __init start_of_day(void)
    7.34      net_init();            /* initializes virtual network system. */
    7.35      initialize_block_io(); /* setup block devices */
    7.36  
    7.37 -
    7.38  #ifdef CONFIG_SMP
    7.39      wait_init_idle = cpu_online_map;
    7.40      clear_bit(smp_processor_id(), &wait_init_idle);
     8.1 --- a/xen/arch/i386/traps.c	Mon Jul 14 14:29:46 2003 +0000
     8.2 +++ b/xen/arch/i386/traps.c	Mon Jul 14 15:54:54 2003 +0000
     8.3 @@ -470,7 +470,15 @@ asmlinkage void do_nmi(struct pt_regs * 
     8.4  {
     8.5      unsigned char reason = inb(0x61);
     8.6  
     8.7 +    ++nmi_count(smp_processor_id());
     8.8 +
     8.9      if (!(reason & 0xc0)) {
    8.10 +#if CONFIG_X86_LOCAL_APIC
    8.11 +        if (nmi_watchdog) {
    8.12 +            nmi_watchdog_tick(regs);
    8.13 +            return;
    8.14 +        }
    8.15 +#endif
    8.16          unknown_nmi_error(reason, regs);
    8.17          return;
    8.18      }
     9.1 --- a/xen/include/asm-i386/hardirq.h	Mon Jul 14 14:29:46 2003 +0000
     9.2 +++ b/xen/include/asm-i386/hardirq.h	Mon Jul 14 15:54:54 2003 +0000
     9.3 @@ -10,6 +10,7 @@ typedef struct {
     9.4  	unsigned int __local_irq_count;
     9.5  	unsigned int __local_bh_count;
     9.6  	unsigned int __syscall_count;
     9.7 +	unsigned int __nmi_count;
     9.8  	unsigned long idle_timestamp;
     9.9  } ____cacheline_aligned irq_cpustat_t;
    9.10  
    10.1 --- a/xen/include/asm-i386/msr.h	Mon Jul 14 14:29:46 2003 +0000
    10.2 +++ b/xen/include/asm-i386/msr.h	Mon Jul 14 15:54:54 2003 +0000
    10.3 @@ -48,17 +48,16 @@
    10.4  #define MSR_IA32_UCODE_WRITE		0x79
    10.5  #define MSR_IA32_UCODE_REV		0x8b
    10.6  
    10.7 -#define MSR_IA32_PERFCTR0		0xc1
    10.8 -#define MSR_IA32_PERFCTR1		0xc2
    10.9 -
   10.10  #define MSR_IA32_BBL_CR_CTL		0x119
   10.11  
   10.12  #define MSR_IA32_MCG_CAP		0x179
   10.13  #define MSR_IA32_MCG_STATUS		0x17a
   10.14  #define MSR_IA32_MCG_CTL		0x17b
   10.15  
   10.16 -#define MSR_IA32_EVNTSEL0		0x186
   10.17 -#define MSR_IA32_EVNTSEL1		0x187
   10.18 +#define MSR_IA32_THERM_CONTROL		0x19a
   10.19 +#define MSR_IA32_THERM_INTERRUPT	0x19b
   10.20 +#define MSR_IA32_THERM_STATUS		0x19c
   10.21 +#define MSR_IA32_MISC_ENABLE		0x1a0
   10.22  
   10.23  #define MSR_IA32_DEBUGCTLMSR		0x1d9
   10.24  #define MSR_IA32_LASTBRANCHFROMIP	0x1db
   10.25 @@ -71,16 +70,26 @@
   10.26  #define MSR_IA32_MC0_ADDR		0x402
   10.27  #define MSR_IA32_MC0_MISC		0x403
   10.28  
   10.29 +#define MSR_P6_PERFCTR0			0xc1
   10.30 +#define MSR_P6_PERFCTR1			0xc2
   10.31 +#define MSR_P6_EVNTSEL0			0x186
   10.32 +#define MSR_P6_EVNTSEL1			0x187
   10.33 +
   10.34  /* AMD Defined MSRs */
   10.35  #define MSR_K6_EFER			0xC0000080
   10.36  #define MSR_K6_STAR			0xC0000081
   10.37  #define MSR_K6_WHCR			0xC0000082
   10.38  #define MSR_K6_UWCCR			0xC0000085
   10.39 +#define MSR_K6_EPMR			0xC0000086
   10.40  #define MSR_K6_PSOR			0xC0000087
   10.41  #define MSR_K6_PFIR			0xC0000088
   10.42  
   10.43  #define MSR_K7_EVNTSEL0			0xC0010000
   10.44  #define MSR_K7_PERFCTR0			0xC0010004
   10.45 +#define MSR_K7_HWCR			0xC0010015
   10.46 +#define MSR_K7_CLK_CTL			0xC001001b
   10.47 +#define MSR_K7_FID_VID_CTL		0xC0010041
   10.48 +#define MSR_K7_VID_STATUS		0xC0010042
   10.49  
   10.50  /* Centaur-Hauls/IDT defined MSRs. */
   10.51  #define MSR_IDT_FCR1			0x107
   10.52 @@ -100,5 +109,13 @@
   10.53  
   10.54  /* VIA Cyrix defined MSRs*/
   10.55  #define MSR_VIA_FCR			0x1107
   10.56 +#define MSR_VIA_LONGHAUL		0x110a
   10.57 +#define MSR_VIA_BCR2			0x1147
   10.58 +
   10.59 +/* Transmeta defined MSRs */
   10.60 +#define MSR_TMTA_LONGRUN_CTRL		0x80868010
   10.61 +#define MSR_TMTA_LONGRUN_FLAGS		0x80868011
   10.62 +#define MSR_TMTA_LRTI_READOUT		0x80868018
   10.63 +#define MSR_TMTA_LRTI_VOLT_MHZ		0x8086801a
   10.64  
   10.65  #endif /* __ASM_MSR_H */
    11.1 --- a/xen/include/xeno/irq_cpustat.h	Mon Jul 14 14:29:46 2003 +0000
    11.2 +++ b/xen/include/xeno/irq_cpustat.h	Mon Jul 14 15:54:54 2003 +0000
    11.3 @@ -30,5 +30,6 @@ extern irq_cpustat_t irq_stat[];			/* de
    11.4  #define local_irq_count(cpu)	__IRQ_STAT((cpu), __local_irq_count)
    11.5  #define local_bh_count(cpu)	__IRQ_STAT((cpu), __local_bh_count)
    11.6  #define syscall_count(cpu)	__IRQ_STAT((cpu), __syscall_count)
    11.7 +#define nmi_count(cpu)		__IRQ_STAT((cpu), __nmi_count)
    11.8  
    11.9  #endif	/* __irq_cpustat_h */