ia64/xen-unstable

changeset 1352:bee8626be37a

bitkeeper revision 1.887.1.2 (409a50dbLW3CCQd-ZdsTiKjfkeHXCw)

Fix calculation of TSS offset on SMP systems when creating bounce frame.
author mwilli2@equilibrium.research.intel-research.net
date Thu May 06 14:51:07 2004 +0000 (2004-05-06)
parents f290b4d93576
children 74d515393e65
files xen/arch/i386/entry.S xen/include/asm-i386/processor.h
line diff
     1.1 --- a/xen/arch/i386/entry.S	Thu May 06 11:18:49 2004 +0000
     1.2 +++ b/xen/arch/i386/entry.S	Thu May 06 14:51:07 2004 +0000
     1.3 @@ -406,7 +406,11 @@ create_bounce_frame:
     1.4          jz   1f /* jump if returning to an existing ring-1 activation */
     1.5          /* obtain ss/esp from TSS -- no current ring-1 activations */
     1.6          movzwl PROCESSOR(%ebx),%eax
     1.7 -        shll $8,%eax /* multiply by 256 */
     1.8 +        /* next 4 lines multiply %eax by 8320, which is sizeof(tss_struct) */
     1.9 +        movl %eax, %ecx
    1.10 +        shll $7, %ecx
    1.11 +        shll $13, %eax
    1.12 +        addl %ecx,%eax
    1.13          addl $init_tss + 12,%eax
    1.14          movl (%eax),%esi /* tss->esp1 */
    1.15  FAULT6: movl 4(%eax),%ds /* tss->ss1  */
     2.1 --- a/xen/include/asm-i386/processor.h	Thu May 06 11:18:49 2004 +0000
     2.2 +++ b/xen/include/asm-i386/processor.h	Thu May 06 14:51:07 2004 +0000
     2.3 @@ -375,7 +375,7 @@ struct tss_struct {
     2.4      unsigned short	trace, bitmap;
     2.5      unsigned long	io_bitmap[IO_BITMAP_SIZE+1];
     2.6      /*
     2.7 -     * pads the TSS to be cacheline-aligned (size is 0x100)
     2.8 +     * pads the TSS to be cacheline-aligned (total size is 0x2080)
     2.9       */
    2.10      unsigned long __cacheline_filler[5];
    2.11  };