1.1 --- a/tools/ioemu/hw/piix4acpi.c	Fri May 11 10:07:06 2007 +0100
     1.2 +++ b/tools/ioemu/hw/piix4acpi.c	Sat May 12 09:48:33 2007 +0100
     1.3 @@ -24,30 +24,12 @@
     1.4   */
     1.5  
     1.6  #include "vl.h"
     1.7 -#define FREQUENCE_PMTIMER  3579545
     1.8 -/* acpi register bit define here  */
     1.9  
    1.10 -/* PM1_STS */
    1.11 -#define TMROF_STS         (1 << 0)
    1.12 -#define BM_STS            (1 << 4)
    1.13 -#define GBL_STS           (1 << 5)
    1.14 -#define PWRBTN_STS        (1 << 8)
    1.15 -#define RTC_STS           (1 << 10)
    1.16 -#define PRBTNOR_STS       (1 << 11)
    1.17 -#define WAK_STS           (1 << 15)
    1.18 -/* PM1_EN */
    1.19 -#define TMROF_EN          (1 << 0)
    1.20 -#define GBL_EN            (1 << 5)
    1.21 -#define PWRBTN_EN         (1 << 8)
    1.22 -#define RTC_EN            (1 << 10)
    1.23 -/* PM1_CNT */
    1.24 -#define SCI_EN            (1 << 0)
    1.25 -#define GBL_RLS           (1 << 2)
    1.26 -#define SLP_EN            (1 << 13)
    1.27 -
    1.28 -/* Bits of PM1a register define here  */
    1.29 -#define SLP_TYP_MASK    0x1C00
    1.30 -#define SLP_VAL         0x1C00
    1.31 +/* PMCNTRL */
    1.32 +#define SCI_EN            (1 <<  0)
    1.33 +#define GBL_RLS           (1 <<  2)
    1.34 +#define SUS_TYP           (7 << 10)
    1.35 +#define SUS_EN            (1 << 13)
    1.36  
    1.37  typedef struct AcpiDeviceState AcpiDeviceState;
    1.38  AcpiDeviceState *acpi_device_table;
    1.39 @@ -80,90 +62,58 @@ static int piix4acpi_load(QEMUFile *f, v
    1.40  static void acpiPm1Control_writeb(void *opaque, uint32_t addr, uint32_t val)
    1.41  {
    1.42      PCIAcpiState *s = opaque;
    1.43 -
    1.44      s->pm1_control = (s->pm1_control & 0xff00) | (val & 0xff);
    1.45 -/*  printf("acpiPm1Control_writeb \n addr %x val:%x\n", addr, val); */
    1.46 -
    1.47  }
    1.48  
    1.49  static uint32_t acpiPm1Control_readb(void *opaque, uint32_t addr)
    1.50  {
    1.51      PCIAcpiState *s = opaque;
    1.52 -    uint32_t val;
    1.53 -
    1.54      /* Mask out the write-only bits */
    1.55 -    val = s->pm1_control & ~(GBL_RLS|SLP_EN) & 0xff;
    1.56 -/*    printf("acpiPm1Control_readb \n addr %x val:%x\n", addr, val); */
    1.57 -
    1.58 -    return val;
    1.59 +    return (uint8_t)(s->pm1_control & ~(GBL_RLS|SUS_EN));
    1.60  }
    1.61  
    1.62  static void acpiPm1ControlP1_writeb(void *opaque, uint32_t addr, uint32_t val)
    1.63  {
    1.64      PCIAcpiState *s = opaque;
    1.65  
    1.66 -    s->pm1_control = (s->pm1_control & 0xff) | (val << 8);
    1.67 -/*    printf("acpiPm1ControlP1_writeb \n addr %x val:%x\n", addr, val); */
    1.68 +    val <<= 8;
    1.69 +    s->pm1_control = ((s->pm1_control & 0xff) | val) & ~SUS_EN;
    1.70  
    1.71 -    // Check for power off request
    1.72 -    val <<= 8;
    1.73 -    if (((val & SLP_EN) != 0) &&
    1.74 -        ((val & SLP_TYP_MASK) == SLP_VAL)) {
    1.75 +    /* Check for power off request. */
    1.76 +    if ((val & (SUS_EN|SUS_TYP)) == SUS_EN)
    1.77          qemu_system_shutdown_request();
    1.78 -    }
    1.79  }
    1.80  
    1.81  static uint32_t acpiPm1ControlP1_readb(void *opaque, uint32_t addr)
    1.82  {
    1.83      PCIAcpiState *s = opaque;
    1.84 -    uint32_t val;
    1.85 -
    1.86      /* Mask out the write-only bits */
    1.87 -    val = (s->pm1_control & ~(GBL_RLS|SLP_EN)) >> 8;
    1.88 -/*    printf("acpiPm1ControlP1_readb \n addr %x val:%x\n", addr, val); */
    1.89 -
    1.90 -    return val;
    1.91 +    return (uint8_t)((s->pm1_control & ~(GBL_RLS|SUS_EN)) >> 8);
    1.92  }
    1.93  
    1.94 -
    1.95 -/* word access   */
    1.96 -
    1.97  static void acpiPm1Control_writew(void *opaque, uint32_t addr, uint32_t val)
    1.98  {
    1.99      PCIAcpiState *s = opaque;
   1.100  
   1.101 -    s->pm1_control = val;
   1.102 -/*    printf("acpiPm1Control_writew \n addr %x val:%x\n", addr, val); */
   1.103 -
   1.104 -    // Check for power off request
   1.105 +    s->pm1_control = val & ~SUS_EN;
   1.106  
   1.107 -    if (((val & SLP_EN) != 0) &&
   1.108 -        ((val & SLP_TYP_MASK) == SLP_VAL)) {
   1.109 +    /* Check for power off request. */
   1.110 +    if ((val & (SUS_EN|SUS_TYP)) == SUS_EN)
   1.111          qemu_system_shutdown_request();
   1.112 -    }
   1.113 -
   1.114  }
   1.115  
   1.116  static uint32_t acpiPm1Control_readw(void *opaque, uint32_t addr)
   1.117  {
   1.118      PCIAcpiState *s = opaque;
   1.119 -    uint32_t val;
   1.120 -
   1.121      /* Mask out the write-only bits */
   1.122 -    val = s->pm1_control & ~(GBL_RLS|SLP_EN);
   1.123 -/*    printf("acpiPm1Control_readw \n addr %x val:%x\n", addr, val);  */
   1.124 -
   1.125 -    return val;
   1.126 +    return (s->pm1_control & ~(GBL_RLS|SUS_EN));
   1.127  }
   1.128  
   1.129 -
   1.130  static void acpi_map(PCIDevice *pci_dev, int region_num,
   1.131                      uint32_t addr, uint32_t size, int type)
   1.132  {
   1.133      PCIAcpiState *d = (PCIAcpiState *)pci_dev;
   1.134  
   1.135 -    printf("register acpi io\n");
   1.136 -
   1.137      /* Byte access */
   1.138      register_ioport_write(addr + 4, 1, 1, acpiPm1Control_writeb, d);
   1.139      register_ioport_read(addr + 4, 1, 1, acpiPm1Control_readb, d);