1.1 --- a/xen/arch/ia64/vmx/vmx_ivt.S	Fri Nov 07 12:05:14 2008 +0900
     1.2 +++ b/xen/arch/ia64/vmx/vmx_ivt.S	Fri Nov 07 19:34:59 2008 +0900
     1.3 @@ -343,7 +343,7 @@ END(vmx_alt_itlb_miss)
     1.4  // 0x1000 Entry 4 (size 64 bundles) Alt DTLB (7,46)
     1.5  ENTRY(vmx_alt_dtlb_miss)
     1.6      VMX_DBG_FAULT(4)
     1.7 -    mov r29=cr.ipsr
     1.8 +    mov r29=cr.ipsr	//frametable_miss needs ipsr is saved in r29.
     1.9      mov r31=pr
    1.10      adds r22=IA64_VCPU_MMU_MODE_OFFSET, r21
    1.11      ;;
    1.12 @@ -356,7 +356,7 @@ vmx_alt_dtlb_miss_vmm:
    1.13      // Test for the address of virtual frame_table
    1.14      shr r22=r16,56;;
    1.15      cmp.eq p8,p0=((VIRT_FRAME_TABLE_ADDR>>56)&0xff)-0x100,r22
    1.16 -(p8)br.cond.sptk frametable_miss ;;
    1.17 +(p8)br.cond.sptk frametable_miss ;; //Make sure ipsr is saved in r29
    1.18  #endif
    1.19      movl r17=PAGE_KERNEL
    1.20      mov r20=cr.isr

     2.1 --- a/xen/arch/ia64/xen/ivt.S	Fri Nov 07 12:05:14 2008 +0900
     2.2 +++ b/xen/arch/ia64/xen/ivt.S	Fri Nov 07 19:34:59 2008 +0900
     2.3 @@ -184,10 +184,12 @@ ENTRY(alt_dtlb_miss)
     2.4  late_alt_dtlb_miss:
     2.5  	mov r20=cr.isr
     2.6  	movl r17=PAGE_KERNEL
     2.7 -	mov r21=cr.ipsr
     2.8 +	mov r29=cr.ipsr // frametable_miss is shared by paravirtual and HVM sides
     2.9 +			// and it assumes ipsr is saved in r29. If change the
    2.10 +			// registers usage here, please check both sides!   
    2.11  	movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
    2.12  	;;
    2.13 -	extr.u r23=r21,IA64_PSR_CPL0_BIT,2	// extract psr.cpl
    2.14 +	extr.u r23=r29,IA64_PSR_CPL0_BIT,2	// extract psr.cpl
    2.15  	and r22=IA64_ISR_CODE_MASK,r20		// get the isr.code field
    2.16  	tbit.nz p6,p7=r20,IA64_ISR_SP_BIT	// is speculation bit on?
    2.17  	extr.u r18=r16,XEN_VIRT_UC_BIT,1	// extract UC bit
    2.18 @@ -234,7 +236,7 @@ late_alt_dtlb_miss:
    2.19  	br.cond.spnt page_fault
    2.20  	;;
    2.21  alt_dtlb_miss_identity_map:
    2.22 -	dep r21=-1,r21,IA64_PSR_ED_BIT,1
    2.23 +	dep r29=-1,r29,IA64_PSR_ED_BIT,1
    2.24  	or r19=r19,r17		// insert PTE control bits into r19
    2.25  	mov cr.itir=r20		// set itir with cleared key
    2.26  	;;
    2.27 @@ -243,7 +245,7 @@ alt_dtlb_miss_identity_map:
    2.28  	cmp.eq.or p8,p0=0x18,r22	// Region 6 is UC for EFI
    2.29  	;;
    2.30  (p8)	dep r19=-1,r19,4,1	// set bit 4 (uncached) if access to UC area
    2.31 -(p6)	mov cr.ipsr=r21
    2.32 +(p6)	mov cr.ipsr=r29
    2.33  	;;
    2.34  (p7)	itc.d r19		// insert the TLB entry
    2.35  	mov pr=r31,-1
    2.36 @@ -288,17 +290,17 @@ GLOBAL_ENTRY(frametable_miss)
    2.37  	rfi
    2.38  END(frametable_miss)
    2.39  
    2.40 -ENTRY(frametable_fault)
    2.41 +ENTRY(frametable_fault)		//ipsr saved in r29 before coming here!
    2.42  	ssm psr.dt		// switch to using virtual data addressing
    2.43  	mov r18=cr.iip
    2.44  	movl r19=ia64_frametable_probe
    2.45  	;;
    2.46  	cmp.eq p6,p7=r18,r19	// is faulting addrress ia64_frametable_probe?
    2.47  	mov r8=0		// assumes that 'probe.r' uses r8
    2.48 -	dep r21=-1,r21,IA64_PSR_RI_BIT+1,1 // return to next instruction in
    2.49 +	dep r29=-1,r29,IA64_PSR_RI_BIT+1,1 // return to next instruction in
    2.50  					   //   bundle 2
    2.51  	;;
    2.52 -(p6)	mov cr.ipsr=r21
    2.53 +(p6)	mov cr.ipsr=r29
    2.54  	mov r19=4		// FAULT(4)
    2.55  (p7)	br.spnt.few dispatch_to_fault_handler
    2.56  	;;