ia64/xen-unstable

changeset 15071:8f510bf078c7

[qemu] Remove atomic_set_bit, atomic_clear_bit and ia64_intrinsic.h and its
users.

Signed-off-by: Christian Limpach <Christian.Limpach@xensource.com>
author Christian Limpach <Christian.Limpach@xensource.com>
date Thu May 10 15:58:35 2007 +0100 (2007-05-10)
parents a4467c0971ba
children 31a3f83d1610
files tools/ioemu/cpu-all.h tools/ioemu/exec-all.h tools/ioemu/ia64_intrinsic.h
line diff
     1.1 --- a/tools/ioemu/cpu-all.h	Thu May 10 15:39:28 2007 +0100
     1.2 +++ b/tools/ioemu/cpu-all.h	Thu May 10 15:58:35 2007 +0100
     1.3 @@ -828,48 +828,6 @@ int cpu_inw(CPUState *env, int addr);
     1.4  int cpu_inl(CPUState *env, int addr);
     1.5  #endif
     1.6  
     1.7 -#if defined(__i386__) || defined(__x86_64__)
     1.8 -static __inline__ void atomic_set_bit(long nr, volatile void *addr)
     1.9 -{
    1.10 -        __asm__ __volatile__(
    1.11 -                "lock ; bts %1,%0"
    1.12 -                :"=m" (*(volatile long *)addr)
    1.13 -                :"dIr" (nr));
    1.14 -}
    1.15 -static __inline__ void atomic_clear_bit(long nr, volatile void *addr)
    1.16 -{
    1.17 -        __asm__ __volatile__(
    1.18 -                "lock ; btr %1,%0"
    1.19 -                :"=m" (*(volatile long *)addr)
    1.20 -                :"dIr" (nr));
    1.21 -}
    1.22 -#elif defined(__ia64__)
    1.23 -#include "ia64_intrinsic.h"
    1.24 -#define atomic_set_bit(nr, addr) ({					\
    1.25 -	typeof(*addr) bit, old, new;					\
    1.26 -	volatile typeof(*addr) *m;					\
    1.27 -									\
    1.28 -	m = (volatile typeof(*addr)*)(addr + nr / (8*sizeof(*addr)));	\
    1.29 -	bit = 1 << (nr % (8*sizeof(*addr)));				\
    1.30 -	do {								\
    1.31 -		old = *m;						\
    1.32 -		new = old | bit;					\
    1.33 -	} while (cmpxchg_acq(m, old, new) != old);			\
    1.34 -})
    1.35 -
    1.36 -#define atomic_clear_bit(nr, addr) ({					\
    1.37 -	typeof(*addr) bit, old, new;					\
    1.38 -	volatile typeof(*addr) *m;					\
    1.39 -									\
    1.40 -	m = (volatile typeof(*addr)*)(addr + nr / (8*sizeof(*addr)));	\
    1.41 -	bit = ~(1 << (nr % (8*sizeof(*addr))));				\
    1.42 -	do {								\
    1.43 -		old = *m;						\
    1.44 -		new = old & bit;					\
    1.45 -	} while (cmpxchg_acq(m, old, new) != old);			\
    1.46 -})
    1.47 -#endif
    1.48 -
    1.49  /* memory API */
    1.50  
    1.51  extern uint64_t phys_ram_size;
     2.1 --- a/tools/ioemu/exec-all.h	Thu May 10 15:39:28 2007 +0100
     2.2 +++ b/tools/ioemu/exec-all.h	Thu May 10 15:58:35 2007 +0100
     2.3 @@ -357,6 +357,7 @@ extern CPUWriteMemoryFunc *io_mem_write[
     2.4  extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
     2.5  extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
     2.6  
     2.7 +#ifndef CONFIG_DM
     2.8  #ifdef __powerpc__
     2.9  static inline int testandset (int *p)
    2.10  {
    2.11 @@ -472,15 +473,15 @@ static inline int testandset (int *p)
    2.12  }
    2.13  #endif
    2.14  
    2.15 -#ifdef __ia64__
    2.16 -#include "ia64_intrinsic.h"
    2.17 +#ifdef __ia64
    2.18 +#include <ia64intrin.h>
    2.19  
    2.20  static inline int testandset (int *p)
    2.21  {
    2.22 -    uint32_t o = 0, n = 1;
    2.23 -    return (int)cmpxchg_acq(p, o, n);
    2.24 +    return __sync_lock_test_and_set (p, 1);
    2.25  }
    2.26  #endif
    2.27 +#endif /* !CONFIG_DM */
    2.28  
    2.29  typedef int spinlock_t;
    2.30  
     3.1 --- a/tools/ioemu/ia64_intrinsic.h	Thu May 10 15:39:28 2007 +0100
     3.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     3.3 @@ -1,276 +0,0 @@
     3.4 -#ifndef IA64_INTRINSIC_H
     3.5 -#define IA64_INTRINSIC_H
     3.6 -
     3.7 -/*
     3.8 - * Compiler-dependent Intrinsics
     3.9 - *
    3.10 - * Copyright (C) 2002,2003 Jun Nakajima <jun.nakajima@intel.com>
    3.11 - * Copyright (C) 2002,2003 Suresh Siddha <suresh.b.siddha@intel.com>
    3.12 - *
    3.13 - */
    3.14 -extern long ia64_cmpxchg_called_with_bad_pointer (void);
    3.15 -extern void ia64_bad_param_for_getreg (void);
    3.16 -#define ia64_cmpxchg(sem,ptr,o,n,s) ({					\
    3.17 -	uint64_t _o, _r;						\
    3.18 -	switch(s) {							\
    3.19 -		case 1: _o = (uint8_t)(long)(o); break;			\
    3.20 -		case 2: _o = (uint16_t)(long)(o); break;		\
    3.21 -		case 4: _o = (uint32_t)(long)(o); break;		\
    3.22 -		case 8: _o = (uint64_t)(long)(o); break;		\
    3.23 -		default: break;						\
    3.24 -	}								\
    3.25 -	switch(s) {							\
    3.26 -		case 1:							\
    3.27 -		_r = ia64_cmpxchg1_##sem((uint8_t*)ptr,n,_o); break;	\
    3.28 -		case 2:							\
    3.29 -		_r = ia64_cmpxchg2_##sem((uint16_t*)ptr,n,_o); break;	\
    3.30 -		case 4:							\
    3.31 -		_r = ia64_cmpxchg4_##sem((uint32_t*)ptr,n,_o); break;	\
    3.32 -		case 8:							\
    3.33 -		_r = ia64_cmpxchg8_##sem((uint64_t*)ptr,n,_o); break;	\
    3.34 -		default:						\
    3.35 -		_r = ia64_cmpxchg_called_with_bad_pointer(); break;	\
    3.36 -	}								\
    3.37 -	(__typeof__(o)) _r;						\
    3.38 -})
    3.39 -
    3.40 -#define cmpxchg_acq(ptr,o,n) ia64_cmpxchg(acq,ptr,o,n,sizeof(*ptr))
    3.41 -#define cmpxchg_rel(ptr,o,n) ia64_cmpxchg(rel,ptr,o,n,sizeof(*ptr))
    3.42 -
    3.43 -/*
    3.44 - * Register Names for getreg() and setreg().
    3.45 - *
    3.46 - * The "magic" numbers happen to match the values used by the Intel compiler's
    3.47 - * getreg()/setreg() intrinsics.
    3.48 - */
    3.49 -
    3.50 -/* Special Registers */
    3.51 -
    3.52 -#define _IA64_REG_IP		1016	/* getreg only */
    3.53 -#define _IA64_REG_PSR		1019
    3.54 -#define _IA64_REG_PSR_L		1019
    3.55 -
    3.56 -/* General Integer Registers */
    3.57 -
    3.58 -#define _IA64_REG_GP		1025	/* R1 */
    3.59 -#define _IA64_REG_R8		1032	/* R8 */
    3.60 -#define _IA64_REG_R9		1033	/* R9 */
    3.61 -#define _IA64_REG_SP		1036	/* R12 */
    3.62 -#define _IA64_REG_TP		1037	/* R13 */
    3.63 -
    3.64 -/* Application Registers */
    3.65 -
    3.66 -#define _IA64_REG_AR_KR0	3072
    3.67 -#define _IA64_REG_AR_KR1	3073
    3.68 -#define _IA64_REG_AR_KR2	3074
    3.69 -#define _IA64_REG_AR_KR3	3075
    3.70 -#define _IA64_REG_AR_KR4	3076
    3.71 -#define _IA64_REG_AR_KR5	3077
    3.72 -#define _IA64_REG_AR_KR6	3078
    3.73 -#define _IA64_REG_AR_KR7	3079
    3.74 -#define _IA64_REG_AR_RSC	3088
    3.75 -#define _IA64_REG_AR_BSP	3089
    3.76 -#define _IA64_REG_AR_BSPSTORE	3090
    3.77 -#define _IA64_REG_AR_RNAT	3091
    3.78 -#define _IA64_REG_AR_FCR	3093
    3.79 -#define _IA64_REG_AR_EFLAG	3096
    3.80 -#define _IA64_REG_AR_CSD	3097
    3.81 -#define _IA64_REG_AR_SSD	3098
    3.82 -#define _IA64_REG_AR_CFLAG	3099
    3.83 -#define _IA64_REG_AR_FSR	3100
    3.84 -#define _IA64_REG_AR_FIR	3101
    3.85 -#define _IA64_REG_AR_FDR	3102
    3.86 -#define _IA64_REG_AR_CCV	3104
    3.87 -#define _IA64_REG_AR_UNAT	3108
    3.88 -#define _IA64_REG_AR_FPSR	3112
    3.89 -#define _IA64_REG_AR_ITC	3116
    3.90 -#define _IA64_REG_AR_PFS	3136
    3.91 -#define _IA64_REG_AR_LC		3137
    3.92 -#define _IA64_REG_AR_EC		3138
    3.93 -
    3.94 -/* Control Registers */
    3.95 -
    3.96 -#define _IA64_REG_CR_DCR	4096
    3.97 -#define _IA64_REG_CR_ITM	4097
    3.98 -#define _IA64_REG_CR_IVA	4098
    3.99 -#define _IA64_REG_CR_PTA	4104
   3.100 -#define _IA64_REG_CR_IPSR	4112
   3.101 -#define _IA64_REG_CR_ISR	4113
   3.102 -#define _IA64_REG_CR_IIP	4115
   3.103 -#define _IA64_REG_CR_IFA	4116
   3.104 -#define _IA64_REG_CR_ITIR	4117
   3.105 -#define _IA64_REG_CR_IIPA	4118
   3.106 -#define _IA64_REG_CR_IFS	4119
   3.107 -#define _IA64_REG_CR_IIM	4120
   3.108 -#define _IA64_REG_CR_IHA	4121
   3.109 -#define _IA64_REG_CR_LID	4160
   3.110 -#define _IA64_REG_CR_IVR	4161	/* getreg only */
   3.111 -#define _IA64_REG_CR_TPR	4162
   3.112 -#define _IA64_REG_CR_EOI	4163
   3.113 -#define _IA64_REG_CR_IRR0	4164	/* getreg only */
   3.114 -#define _IA64_REG_CR_IRR1	4165	/* getreg only */
   3.115 -#define _IA64_REG_CR_IRR2	4166	/* getreg only */
   3.116 -#define _IA64_REG_CR_IRR3	4167	/* getreg only */
   3.117 -#define _IA64_REG_CR_ITV	4168
   3.118 -#define _IA64_REG_CR_PMV	4169
   3.119 -#define _IA64_REG_CR_CMCV	4170
   3.120 -#define _IA64_REG_CR_LRR0	4176
   3.121 -#define _IA64_REG_CR_LRR1	4177
   3.122 -
   3.123 -/* Indirect Registers for getindreg() and setindreg() */
   3.124 -
   3.125 -#define _IA64_REG_INDR_CPUID	9000	/* getindreg only */
   3.126 -#define _IA64_REG_INDR_DBR	9001
   3.127 -#define _IA64_REG_INDR_IBR	9002
   3.128 -#define _IA64_REG_INDR_PKR	9003
   3.129 -#define _IA64_REG_INDR_PMC	9004
   3.130 -#define _IA64_REG_INDR_PMD	9005
   3.131 -#define _IA64_REG_INDR_RR	9006
   3.132 -
   3.133 -#ifdef __INTEL_COMPILER
   3.134 -void  __fc(uint64_t *addr);
   3.135 -void  __synci(void);
   3.136 -void __isrlz(void);
   3.137 -void __dsrlz(void);
   3.138 -uint64_t __getReg(const int whichReg);
   3.139 -uint64_t _InterlockedCompareExchange8_rel(volatile uint8_t *dest, uint64_t xchg, uint64_t comp);
   3.140 -uint64_t _InterlockedCompareExchange8_acq(volatile uint8_t *dest, uint64_t xchg, uint64_t comp);
   3.141 -uint64_t _InterlockedCompareExchange16_rel(volatile uint16_t *dest, uint64_t xchg, uint64_t comp);
   3.142 -uint64_t _InterlockedCompareExchange16_acq(volatile uint16_t *dest, uint64_t xchg, uint64_t comp);
   3.143 -uint64_t _InterlockedCompareExchange_rel(volatile uint32_t *dest, uint64_t xchg, uint64_t comp);
   3.144 -uint64_t _InterlockedCompareExchange_acq(volatile uint32_t *dest, uint64_t xchg, uint64_t comp);
   3.145 -uint64_t _InterlockedCompareExchange64_rel(volatile uint64_t *dest, uint64_t xchg, uint64_t comp);
   3.146 -u64_t _InterlockedCompareExchange64_acq(volatile uint64_t *dest, uint64_t xchg, uint64_t comp);
   3.147 -
   3.148 -#define ia64_cmpxchg1_rel	_InterlockedCompareExchange8_rel
   3.149 -#define ia64_cmpxchg1_acq	_InterlockedCompareExchange8_acq
   3.150 -#define ia64_cmpxchg2_rel	_InterlockedCompareExchange16_rel
   3.151 -#define ia64_cmpxchg2_acq	_InterlockedCompareExchange16_acq
   3.152 -#define ia64_cmpxchg4_rel	_InterlockedCompareExchange_rel
   3.153 -#define ia64_cmpxchg4_acq	_InterlockedCompareExchange_acq
   3.154 -#define ia64_cmpxchg8_rel	_InterlockedCompareExchange64_rel
   3.155 -#define ia64_cmpxchg8_acq	_InterlockedCompareExchange64_acq
   3.156 -
   3.157 -#define ia64_srlz_d		__dsrlz
   3.158 -#define ia64_srlz_i		__isrlz
   3.159 -#define __ia64_fc 		__fc
   3.160 -#define ia64_sync_i		__synci
   3.161 -#define __ia64_getreg		__getReg
   3.162 -#else /* __INTEL_COMPILER */
   3.163 -#define ia64_cmpxchg1_acq(ptr, new, old)						\
   3.164 -({											\
   3.165 -	uint64_t ia64_intri_res;							\
   3.166 -	asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));					\
   3.167 -	asm volatile ("cmpxchg1.acq %0=[%1],%2,ar.ccv":					\
   3.168 -			      "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory");	\
   3.169 -	ia64_intri_res;									\
   3.170 -})
   3.171 -
   3.172 -#define ia64_cmpxchg1_rel(ptr, new, old)						\
   3.173 -({											\
   3.174 -	uint64_t ia64_intri_res;							\
   3.175 -	asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));					\
   3.176 -	asm volatile ("cmpxchg1.rel %0=[%1],%2,ar.ccv":					\
   3.177 -			      "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory");	\
   3.178 -	ia64_intri_res;									\
   3.179 -})
   3.180 -
   3.181 -#define ia64_cmpxchg2_acq(ptr, new, old)						\
   3.182 -({											\
   3.183 -	uint64_t ia64_intri_res;							\
   3.184 -	asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));					\
   3.185 -	asm volatile ("cmpxchg2.acq %0=[%1],%2,ar.ccv":					\
   3.186 -			      "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory");	\
   3.187 -	ia64_intri_res;									\
   3.188 -})
   3.189 -
   3.190 -#define ia64_cmpxchg2_rel(ptr, new, old)						\
   3.191 -({											\
   3.192 -	uint64_t ia64_intri_res;							\
   3.193 -	asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));					\
   3.194 -											\
   3.195 -	asm volatile ("cmpxchg2.rel %0=[%1],%2,ar.ccv":					\
   3.196 -			      "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory");	\
   3.197 -	ia64_intri_res;									\
   3.198 -})
   3.199 -
   3.200 -#define ia64_cmpxchg4_acq(ptr, new, old)						\
   3.201 -({											\
   3.202 -	uint64_t ia64_intri_res;							\
   3.203 -	asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));					\
   3.204 -	asm volatile ("cmpxchg4.acq %0=[%1],%2,ar.ccv":					\
   3.205 -			      "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory");	\
   3.206 -	ia64_intri_res;									\
   3.207 -})
   3.208 -
   3.209 -#define ia64_cmpxchg4_rel(ptr, new, old)						\
   3.210 -({											\
   3.211 -	uint64_t ia64_intri_res;							\
   3.212 -	asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));					\
   3.213 -	asm volatile ("cmpxchg4.rel %0=[%1],%2,ar.ccv":					\
   3.214 -			      "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory");	\
   3.215 -	ia64_intri_res;									\
   3.216 -})
   3.217 -
   3.218 -#define ia64_cmpxchg8_acq(ptr, new, old)						\
   3.219 -({											\
   3.220 -	uint64_t ia64_intri_res;							\
   3.221 -	asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));					\
   3.222 -	asm volatile ("cmpxchg8.acq %0=[%1],%2,ar.ccv":					\
   3.223 -			      "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory");	\
   3.224 -	ia64_intri_res;									\
   3.225 -})
   3.226 -
   3.227 -#define ia64_cmpxchg8_rel(ptr, new, old)						\
   3.228 -({											\
   3.229 -	uint64_t ia64_intri_res;							\
   3.230 -	asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));					\
   3.231 -											\
   3.232 -	asm volatile ("cmpxchg8.rel %0=[%1],%2,ar.ccv":					\
   3.233 -			      "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory");	\
   3.234 -	ia64_intri_res;									\
   3.235 -})
   3.236 -
   3.237 -#define ia64_srlz_i()	asm volatile (";; srlz.i ;;" ::: "memory")
   3.238 -#define ia64_srlz_d()	asm volatile (";; srlz.d" ::: "memory");
   3.239 -#define __ia64_fc(addr)	asm volatile ("fc %0" :: "r"(addr) : "memory")
   3.240 -#define ia64_sync_i()	asm volatile (";; sync.i" ::: "memory")
   3.241 -
   3.242 -register unsigned long ia64_r13 asm ("r13") __attribute_used__;
   3.243 -#define __ia64_getreg(regnum)							\
   3.244 -({										\
   3.245 -	uint64_t ia64_intri_res;							\
   3.246 -										\
   3.247 -	switch (regnum) {							\
   3.248 -	case _IA64_REG_GP:							\
   3.249 -		asm volatile ("mov %0=gp" : "=r"(ia64_intri_res));		\
   3.250 -		break;								\
   3.251 -	case _IA64_REG_IP:							\
   3.252 -		asm volatile ("mov %0=ip" : "=r"(ia64_intri_res));		\
   3.253 -		break;								\
   3.254 -	case _IA64_REG_PSR:							\
   3.255 -		asm volatile ("mov %0=psr" : "=r"(ia64_intri_res));		\
   3.256 -		break;								\
   3.257 -	case _IA64_REG_TP:	/* for current() */				\
   3.258 -		ia64_intri_res = ia64_r13;					\
   3.259 -		break;								\
   3.260 -	case _IA64_REG_AR_KR0 ... _IA64_REG_AR_EC:				\
   3.261 -		asm volatile ("mov %0=ar%1" : "=r" (ia64_intri_res)		\
   3.262 -				      : "i"(regnum - _IA64_REG_AR_KR0));	\
   3.263 -		break;								\
   3.264 -	case _IA64_REG_CR_DCR ... _IA64_REG_CR_LRR1:				\
   3.265 -		asm volatile ("mov %0=cr%1" : "=r" (ia64_intri_res)		\
   3.266 -				      : "i" (regnum - _IA64_REG_CR_DCR));	\
   3.267 -		break;								\
   3.268 -	case _IA64_REG_SP:							\
   3.269 -		asm volatile ("mov %0=sp" : "=r" (ia64_intri_res));		\
   3.270 -		break;								\
   3.271 -	default:								\
   3.272 -		ia64_bad_param_for_getreg();					\
   3.273 -		break;								\
   3.274 -	}									\
   3.275 -	ia64_intri_res;								\
   3.276 -})
   3.277 -
   3.278 -#endif /* __INTEL_COMPILER */
   3.279 -#endif /* IA64_INTRINSIC_H */