ia64/xen-unstable

changeset 1153:7869b7caa363

bitkeeper revision 1.773 (404f1c2crOagpEppZ6uF3JohTX-G5g)

xen.patchF
author kaf24@scramble.cl.cam.ac.uk[kaf24]
date Wed Mar 10 13:46:20 2004 +0000 (2004-03-10)
parents f54cd472c1af
children ffcfa91cf6bc
files xen/arch/i386/Rules.mk xen/arch/i386/entry.S xen/arch/i386/process.c xen/arch/i386/time.c xen/arch/x86_64/Rules.mk xen/common/Makefile xen/common/memory.c xen/include/asm-i386/config.h xen/include/asm-x86_64/apic.h xen/include/asm-x86_64/apicdef.h xen/include/asm-x86_64/atomic.h xen/include/asm-x86_64/bitops.h xen/include/asm-x86_64/byteorder.h xen/include/asm-x86_64/cache.h xen/include/asm-x86_64/config.h xen/include/asm-x86_64/cpufeature.h xen/include/asm-x86_64/current.h xen/include/asm-x86_64/debugreg.h xen/include/asm-x86_64/delay.h xen/include/asm-x86_64/desc.h xen/include/asm-x86_64/domain_page.h xen/include/asm-x86_64/fixmap.h xen/include/asm-x86_64/hdreg.h xen/include/asm-x86_64/ide.h xen/include/asm-x86_64/io.h xen/include/asm-x86_64/io_apic.h xen/include/asm-x86_64/ioctl.h xen/include/asm-x86_64/irq.h xen/include/asm-x86_64/mpspec.h xen/include/asm-x86_64/msr.h xen/include/asm-x86_64/page.h xen/include/asm-x86_64/param.h xen/include/asm-x86_64/pci.h xen/include/asm-x86_64/pgalloc.h xen/include/asm-x86_64/processor.h xen/include/asm-x86_64/ptrace.h xen/include/asm-x86_64/rwlock.h xen/include/asm-x86_64/scatterlist.h xen/include/asm-x86_64/smp.h xen/include/asm-x86_64/spinlock.h xen/include/asm-x86_64/string.h xen/include/asm-x86_64/system.h xen/include/asm-x86_64/timex.h xen/include/asm-x86_64/types.h xen/include/asm-x86_64/uaccess.h xen/include/asm-x86_64/unaligned.h xen/include/hypervisor-ifs/dom0_ops.h xen/include/hypervisor-ifs/hypervisor-if.h xen/include/hypervisor-ifs/if-i386/hypervisor-if-arch.h xen/include/hypervisor-ifs/if-x86_64/hypervisor-if-arch.h xen/include/xeno/sched.h
line diff
     1.1 --- a/xen/arch/i386/Rules.mk	Wed Mar 10 13:44:42 2004 +0000
     1.2 +++ b/xen/arch/i386/Rules.mk	Wed Mar 10 13:46:20 2004 +0000
     1.3 @@ -11,7 +11,8 @@ CFLAGS  := -nostdinc -fno-builtin -fno-c
     1.4  CFLAGS  += -iwithprefix include -O3 -Wall -DMONITOR_BASE=$(MONITOR_BASE)
     1.5  CFLAGS  += -fomit-frame-pointer -I$(BASEDIR)/include -D__KERNEL__ -DNDEBUG
     1.6  #CFLAGS  += -fomit-frame-pointer -I$(BASEDIR)/include -D__KERNEL__
     1.7 -CFLAGS  += -Wno-pointer-arith -Wredundant-decls
     1.8 -LDFLAGS := -T xeno.lds -N
     1.9 +CFLAGS  += -Wno-pointer-arith -Wredundant-decls -m32
    1.10 +LDARCHFLAGS := --oformat elf32-i386 
    1.11 +LDFLAGS := -T xeno.lds -N 
    1.12  
    1.13  
     2.1 --- a/xen/arch/i386/entry.S	Wed Mar 10 13:44:42 2004 +0000
     2.2 +++ b/xen/arch/i386/entry.S	Wed Mar 10 13:46:20 2004 +0000
     2.3 @@ -202,7 +202,7 @@ multicall_fault6:
     2.4  multicall_return_from_call:
     2.5          addl  $20,%esp
     2.6          popl  %ecx
     2.7 -        addl  $BYTES_PER_MULTICALL_ENTRY,%ebx
     2.8 +        addl  $(ARGS_PER_MULTICALL_ENTRY*4),%ebx
     2.9          loop  multicall_loop
    2.10          popl  %ebx
    2.11          xorl  %eax,%eax
     3.1 --- a/xen/arch/i386/process.c	Wed Mar 10 13:44:42 2004 +0000
     3.2 +++ b/xen/arch/i386/process.c	Wed Mar 10 13:46:20 2004 +0000
     3.3 @@ -28,6 +28,7 @@
     3.4  #include <asm/desc.h>
     3.5  #include <asm/i387.h>
     3.6  #include <asm/mpspec.h>
     3.7 +#include <asm/ldt.h>
     3.8  
     3.9  #include <xeno/irq.h>
    3.10  #include <xeno/event.h>
     4.1 --- a/xen/arch/i386/time.c	Wed Mar 10 13:44:42 2004 +0000
     4.2 +++ b/xen/arch/i386/time.c	Wed Mar 10 13:46:20 2004 +0000
     4.3 @@ -282,7 +282,7 @@ void update_dom_time(shared_info_t *si)
     4.4  
     4.5      /* NB. These two values don't actually ever change. */
     4.6      si->cpu_freq       = cpu_freq;
     4.7 -    si->rdtsc_bitshift = rdtsc_bitshift;
     4.8 +    si->arch.rdtsc_bitshift = rdtsc_bitshift;
     4.9  
    4.10      si->system_time    = stime_irq;
    4.11      si->tsc_timestamp  = tsc_irq;
     5.1 --- a/xen/arch/x86_64/Rules.mk	Wed Mar 10 13:44:42 2004 +0000
     5.2 +++ b/xen/arch/x86_64/Rules.mk	Wed Mar 10 13:46:20 2004 +0000
     5.3 @@ -11,7 +11,8 @@ CFLAGS  := -nostdinc -fno-builtin -fno-c
     5.4  CFLAGS  += -iwithprefix include -O3 -Wall -DMONITOR_BASE=$(MONITOR_BASE)
     5.5  CFLAGS  += -fomit-frame-pointer -I$(BASEDIR)/include -D__KERNEL__ -DNDEBUG
     5.6  #CFLAGS  += -fomit-frame-pointer -I$(BASEDIR)/include -D__KERNEL__
     5.7 -CFLAGS  += -Wno-pointer-arith -Wredundant-decls
     5.8 -LDFLAGS := -T xeno.lds -N
     5.9 +CFLAGS  += -Wno-pointer-arith -Wredundant-decls -m64
    5.10 +LDARCHFLAGS := 
    5.11 +LDFLAGS := -T xeno.lds -N 
    5.12  
    5.13  
     6.1 --- a/xen/common/Makefile	Wed Mar 10 13:44:42 2004 +0000
     6.2 +++ b/xen/common/Makefile	Wed Mar 10 13:46:20 2004 +0000
     6.3 @@ -2,7 +2,7 @@
     6.4  include $(BASEDIR)/Rules.mk
     6.5  
     6.6  default: $(OBJS)
     6.7 -	$(LD) -r -o common.o $(OBJS)
     6.8 +	$(LD) $(LDARCHFLAGS) -r -o common.o $(OBJS)
     6.9  
    6.10  clean:
    6.11  	rm -f *.o *~ core
     7.1 --- a/xen/common/memory.c	Wed Mar 10 13:44:42 2004 +0000
     7.2 +++ b/xen/common/memory.c	Wed Mar 10 13:46:20 2004 +0000
     7.3 @@ -138,6 +138,7 @@
     7.4  #include <asm/io.h>
     7.5  #include <asm/uaccess.h>
     7.6  #include <asm/domain_page.h>
     7.7 +#include <asm/ldt.h>
     7.8  
     7.9  #ifndef NDEBUG
    7.10  #define MEM_LOG(_f, _a...)                             \
     8.1 --- a/xen/include/asm-i386/config.h	Wed Mar 10 13:44:42 2004 +0000
     8.2 +++ b/xen/include/asm-i386/config.h	Wed Mar 10 13:46:20 2004 +0000
     8.3 @@ -4,8 +4,8 @@
     8.4   * A Linux-style configuration list.
     8.5   */
     8.6  
     8.7 -#ifndef __XENO_CONFIG_H__
     8.8 -#define __XENO_CONFIG_H__
     8.9 +#ifndef __XENO_I386_CONFIG_H__
    8.10 +#define __XENO_I386_CONFIG_H__
    8.11  
    8.12  #define CONFIG_X86 1
    8.13  
    8.14 @@ -167,4 +167,4 @@ extern unsigned int opt_ser_baud;
    8.15  
    8.16  #endif /* __ASSEMBLY__ */
    8.17  
    8.18 -#endif /* __XENO_CONFIG_H__ */
    8.19 +#endif /* __XENO_I386_CONFIG_H__ */
     9.1 --- a/xen/include/asm-x86_64/apic.h	Wed Mar 10 13:44:42 2004 +0000
     9.2 +++ b/xen/include/asm-x86_64/apic.h	Wed Mar 10 13:46:20 2004 +0000
     9.3 @@ -20,19 +20,20 @@
     9.4   * Basic functions accessing APICs.
     9.5   */
     9.6  
     9.7 -static __inline void apic_write(unsigned long reg, unsigned long v)
     9.8 +static __inline void apic_write(unsigned long reg, unsigned int v)
     9.9  {
    9.10 -	*((volatile unsigned long *)(APIC_BASE+reg)) = v;
    9.11 +	*((volatile unsigned int *)(APIC_BASE+reg)) = v;
    9.12 +	barrier();
    9.13  }
    9.14  
    9.15 -static __inline void apic_write_atomic(unsigned long reg, unsigned long v)
    9.16 +static __inline void apic_write_atomic(unsigned long reg, unsigned int v)
    9.17  {
    9.18 -	xchg((volatile unsigned long *)(APIC_BASE+reg), v);
    9.19 +	xchg((volatile unsigned int *)(APIC_BASE+reg), v);
    9.20  }
    9.21  
    9.22 -static __inline unsigned long apic_read(unsigned long reg)
    9.23 +static __inline unsigned int apic_read(unsigned long reg)
    9.24  {
    9.25 -	return *((volatile unsigned long *)(APIC_BASE+reg));
    9.26 +	return *((volatile unsigned int *)(APIC_BASE+reg));
    9.27  }
    9.28  
    9.29  static __inline__ void apic_wait_icr_idle(void)
    9.30 @@ -95,4 +96,7 @@ extern unsigned int nmi_watchdog;
    9.31  
    9.32  #endif /* CONFIG_X86_LOCAL_APIC */
    9.33  
    9.34 +#define clustered_apic_mode 0
    9.35 +#define esr_disable 0
    9.36 +
    9.37  #endif /* __ASM_APIC_H */
    10.1 --- a/xen/include/asm-x86_64/apicdef.h	Wed Mar 10 13:44:42 2004 +0000
    10.2 +++ b/xen/include/asm-x86_64/apicdef.h	Wed Mar 10 13:46:20 2004 +0000
    10.3 @@ -32,8 +32,6 @@
    10.4  #define			SET_APIC_LOGICAL_ID(x)	(((x)<<24))
    10.5  #define			APIC_ALL_CPUS		0xFF
    10.6  #define		APIC_DFR	0xE0
    10.7 -#define			APIC_DFR_CLUSTER	0x0FFFFFFFul	/* Clustered */
    10.8 -#define			APIC_DFR_FLAT		0xFFFFFFFFul	/* Flat mode */
    10.9  #define		APIC_SPIV	0xF0
   10.10  #define			APIC_SPIV_FOCUS_DISABLED	(1<<9)
   10.11  #define			APIC_SPIV_APIC_ENABLED		(1<<8)
   10.12 @@ -59,7 +57,6 @@
   10.13  #define			APIC_INT_LEVELTRIG	0x08000
   10.14  #define			APIC_INT_ASSERT		0x04000
   10.15  #define			APIC_ICR_BUSY		0x01000
   10.16 -#define			APIC_DEST_PHYSICAL	0x00000
   10.17  #define			APIC_DEST_LOGICAL	0x00800
   10.18  #define			APIC_DM_FIXED		0x00000
   10.19  #define			APIC_DM_LOWEST		0x00100
   10.20 @@ -110,19 +107,7 @@
   10.21  
   10.22  #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
   10.23  
   10.24 -#ifdef CONFIG_X86_CLUSTERED_APIC
   10.25 -#define MAX_IO_APICS 32
   10.26 -#else
   10.27 -#define MAX_IO_APICS 8
   10.28 -#endif
   10.29 -
   10.30 -
   10.31 -/*
   10.32 - * The broadcast ID is 0xF for old APICs and 0xFF for xAPICs.  SAPICs
   10.33 - * don't broadcast (yet?), but if they did, they might use 0xFFFF.
   10.34 - */
   10.35 -#define APIC_BROADCAST_ID_XAPIC (0xFF)
   10.36 -#define APIC_BROADCAST_ID_APIC  (0x0F)
   10.37 +#define MAX_IO_APICS 16
   10.38  
   10.39  /*
   10.40   * the local APIC register structure, memory mapped. Not terribly well
    11.1 --- a/xen/include/asm-x86_64/atomic.h	Wed Mar 10 13:44:42 2004 +0000
    11.2 +++ b/xen/include/asm-x86_64/atomic.h	Wed Mar 10 13:46:20 2004 +0000
    11.3 @@ -186,6 +186,16 @@ static __inline__ int atomic_add_negativ
    11.4  	return c;
    11.5  }
    11.6  
    11.7 +
    11.8 +/* These are x86-specific, used by some header files */
    11.9 +#define atomic_clear_mask(mask, addr) \
   11.10 +__asm__ __volatile__(LOCK "andl %0,%1" \
   11.11 +: : "r" (~(mask)),"m" (*addr) : "memory")
   11.12 +
   11.13 +#define atomic_set_mask(mask, addr) \
   11.14 +__asm__ __volatile__(LOCK "orl %0,%1" \
   11.15 +: : "r" ((unsigned)mask),"m" (*addr) : "memory")
   11.16 +
   11.17  /* Atomic operations are already serializing on x86 */
   11.18  #define smp_mb__before_atomic_dec()	barrier()
   11.19  #define smp_mb__after_atomic_dec()	barrier()
    12.1 --- a/xen/include/asm-x86_64/bitops.h	Wed Mar 10 13:44:42 2004 +0000
    12.2 +++ b/xen/include/asm-x86_64/bitops.h	Wed Mar 10 13:46:20 2004 +0000
    12.3 @@ -1,5 +1,5 @@
    12.4 -#ifndef _I386_BITOPS_H
    12.5 -#define _I386_BITOPS_H
    12.6 +#ifndef _X86_64_BITOPS_H
    12.7 +#define _X86_64_BITOPS_H
    12.8  
    12.9  /*
   12.10   * Copyright 1992, Linus Torvalds.
   12.11 @@ -33,12 +33,12 @@
   12.12   * Note that @nr may be almost arbitrarily large; this function is not
   12.13   * restricted to acting on a single-word quantity.
   12.14   */
   12.15 -static __inline__ void set_bit(int nr, volatile void * addr)
   12.16 +static __inline__ void set_bit(long nr, volatile void * addr)
   12.17  {
   12.18  	__asm__ __volatile__( LOCK_PREFIX
   12.19 -		"btsl %1,%0"
   12.20 +		"btsq %1,%0"
   12.21  		:"=m" (ADDR)
   12.22 -		:"Ir" (nr));
   12.23 +		:"dIr" (nr));
   12.24  }
   12.25  
   12.26  /**
   12.27 @@ -50,12 +50,12 @@ static __inline__ void set_bit(int nr, v
   12.28   * If it's called on the same region of memory simultaneously, the effect
   12.29   * may be that only one operation succeeds.
   12.30   */
   12.31 -static __inline__ void __set_bit(int nr, volatile void * addr)
   12.32 +static __inline__ void __set_bit(long nr, volatile void * addr)
   12.33  {
   12.34  	__asm__(
   12.35 -		"btsl %1,%0"
   12.36 +		"btsq %1,%0"
   12.37  		:"=m" (ADDR)
   12.38 -		:"Ir" (nr));
   12.39 +		:"dIr" (nr));
   12.40  }
   12.41  
   12.42  /**
   12.43 @@ -68,12 +68,12 @@ static __inline__ void __set_bit(int nr,
   12.44   * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
   12.45   * in order to ensure changes are visible on other processors.
   12.46   */
   12.47 -static __inline__ void clear_bit(int nr, volatile void * addr)
   12.48 +static __inline__ void clear_bit(long nr, volatile void * addr)
   12.49  {
   12.50  	__asm__ __volatile__( LOCK_PREFIX
   12.51 -		"btrl %1,%0"
   12.52 +		"btrq %1,%0"
   12.53  		:"=m" (ADDR)
   12.54 -		:"Ir" (nr));
   12.55 +		:"dIr" (nr));
   12.56  }
   12.57  #define smp_mb__before_clear_bit()	barrier()
   12.58  #define smp_mb__after_clear_bit()	barrier()
   12.59 @@ -87,12 +87,12 @@ static __inline__ void clear_bit(int nr,
   12.60   * If it's called on the same region of memory simultaneously, the effect
   12.61   * may be that only one operation succeeds.
   12.62   */
   12.63 -static __inline__ void __change_bit(int nr, volatile void * addr)
   12.64 +static __inline__ void __change_bit(long nr, volatile void * addr)
   12.65  {
   12.66  	__asm__ __volatile__(
   12.67 -		"btcl %1,%0"
   12.68 +		"btcq %1,%0"
   12.69  		:"=m" (ADDR)
   12.70 -		:"Ir" (nr));
   12.71 +		:"dIr" (nr));
   12.72  }
   12.73  
   12.74  /**
   12.75 @@ -104,12 +104,12 @@ static __inline__ void __change_bit(int 
   12.76   * Note that @nr may be almost arbitrarily large; this function is not
   12.77   * restricted to acting on a single-word quantity.
   12.78   */
   12.79 -static __inline__ void change_bit(int nr, volatile void * addr)
   12.80 +static __inline__ void change_bit(long nr, volatile void * addr)
   12.81  {
   12.82  	__asm__ __volatile__( LOCK_PREFIX
   12.83 -		"btcl %1,%0"
   12.84 +		"btcq %1,%0"
   12.85  		:"=m" (ADDR)
   12.86 -		:"Ir" (nr));
   12.87 +		:"dIr" (nr));
   12.88  }
   12.89  
   12.90  /**
   12.91 @@ -120,14 +120,14 @@ static __inline__ void change_bit(int nr
   12.92   * This operation is atomic and cannot be reordered.  
   12.93   * It also implies a memory barrier.
   12.94   */
   12.95 -static __inline__ int test_and_set_bit(int nr, volatile void * addr)
   12.96 +static __inline__ int test_and_set_bit(long nr, volatile void * addr)
   12.97  {
   12.98 -	int oldbit;
   12.99 +        long oldbit;
  12.100  
  12.101  	__asm__ __volatile__( LOCK_PREFIX
  12.102 -		"btsl %2,%1\n\tsbbl %0,%0"
  12.103 +		"btsq %2,%1\n\tsbbq %0,%0"
  12.104  		:"=r" (oldbit),"=m" (ADDR)
  12.105 -		:"Ir" (nr) : "memory");
  12.106 +		:"dIr" (nr) : "memory");
  12.107  	return oldbit;
  12.108  }
  12.109  
  12.110 @@ -140,14 +140,14 @@ static __inline__ int test_and_set_bit(i
  12.111   * If two examples of this operation race, one can appear to succeed
  12.112   * but actually fail.  You must protect multiple accesses with a lock.
  12.113   */
  12.114 -static __inline__ int __test_and_set_bit(int nr, volatile void * addr)
  12.115 +static __inline__ int __test_and_set_bit(long nr, volatile void * addr)
  12.116  {
  12.117 -	int oldbit;
  12.118 +	long oldbit;
  12.119  
  12.120  	__asm__(
  12.121 -		"btsl %2,%1\n\tsbbl %0,%0"
  12.122 +		"btsq %2,%1\n\tsbbq %0,%0"
  12.123  		:"=r" (oldbit),"=m" (ADDR)
  12.124 -		:"Ir" (nr));
  12.125 +		:"dIr" (nr));
  12.126  	return oldbit;
  12.127  }
  12.128  
  12.129 @@ -159,14 +159,14 @@ static __inline__ int __test_and_set_bit
  12.130   * This operation is atomic and cannot be reordered.  
  12.131   * It also implies a memory barrier.
  12.132   */
  12.133 -static __inline__ int test_and_clear_bit(int nr, volatile void * addr)
  12.134 +static __inline__ int test_and_clear_bit(long nr, volatile void * addr)
  12.135  {
  12.136 -	int oldbit;
  12.137 +	long oldbit;
  12.138  
  12.139  	__asm__ __volatile__( LOCK_PREFIX
  12.140 -		"btrl %2,%1\n\tsbbl %0,%0"
  12.141 +		"btrq %2,%1\n\tsbbq %0,%0"
  12.142  		:"=r" (oldbit),"=m" (ADDR)
  12.143 -		:"Ir" (nr) : "memory");
  12.144 +		:"dIr" (nr) : "memory");
  12.145  	return oldbit;
  12.146  }
  12.147  
  12.148 @@ -179,26 +179,26 @@ static __inline__ int test_and_clear_bit
  12.149   * If two examples of this operation race, one can appear to succeed
  12.150   * but actually fail.  You must protect multiple accesses with a lock.
  12.151   */
  12.152 -static __inline__ int __test_and_clear_bit(int nr, volatile void * addr)
  12.153 +static __inline__ int __test_and_clear_bit(long nr, volatile void * addr)
  12.154  {
  12.155 -	int oldbit;
  12.156 +	long oldbit;
  12.157  
  12.158  	__asm__(
  12.159 -		"btrl %2,%1\n\tsbbl %0,%0"
  12.160 +		"btrq %2,%1\n\tsbbq %0,%0"
  12.161  		:"=r" (oldbit),"=m" (ADDR)
  12.162 -		:"Ir" (nr));
  12.163 +		:"dIr" (nr));
  12.164  	return oldbit;
  12.165  }
  12.166  
  12.167  /* WARNING: non atomic and it can be reordered! */
  12.168 -static __inline__ int __test_and_change_bit(int nr, volatile void * addr)
  12.169 +static __inline__ int __test_and_change_bit(long nr, volatile void * addr)
  12.170  {
  12.171 -	int oldbit;
  12.172 +	long oldbit;
  12.173  
  12.174  	__asm__ __volatile__(
  12.175 -		"btcl %2,%1\n\tsbbl %0,%0"
  12.176 +		"btcq %2,%1\n\tsbbq %0,%0"
  12.177  		:"=r" (oldbit),"=m" (ADDR)
  12.178 -		:"Ir" (nr) : "memory");
  12.179 +		:"dIr" (nr) : "memory");
  12.180  	return oldbit;
  12.181  }
  12.182  
  12.183 @@ -210,31 +210,39 @@ static __inline__ int __test_and_change_
  12.184   * This operation is atomic and cannot be reordered.  
  12.185   * It also implies a memory barrier.
  12.186   */
  12.187 -static __inline__ int test_and_change_bit(int nr, volatile void * addr)
  12.188 +static __inline__ int test_and_change_bit(long nr, volatile void * addr)
  12.189  {
  12.190 -	int oldbit;
  12.191 +	long oldbit;
  12.192  
  12.193  	__asm__ __volatile__( LOCK_PREFIX
  12.194 -		"btcl %2,%1\n\tsbbl %0,%0"
  12.195 +		"btcq %2,%1\n\tsbbq %0,%0"
  12.196  		:"=r" (oldbit),"=m" (ADDR)
  12.197 -		:"Ir" (nr) : "memory");
  12.198 +		:"dIr" (nr) : "memory");
  12.199  	return oldbit;
  12.200  }
  12.201  
  12.202 +#if 0 /* Fool kernel-doc since it doesn't do macros yet */
  12.203 +/**
  12.204 + * test_bit - Determine whether a bit is set
  12.205 + * @nr: bit number to test
  12.206 + * @addr: Address to start counting from
  12.207 + */
  12.208 +static int test_bit(int nr, const volatile void * addr);
  12.209 +#endif
  12.210  
  12.211 -static __inline__ int constant_test_bit(int nr, const volatile void * addr)
  12.212 +static __inline__ int constant_test_bit(long nr, const volatile void * addr)
  12.213  {
  12.214  	return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0;
  12.215  }
  12.216  
  12.217 -static __inline__ int variable_test_bit(int nr, volatile void * addr)
  12.218 +static __inline__ int variable_test_bit(long nr, volatile void * addr)
  12.219  {
  12.220 -	int oldbit;
  12.221 +	long oldbit;
  12.222  
  12.223  	__asm__ __volatile__(
  12.224 -		"btl %2,%1\n\tsbbl %0,%0"
  12.225 +		"btq %2,%1\n\tsbbq %0,%0"
  12.226  		:"=r" (oldbit)
  12.227 -		:"m" (ADDR),"Ir" (nr));
  12.228 +		:"m" (ADDR),"dIr" (nr));
  12.229  	return oldbit;
  12.230  }
  12.231  
  12.232 @@ -246,10 +254,10 @@ static __inline__ int variable_test_bit(
  12.233  /**
  12.234   * find_first_zero_bit - find the first zero bit in a memory region
  12.235   * @addr: The address to start the search at
  12.236 - * @size: The maximum size to search
  12.237 + * @size: The maximum bitnumber to search
  12.238   *
  12.239   * Returns the bit-number of the first zero bit, not the number of the byte
  12.240 - * containing a bit.
  12.241 + * containing a bit. -1 when none found.
  12.242   */
  12.243  static __inline__ int find_first_zero_bit(void * addr, unsigned size)
  12.244  {
  12.245 @@ -258,20 +266,19 @@ static __inline__ int find_first_zero_bi
  12.246  
  12.247  	if (!size)
  12.248  		return 0;
  12.249 -	/* This looks at memory. Mark it volatile to tell gcc not to move it around */
  12.250  	__asm__ __volatile__(
  12.251  		"movl $-1,%%eax\n\t"
  12.252  		"xorl %%edx,%%edx\n\t"
  12.253  		"repe; scasl\n\t"
  12.254  		"je 1f\n\t"
  12.255 -		"xorl -4(%%edi),%%eax\n\t"
  12.256 -		"subl $4,%%edi\n\t"
  12.257 +		"xorl -4(%%rdi),%%eax\n\t"
  12.258 +		"subq $4,%%rdi\n\t"
  12.259  		"bsfl %%eax,%%edx\n"
  12.260 -		"1:\tsubl %%ebx,%%edi\n\t"
  12.261 -		"shll $3,%%edi\n\t"
  12.262 -		"addl %%edi,%%edx"
  12.263 +		"1:\tsubq %%rbx,%%rdi\n\t"
  12.264 +		"shlq $3,%%rdi\n\t"
  12.265 +		"addq %%rdi,%%rdx"
  12.266  		:"=d" (res), "=&c" (d0), "=&D" (d1), "=&a" (d2)
  12.267 -		:"1" ((size + 31) >> 5), "2" (addr), "b" (addr));
  12.268 +		:"1" ((size + 31) >> 5), "2" (addr), "b" (addr) : "memory");
  12.269  	return res;
  12.270  }
  12.271  
  12.272 @@ -283,7 +290,7 @@ static __inline__ int find_first_zero_bi
  12.273   */
  12.274  static __inline__ int find_next_zero_bit (void * addr, int size, int offset)
  12.275  {
  12.276 -	unsigned long * p = ((unsigned long *) addr) + (offset >> 5);
  12.277 +	unsigned int * p = ((unsigned int *) addr) + (offset >> 5);
  12.278  	int set = 0, bit = offset & 31, res;
  12.279  	
  12.280  	if (bit) {
  12.281 @@ -304,10 +311,36 @@ static __inline__ int find_next_zero_bit
  12.282  	/*
  12.283  	 * No zero yet, search remaining full bytes for a zero
  12.284  	 */
  12.285 -	res = find_first_zero_bit (p, size - 32 * (p - (unsigned long *) addr));
  12.286 +	res = find_first_zero_bit (p, size - 32 * (p - (unsigned int *) addr));
  12.287  	return (offset + set + res);
  12.288  }
  12.289  
  12.290 +/* 
  12.291 + * Find string of zero bits in a bitmap. -1 when not found.
  12.292 + */ 
  12.293 +extern unsigned long 
  12.294 +find_next_zero_string(unsigned long *bitmap, long start, long nbits, int len);
  12.295 +
  12.296 +static inline void set_bit_string(unsigned long *bitmap, unsigned long i, 
  12.297 +				  int len) 
  12.298 +{ 
  12.299 +	unsigned long end = i + len; 
  12.300 +	while (i < end) {
  12.301 +		__set_bit(i, bitmap); 
  12.302 +		i++;
  12.303 +	}
  12.304 +} 
  12.305 +
  12.306 +static inline void clear_bit_string(unsigned long *bitmap, unsigned long i, 
  12.307 +				    int len) 
  12.308 +{ 
  12.309 +	unsigned long end = i + len; 
  12.310 +	while (i < end) {
  12.311 +		clear_bit(i, bitmap); 
  12.312 +		i++;
  12.313 +	}
  12.314 +} 
  12.315 +
  12.316  /**
  12.317   * ffz - find first zero in word.
  12.318   * @word: The word to search
  12.319 @@ -316,12 +349,13 @@ static __inline__ int find_next_zero_bit
  12.320   */
  12.321  static __inline__ unsigned long ffz(unsigned long word)
  12.322  {
  12.323 -	__asm__("bsfl %1,%0"
  12.324 +	__asm__("bsfq %1,%0"
  12.325  		:"=r" (word)
  12.326  		:"r" (~word));
  12.327  	return word;
  12.328  }
  12.329  
  12.330 +
  12.331  /**
  12.332   * ffs - find first bit set
  12.333   * @x: the word to search
  12.334 @@ -352,6 +386,8 @@ static __inline__ int ffs(int x)
  12.335  #define hweight16(x) generic_hweight16(x)
  12.336  #define hweight8(x) generic_hweight8(x)
  12.337  
  12.338 +
  12.339 +
  12.340  #define ext2_set_bit                 __test_and_set_bit
  12.341  #define ext2_clear_bit               __test_and_clear_bit
  12.342  #define ext2_test_bit                test_bit
  12.343 @@ -365,4 +401,5 @@ static __inline__ int ffs(int x)
  12.344  #define minix_test_bit(nr,addr) test_bit(nr,addr)
  12.345  #define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size)
  12.346  
  12.347 -#endif /* _I386_BITOPS_H */
  12.348 +
  12.349 +#endif /* _X86_64_BITOPS_H */
    13.1 --- a/xen/include/asm-x86_64/byteorder.h	Wed Mar 10 13:44:42 2004 +0000
    13.2 +++ b/xen/include/asm-x86_64/byteorder.h	Wed Mar 10 13:46:20 2004 +0000
    13.3 @@ -1,47 +1,32 @@
    13.4 -#ifndef _I386_BYTEORDER_H
    13.5 -#define _I386_BYTEORDER_H
    13.6 +#ifndef _X86_64_BYTEORDER_H
    13.7 +#define _X86_64_BYTEORDER_H
    13.8  
    13.9  #include <asm/types.h>
   13.10  
   13.11  #ifdef __GNUC__
   13.12  
   13.13 -/* For avoiding bswap on i386 */
   13.14 -#ifdef __KERNEL__
   13.15 -#include <linux/config.h>
   13.16 -#endif
   13.17 +static __inline__ __const__ __u64 ___arch__swab64(__u64 x)
   13.18 +{
   13.19 +	__asm__("bswapq %0" : "=r" (x) : "0" (x));
   13.20 +	return x;
   13.21 +}
   13.22  
   13.23  static __inline__ __const__ __u32 ___arch__swab32(__u32 x)
   13.24  {
   13.25 -#ifdef CONFIG_X86_BSWAP
   13.26 -	__asm__("bswap %0" : "=r" (x) : "0" (x));
   13.27 -#else
   13.28 -	__asm__("xchgb %b0,%h0\n\t"	/* swap lower bytes	*/
   13.29 -		"rorl $16,%0\n\t"	/* swap words		*/
   13.30 -		"xchgb %b0,%h0"		/* swap higher bytes	*/
   13.31 -		:"=q" (x)
   13.32 -		: "0" (x));
   13.33 -#endif
   13.34 +	__asm__("bswapl %0" : "=r" (x) : "0" (x));
   13.35  	return x;
   13.36  }
   13.37  
   13.38 -static __inline__ __const__ __u16 ___arch__swab16(__u16 x)
   13.39 -{
   13.40 -	__asm__("xchgb %b0,%h0"		/* swap bytes		*/ \
   13.41 -		: "=q" (x) \
   13.42 -		:  "0" (x)); \
   13.43 -		return x;
   13.44 -}
   13.45 +/* Do not define swab16.  Gcc is smart enought to recognize "C" version and
   13.46 +   convert it into rotation or exhange.  */
   13.47  
   13.48  #define __arch__swab32(x) ___arch__swab32(x)
   13.49 -#define __arch__swab16(x) ___arch__swab16(x)
   13.50 -
   13.51 -#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
   13.52 -#  define __BYTEORDER_HAS_U64__
   13.53 -#  define __SWAB_64_THRU_32__
   13.54 -#endif
   13.55 +#define __arch__swab64(x) ___arch__swab64(x)
   13.56  
   13.57  #endif /* __GNUC__ */
   13.58  
   13.59 +#define __BYTEORDER_HAS_U64__
   13.60 +
   13.61  #include <linux/byteorder/little_endian.h>
   13.62  
   13.63 -#endif /* _I386_BYTEORDER_H */
   13.64 +#endif /* _X86_64_BYTEORDER_H */
    14.1 --- a/xen/include/asm-x86_64/cache.h	Wed Mar 10 13:44:42 2004 +0000
    14.2 +++ b/xen/include/asm-x86_64/cache.h	Wed Mar 10 13:46:20 2004 +0000
    14.3 @@ -1,8 +1,8 @@
    14.4  /*
    14.5 - * include/asm-i386/cache.h
    14.6 + * include/asm-x8664/cache.h
    14.7   */
    14.8 -#ifndef __ARCH_I386_CACHE_H
    14.9 -#define __ARCH_I386_CACHE_H
   14.10 +#ifndef __ARCH_X8664_CACHE_H
   14.11 +#define __ARCH_X8664_CACHE_H
   14.12  
   14.13  #include <xeno/config.h>
   14.14  
    15.1 --- a/xen/include/asm-x86_64/config.h	Wed Mar 10 13:44:42 2004 +0000
    15.2 +++ b/xen/include/asm-x86_64/config.h	Wed Mar 10 13:46:20 2004 +0000
    15.3 @@ -4,8 +4,8 @@
    15.4   * A Linux-style configuration list.
    15.5   */
    15.6  
    15.7 -#ifndef __XENO_CONFIG_H__
    15.8 -#define __XENO_CONFIG_H__
    15.9 +#ifndef __XENO_X86_64_CONFIG_H__
   15.10 +#define __XENO_X86_64_CONFIG_H__
   15.11  
   15.12  #define CONFIG_X86 1
   15.13  
   15.14 @@ -53,9 +53,18 @@
   15.15  #define __cacheline_aligned __attribute__((__aligned__(SMP_CACHE_BYTES)))
   15.16  #define ____cacheline_aligned __cacheline_aligned
   15.17  
   15.18 -/*** Hypervisor owns top 64MB of virtual address space. ***/
   15.19 -#define HYPERVISOR_VIRT_START (0xFC000000UL)
   15.20 -
   15.21 +/*
   15.22 + * Virtual addresses beyond this are not modifiable by guest OSes. The
   15.23 + * machine->physical mapping table starts at this address, read-only.
   15.24 + */
   15.25 +#define HYPERVISOR_VIRT_START (0xFFFF800000000000ULL)
   15.26 +                                                                                                
   15.27 +/*
   15.28 + * Xen exists in the highest 2GB of address space for RIP-relative
   15.29 + * addressing
   15.30 + */
   15.31 +#define XEN_VIRT_START        (0xFFFFFFFF80000000ULL)
   15.32 +                                                                                                
   15.33  /*
   15.34   * First 4MB are mapped read-only for all. It's for the machine->physical
   15.35   * mapping table (MPT table). The following are virtual addresses.
   15.36 @@ -130,8 +139,12 @@
   15.37  
   15.38  #define barrier() __asm__ __volatile__("": : :"memory")
   15.39  
   15.40 -#define __HYPERVISOR_CS 0x0808
   15.41 -#define __HYPERVISOR_DS 0x0810
   15.42 +/*
   15.43 + * Hypervisor segment selectors
   15.44 + */
   15.45 +#define __HYPERVISOR_CS64 0x0810
   15.46 +#define __HYPERVISOR_CS32 0x0808
   15.47 +#define __HYPERVISOR_DS 0x0818
   15.48  
   15.49  #define NR_syscalls 256
   15.50  
   15.51 @@ -167,4 +180,4 @@ extern unsigned int opt_ser_baud;
   15.52  
   15.53  #endif /* __ASSEMBLY__ */
   15.54  
   15.55 -#endif /* __XENO_CONFIG_H__ */
   15.56 +#endif /* __XENO_X86_64_CONFIG_H__ */
    16.1 --- a/xen/include/asm-x86_64/cpufeature.h	Wed Mar 10 13:44:42 2004 +0000
    16.2 +++ b/xen/include/asm-x86_64/cpufeature.h	Wed Mar 10 13:46:20 2004 +0000
    16.3 @@ -4,8 +4,8 @@
    16.4   * Defines x86 CPU feature bits
    16.5   */
    16.6  
    16.7 -#ifndef __ASM_I386_CPUFEATURE_H
    16.8 -#define __ASM_I386_CPUFEATURE_H
    16.9 +#ifndef __ASM_X8664_CPUFEATURE_H
   16.10 +#define __ASM_X8664_CPUFEATURE_H
   16.11  
   16.12  /* Sample usage: CPU_FEATURE_P(cpu.x86_capability, FPU) */
   16.13  #define CPU_FEATURE_P(CAP, FEATURE) test_bit(CAP, X86_FEATURE_##FEATURE ##_BIT)
   16.14 @@ -40,7 +40,6 @@
   16.15  #define X86_FEATURE_XMM		(0*32+25) /* Streaming SIMD Extensions */
   16.16  #define X86_FEATURE_XMM2	(0*32+26) /* Streaming SIMD Extensions-2 */
   16.17  #define X86_FEATURE_SELFSNOOP	(0*32+27) /* CPU self snoop */
   16.18 -#define X86_FEATURE_HT		(0*32+28) /* Hyper-Threading */
   16.19  #define X86_FEATURE_ACC		(0*32+29) /* Automatic clock control */
   16.20  #define X86_FEATURE_IA64	(0*32+30) /* IA-64 processor */
   16.21  
   16.22 @@ -64,9 +63,7 @@
   16.23  #define X86_FEATURE_CYRIX_ARR	(3*32+ 2) /* Cyrix ARRs (= MTRRs) */
   16.24  #define X86_FEATURE_CENTAUR_MCR	(3*32+ 3) /* Centaur MCRs (= MTRRs) */
   16.25  
   16.26 -#define cpu_has(c, bit)		test_bit(bit, (c)->x86_capability)
   16.27 -
   16.28 -#endif /* __ASM_I386_CPUFEATURE_H */
   16.29 +#endif /* __ASM_X8664_CPUFEATURE_H */
   16.30  
   16.31  /* 
   16.32   * Local Variables:
    17.1 --- a/xen/include/asm-x86_64/current.h	Wed Mar 10 13:44:42 2004 +0000
    17.2 +++ b/xen/include/asm-x86_64/current.h	Wed Mar 10 13:46:20 2004 +0000
    17.3 @@ -1,16 +1,18 @@
    17.4 -#ifndef _I386_CURRENT_H
    17.5 -#define _I386_CURRENT_H
    17.6 +#ifndef _X86_64_CURRENT_H
    17.7 +#define _X86_64_CURRENT_H
    17.8  
    17.9 +#if !defined(__ASSEMBLY__)
   17.10  struct task_struct;
   17.11  
   17.12 +#include <asm/pda.h>
   17.13 +
   17.14  #define STACK_RESERVED \
   17.15 -    (sizeof(execution_context_t) + sizeof(struct task_struct *))
   17.16 +    (sizeof(execution_context_t))
   17.17  
   17.18  static inline struct task_struct * get_current(void)
   17.19  {
   17.20      struct task_struct *current;
   17.21 -    __asm__ ( "orl %%esp,%0; andl $~3,%0; movl (%0),%0" 
   17.22 -              : "=r" (current) : "0" (STACK_SIZE-4) );
   17.23 +    current = read_pda(pcurrent);
   17.24      return current;
   17.25  }
   17.26   
   17.27 @@ -18,30 +20,29 @@ static inline struct task_struct * get_c
   17.28  
   17.29  static inline void set_current(struct task_struct *p)
   17.30  {
   17.31 -    __asm__ ( "orl %%esp,%0; andl $~3,%0; movl %1,(%0)" 
   17.32 -              : : "r" (STACK_SIZE-4), "r" (p) );    
   17.33 +    write_pda(pcurrent,p);
   17.34  }
   17.35  
   17.36  static inline execution_context_t *get_execution_context(void)
   17.37  {
   17.38      execution_context_t *execution_context;
   17.39 -    __asm__ ( "andl %%esp,%0; addl %2,%0"
   17.40 -              : "=r" (execution_context) 
   17.41 -              : "0" (~(STACK_SIZE-1)), "i" (STACK_SIZE-STACK_RESERVED) );
   17.42 +    __asm__( "andq %%rsp,%0; addl %2,%0"
   17.43 +	    : "=r" (execution_context)
   17.44 +	    : "0" (~(STACK_SIZE-1)), "i" (STACK_SIZE-STACK_RESERVED) ); 
   17.45      return execution_context;
   17.46  }
   17.47  
   17.48  static inline unsigned long get_stack_top(void)
   17.49  {
   17.50      unsigned long p;
   17.51 -    __asm__ ( "orl %%esp,%0; andl $~3,%0" 
   17.52 -              : "=r" (p) : "0" (STACK_SIZE-4) );
   17.53 +    __asm__ ( "orq %%rsp,%0; andq $~7,%0" 
   17.54 +              : "=r" (p) : "0" (STACK_SIZE-8) );
   17.55      return p;
   17.56  }
   17.57  
   17.58  #define schedule_tail(_p)                                         \
   17.59      __asm__ __volatile__ (                                        \
   17.60 -        "andl %%esp,%0; addl %2,%0; movl %0,%%esp; jmp *%1"       \
   17.61 +        "andq %%rsp,%0; addq %2,%0; movl %0,%%rsp; jmp *%1"       \
   17.62          : : "r" (~(STACK_SIZE-1)),                                \
   17.63              "r" (unlikely(is_idle_task((_p))) ?                   \
   17.64                                  continue_cpu_idle_loop :          \
   17.65 @@ -49,4 +50,14 @@ static inline unsigned long get_stack_to
   17.66              "i" (STACK_SIZE-STACK_RESERVED) )
   17.67  
   17.68  
   17.69 -#endif /* !(_I386_CURRENT_H) */
   17.70 +#else
   17.71 +
   17.72 +#ifndef ASM_OFFSET_H
   17.73 +#include <asm/offset.h> 
   17.74 +#endif
   17.75 +
   17.76 +#define GET_CURRENT(reg) movq %gs:(pda_pcurrent),reg
   17.77 +
   17.78 +#endif
   17.79 +
   17.80 +#endif /* !(_X86_64_CURRENT_H) */
    18.1 --- a/xen/include/asm-x86_64/debugreg.h	Wed Mar 10 13:44:42 2004 +0000
    18.2 +++ b/xen/include/asm-x86_64/debugreg.h	Wed Mar 10 13:46:20 2004 +0000
    18.3 @@ -1,5 +1,5 @@
    18.4 -#ifndef _I386_DEBUGREG_H
    18.5 -#define _I386_DEBUGREG_H
    18.6 +#ifndef _X86_64_DEBUGREG_H
    18.7 +#define _X86_64_DEBUGREG_H
    18.8  
    18.9  
   18.10  /* Indicate the register numbers for a number of the specific
   18.11 @@ -38,6 +38,7 @@
   18.12  #define DR_LEN_1 (0x0) /* Settings for data length to trap on */
   18.13  #define DR_LEN_2 (0x4)
   18.14  #define DR_LEN_4 (0xC)
   18.15 +#define DR_LEN_8 (0x8)
   18.16  
   18.17  /* The low byte to the control register determine which registers are
   18.18     enabled.  There are 4 fields of two bits.  One bit is "local", meaning
   18.19 @@ -57,7 +58,7 @@
   18.20     We can slow the instruction pipeline for instructions coming via the
   18.21     gdt or the ldt if we want to.  I am not sure why this is an advantage */
   18.22  
   18.23 -#define DR_CONTROL_RESERVED (0xFC00) /* Reserved by Intel */
   18.24 +#define DR_CONTROL_RESERVED (0xFFFFFFFF0000FC00UL) /* Reserved */
   18.25  #define DR_LOCAL_SLOWDOWN (0x100)   /* Local slow the pipeline */
   18.26  #define DR_GLOBAL_SLOWDOWN (0x200)  /* Global slow the pipeline */
   18.27  
    19.1 --- a/xen/include/asm-x86_64/delay.h	Wed Mar 10 13:44:42 2004 +0000
    19.2 +++ b/xen/include/asm-x86_64/delay.h	Wed Mar 10 13:46:20 2004 +0000
    19.3 @@ -1,5 +1,5 @@
    19.4 -#ifndef _I386_DELAY_H
    19.5 -#define _I386_DELAY_H
    19.6 +#ifndef _X86_64_DELAY_H
    19.7 +#define _X86_64_DELAY_H
    19.8  
    19.9  /*
   19.10   * Copyright (C) 1993 Linus Torvalds
   19.11 @@ -11,4 +11,4 @@ extern unsigned long ticks_per_usec;
   19.12  extern void __udelay(unsigned long usecs);
   19.13  #define udelay(n) __udelay(n)
   19.14  
   19.15 -#endif /* defined(_I386_DELAY_H) */
   19.16 +#endif /* defined(_X86_64_DELAY_H) */
    20.1 --- a/xen/include/asm-x86_64/desc.h	Wed Mar 10 13:44:42 2004 +0000
    20.2 +++ b/xen/include/asm-x86_64/desc.h	Wed Mar 10 13:46:20 2004 +0000
    20.3 @@ -1,17 +1,19 @@
    20.4  #ifndef __ARCH_DESC_H
    20.5  #define __ARCH_DESC_H
    20.6  
    20.7 -#define LDT_ENTRY_SIZE 8
    20.8 +#define LDT_ENTRY_SIZE 16
    20.9  
   20.10  #define __DOUBLEFAULT_TSS_ENTRY FIRST_RESERVED_GDT_ENTRY
   20.11  
   20.12 -#define __FIRST_TSS_ENTRY (FIRST_RESERVED_GDT_ENTRY + 8)
   20.13 -#define __FIRST_LDT_ENTRY (__FIRST_TSS_ENTRY + 1)
   20.14 +#define __FIRST_PER_CPU_ENTRY (FIRST_RESERVED_GDT_ENTRY + 8)
   20.15  
   20.16 -#define __TSS(n) (((n)<<1) + __FIRST_TSS_ENTRY)
   20.17 +#define __CPU_DESC_INDEX(x,field) \
   20.18 +	((x) * sizeof(struct per_cpu_gdt) + offsetof(struct per_cpu_gdt, field) + (FIRST_PER_CPU_ENTRY*8))
   20.19  #define __LDT(n) (((n)<<1) + __FIRST_LDT_ENTRY)
   20.20  
   20.21 -#define load_TR(n)  __asm__ __volatile__ ("ltr  %%ax" : : "a" (__TSS(n)<<3) )
   20.22 +#define load_TR(cpu) asm volatile("ltr %w0"::"r" (__CPU_DESC_INDEX(cpu, tss)));
   20.23 +#define __load_LDT(cpu) asm volatile("lldt %w0"::"r" (__CPU_DESC_INDEX(cpu, ldt)));
   20.24 +#define clear_LDT(n)  asm volatile("lldt %w0"::"r" (0))
   20.25  
   20.26  /*
   20.27   * Guest OS must provide its own code selectors, or use the one we provide. The
   20.28 @@ -24,8 +26,8 @@
   20.29      (((((_s)>>3) < FIRST_RESERVED_GDT_ENTRY) ||                            \
   20.30        (((_s)>>3) >  LAST_RESERVED_GDT_ENTRY) ||                            \
   20.31        ((_s)&4)) &&                                                         \
   20.32 -     (((_s)&3) == 1))
   20.33 -#define VALID_CODESEL(_s) ((_s) == FLAT_RING1_CS || VALID_SEL(_s))
   20.34 +     (((_s)&3) == 0))
   20.35 +#define VALID_CODESEL(_s) ((_s) == FLAT_RING3_CS || VALID_SEL(_s))
   20.36  
   20.37  /* These are bitmasks for the first 32 bits of a descriptor table entry. */
   20.38  #define _SEGMENT_TYPE    (15<< 8)
   20.39 @@ -35,17 +37,75 @@
   20.40  #define _SEGMENT_G       ( 1<<23) /* Granularity */
   20.41  
   20.42  #ifndef __ASSEMBLY__
   20.43 -struct desc_struct {
   20.44 -	unsigned long a,b;
   20.45 +
   20.46 +enum { 
   20.47 +	GATE_INTERRUPT = 0xE, 
   20.48 +	GATE_TRAP = 0xF, 	
   20.49 +	GATE_CALL = 0xC,
   20.50 +}; 	
   20.51 +
   20.52 +// 16byte gate
   20.53 +struct gate_struct {          
   20.54 +	u16 offset_low;
   20.55 +	u16 segment; 
   20.56 +	unsigned ist : 3, zero0 : 5, type : 5, dpl : 2, p : 1;
   20.57 +	u16 offset_middle;
   20.58 +	u32 offset_high;
   20.59 +	u32 zero1; 
   20.60 +} __attribute__((packed));
   20.61 +
   20.62 +// 8 byte segment descriptor
   20.63 +struct desc_struct { 
   20.64 +	u16 limit0;
   20.65 +	u16 base0;
   20.66 +	unsigned base1 : 8, type : 4, s : 1, dpl : 2, p : 1;
   20.67 +	unsigned limit : 4, avl : 1, l : 1, d : 1, g : 1, base2 : 8;
   20.68 +} __attribute__((packed)); 
   20.69 +
   20.70 +// LDT or TSS descriptor in the GDT. 16 bytes.
   20.71 +struct ldttss_desc { 
   20.72 +	u16 limit0;
   20.73 +	u16 base0;
   20.74 +	unsigned base1 : 8, type : 5, dpl : 2, p : 1;
   20.75 +	unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
   20.76 +	u32 base3;
   20.77 +	u32 zero1; 
   20.78 +} __attribute__((packed)); 
   20.79 +
   20.80 +// Union of above structures
   20.81 +union desc_union {
   20.82 +	struct desc_struct seg;
   20.83 +	struct ldttss_desc ldttss;
   20.84 +	struct gate_struct gate;
   20.85  };
   20.86  
   20.87 -extern struct desc_struct gdt_table[];
   20.88 -extern struct desc_struct *idt, *gdt;
   20.89 +struct per_cpu_gdt {
   20.90 +	struct ldttss_desc tss;
   20.91 +	struct ldttss_desc ldt; 
   20.92 +} ____cacheline_aligned; 
   20.93 +
   20.94  
   20.95  struct Xgt_desc_struct {
   20.96  	unsigned short size;
   20.97 -	unsigned long address __attribute__((packed));
   20.98 -};
   20.99 +	unsigned long address;
  20.100 +} __attribute__((packed));
  20.101 +
  20.102 +extern __u8 gdt_table[];
  20.103 +extern __u8 gdt_end[];
  20.104 +extern union desc_union *gdt; 
  20.105 +
  20.106 +extern struct per_cpu_gdt gdt_cpu_table[]; 
  20.107 +
  20.108 +#define PTR_LOW(x) ((unsigned long)(x) & 0xFFFF) 
  20.109 +#define PTR_MIDDLE(x) (((unsigned long)(x) >> 16) & 0xFFFF)
  20.110 +#define PTR_HIGH(x) ((unsigned long)(x) >> 32)
  20.111 +
  20.112 +enum { 
  20.113 +	DESC_TSS = 0x9,
  20.114 +	DESC_LDT = 0x2,
  20.115 +}; 
  20.116 +
  20.117 +extern struct gate_struct *idt;
  20.118  
  20.119  #define idt_descr (*(struct Xgt_desc_struct *)((char *)&idt - 2))
  20.120  #define gdt_descr (*(struct Xgt_desc_struct *)((char *)&gdt - 2))
    21.1 --- a/xen/include/asm-x86_64/domain_page.h	Wed Mar 10 13:44:42 2004 +0000
    21.2 +++ b/xen/include/asm-x86_64/domain_page.h	Wed Mar 10 13:46:20 2004 +0000
    21.3 @@ -9,21 +9,19 @@
    21.4  
    21.5  #include <xeno/config.h>
    21.6  #include <xeno/sched.h>
    21.7 -
    21.8 -extern unsigned long *mapcache;
    21.9 -#define MAPCACHE_ENTRIES        1024
   21.10 +#include <asm/page.h>
   21.11  
   21.12  /*
   21.13   * Maps a given physical address, returning corresponding virtual address.
   21.14   * The entire page containing that VA is now accessible until a 
   21.15   * corresponding call to unmap_domain_mem().
   21.16   */
   21.17 -extern void *map_domain_mem(unsigned long pa);
   21.18 +#define map_domain_mem(pa) __va(pa)
   21.19  
   21.20  /*
   21.21   * Pass a VA within a page previously mapped with map_domain_mem().
   21.22   * That page will then be removed from the mapping lists.
   21.23   */
   21.24 -extern void unmap_domain_mem(void *va);
   21.25 +#define unmap_domain_mem(va) {}
   21.26  
   21.27  #endif /* __ASM_DOMAIN_PAGE_H__ */
    22.1 --- a/xen/include/asm-x86_64/fixmap.h	Wed Mar 10 13:44:42 2004 +0000
    22.2 +++ b/xen/include/asm-x86_64/fixmap.h	Wed Mar 10 13:46:20 2004 +0000
    22.3 @@ -74,7 +74,7 @@ extern void __set_fixmap (enum fixed_add
    22.4   * the start of the fixmap, and leave one page empty
    22.5   * at the top of mem..
    22.6   */
    22.7 -#define FIXADDR_TOP	(0xffffe000UL)
    22.8 +#define FIXADDR_TOP	(0xffffffffffffe000UL)
    22.9  #define FIXADDR_SIZE	(__end_of_fixed_addresses << PAGE_SHIFT)
   22.10  #define FIXADDR_START	(FIXADDR_TOP - FIXADDR_SIZE)
   22.11  
    23.1 --- a/xen/include/asm-x86_64/hdreg.h	Wed Mar 10 13:44:42 2004 +0000
    23.2 +++ b/xen/include/asm-x86_64/hdreg.h	Wed Mar 10 13:46:20 2004 +0000
    23.3 @@ -1,12 +1,13 @@
    23.4  /*
    23.5 - *  linux/include/asm-i386/hdreg.h
    23.6 + *  linux/include/asm-x86_64/hdreg.h
    23.7   *
    23.8   *  Copyright (C) 1994-1996  Linus Torvalds & authors
    23.9   */
   23.10  
   23.11 -#ifndef __ASMi386_HDREG_H
   23.12 -#define __ASMi386_HDREG_H
   23.13 +#ifndef __ASMx86_64_HDREG_H
   23.14 +#define __ASMx86_64_HDREG_H
   23.15  
   23.16 -typedef unsigned short ide_ioreg_t;
   23.17 +//typedef unsigned short ide_ioreg_t;
   23.18 +typedef unsigned long ide_ioreg_t;
   23.19  
   23.20 -#endif /* __ASMi386_HDREG_H */
   23.21 +#endif /* __ASMx86_64_HDREG_H */
    24.1 --- a/xen/include/asm-x86_64/ide.h	Wed Mar 10 13:44:42 2004 +0000
    24.2 +++ b/xen/include/asm-x86_64/ide.h	Wed Mar 10 13:46:20 2004 +0000
    24.3 @@ -1,15 +1,15 @@
    24.4  /*
    24.5 - *  linux/include/asm-i386/ide.h
    24.6 + *  linux/include/asm-x86_64/ide.h
    24.7   *
    24.8   *  Copyright (C) 1994-1996  Linus Torvalds & authors
    24.9   */
   24.10  
   24.11  /*
   24.12 - *  This file contains the i386 architecture specific IDE code.
   24.13 + *  This file contains the x86_64 architecture specific IDE code.
   24.14   */
   24.15  
   24.16 -#ifndef __ASMi386_IDE_H
   24.17 -#define __ASMi386_IDE_H
   24.18 +#ifndef __ASMx86_64_IDE_H
   24.19 +#define __ASMx86_64_IDE_H
   24.20  
   24.21  #ifdef __KERNEL__
   24.22  
   24.23 @@ -23,8 +23,6 @@
   24.24  # endif
   24.25  #endif
   24.26  
   24.27 -#define ide__sti()	__sti()
   24.28 -
   24.29  static __inline__ int ide_default_irq(ide_ioreg_t base)
   24.30  {
   24.31  	switch (base) {
   24.32 @@ -79,6 +77,7 @@ static __inline__ void ide_init_default_
   24.33  	int index;
   24.34  
   24.35  	for(index = 0; index < MAX_HWIFS; index++) {
   24.36 +		memset(&hw, 0, sizeof hw);
   24.37  		ide_init_hwif_ports(&hw, ide_default_io_base(index), 0, NULL);
   24.38  		hw.irq = ide_default_irq(ide_default_io_base(index));
   24.39  		ide_register_hw(&hw, NULL);
   24.40 @@ -125,4 +124,4 @@ typedef union {
   24.41  
   24.42  #endif /* __KERNEL__ */
   24.43  
   24.44 -#endif /* __ASMi386_IDE_H */
   24.45 +#endif /* __ASMx86_64_IDE_H */
    25.1 --- a/xen/include/asm-x86_64/io.h	Wed Mar 10 13:44:42 2004 +0000
    25.2 +++ b/xen/include/asm-x86_64/io.h	Wed Mar 10 13:46:20 2004 +0000
    25.3 @@ -1,18 +1,115 @@
    25.4  #ifndef _ASM_IO_H
    25.5  #define _ASM_IO_H
    25.6  
    25.7 -#include <xeno/config.h>
    25.8 -#include <asm/page.h>
    25.9 +#include <linux/config.h>
   25.10 +
   25.11 +/*
   25.12 + * This file contains the definitions for the x86 IO instructions
   25.13 + * inb/inw/inl/outb/outw/outl and the "string versions" of the same
   25.14 + * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
   25.15 + * versions of the single-IO instructions (inb_p/inw_p/..).
   25.16 + *
   25.17 + * This file is not meant to be obfuscating: it's just complicated
   25.18 + * to (a) handle it all in a way that makes gcc able to optimize it
   25.19 + * as well as possible and (b) trying to avoid writing the same thing
   25.20 + * over and over again with slight variations and possibly making a
   25.21 + * mistake somewhere.
   25.22 + */
   25.23 +
   25.24 +/*
   25.25 + * Thanks to James van Artsdalen for a better timing-fix than
   25.26 + * the two short jumps: using outb's to a nonexistent port seems
   25.27 + * to guarantee better timings even on fast machines.
   25.28 + *
   25.29 + * On the other hand, I'd like to be sure of a non-existent port:
   25.30 + * I feel a bit unsafe about using 0x80 (should be safe, though)
   25.31 + *
   25.32 + *		Linus
   25.33 + */
   25.34 +
   25.35 + /*
   25.36 +  *  Bit simplified and optimized by Jan Hubicka
   25.37 +  *  Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999.
   25.38 +  *
   25.39 +  *  isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added,
   25.40 +  *  isa_read[wl] and isa_write[wl] fixed
   25.41 +  *  - Arnaldo Carvalho de Melo <acme@conectiva.com.br>
   25.42 +  */
   25.43 +
   25.44 +#ifdef SLOW_IO_BY_JUMPING
   25.45 +#define __SLOW_DOWN_IO "\njmp 1f\n1:\tjmp 1f\n1:"
   25.46 +#else
   25.47 +#define __SLOW_DOWN_IO "\noutb %%al,$0x80"
   25.48 +#endif
   25.49 +
   25.50 +#ifdef REALLY_SLOW_IO
   25.51 +#define __FULL_SLOW_DOWN_IO __SLOW_DOWN_IO __SLOW_DOWN_IO __SLOW_DOWN_IO __SLOW_DOWN_IO
   25.52 +#else
   25.53 +#define __FULL_SLOW_DOWN_IO __SLOW_DOWN_IO
   25.54 +#endif
   25.55 +
   25.56 +/*
   25.57 + * Talk about misusing macros..
   25.58 + */
   25.59 +#define __OUT1(s,x) \
   25.60 +extern inline void out##s(unsigned x value, unsigned short port) {
   25.61 +
   25.62 +#define __OUT2(s,s1,s2) \
   25.63 +__asm__ __volatile__ ("out" #s " %" s1 "0,%" s2 "1"
   25.64 +
   25.65 +#define __OUT(s,s1,x) \
   25.66 +__OUT1(s,x) __OUT2(s,s1,"w") : : "a" (value), "Nd" (port)); } \
   25.67 +__OUT1(s##_p,x) __OUT2(s,s1,"w") __FULL_SLOW_DOWN_IO : : "a" (value), "Nd" (port));} \
   25.68 +
   25.69 +#define __IN1(s) \
   25.70 +extern inline RETURN_TYPE in##s(unsigned short port) { RETURN_TYPE _v;
   25.71 +
   25.72 +#define __IN2(s,s1,s2) \
   25.73 +__asm__ __volatile__ ("in" #s " %" s2 "1,%" s1 "0"
   25.74 +
   25.75 +#define __IN(s,s1,i...) \
   25.76 +__IN1(s) __IN2(s,s1,"w") : "=a" (_v) : "Nd" (port) ,##i ); return _v; } \
   25.77 +__IN1(s##_p) __IN2(s,s1,"w") __FULL_SLOW_DOWN_IO : "=a" (_v) : "Nd" (port) ,##i ); return _v; } \
   25.78 +
   25.79 +#define __INS(s) \
   25.80 +extern inline void ins##s(unsigned short port, void * addr, unsigned long count) \
   25.81 +{ __asm__ __volatile__ ("rep ; ins" #s \
   25.82 +: "=D" (addr), "=c" (count) : "d" (port),"0" (addr),"1" (count)); }
   25.83 +
   25.84 +#define __OUTS(s) \
   25.85 +extern inline void outs##s(unsigned short port, const void * addr, unsigned long count) \
   25.86 +{ __asm__ __volatile__ ("rep ; outs" #s \
   25.87 +: "=S" (addr), "=c" (count) : "d" (port),"0" (addr),"1" (count)); }
   25.88 +
   25.89 +#define RETURN_TYPE unsigned char
   25.90 +__IN(b,"")
   25.91 +#undef RETURN_TYPE
   25.92 +#define RETURN_TYPE unsigned short
   25.93 +__IN(w,"")
   25.94 +#undef RETURN_TYPE
   25.95 +#define RETURN_TYPE unsigned int
   25.96 +__IN(l,"")
   25.97 +#undef RETURN_TYPE
   25.98 +
   25.99 +__OUT(b,"b",char)
  25.100 +__OUT(w,"w",short)
  25.101 +__OUT(l,,int)
  25.102 +
  25.103 +__INS(b)
  25.104 +__INS(w)
  25.105 +__INS(l)
  25.106 +
  25.107 +__OUTS(b)
  25.108 +__OUTS(w)
  25.109 +__OUTS(l)
  25.110  
  25.111  #define IO_SPACE_LIMIT 0xffff
  25.112  
  25.113 -/*#include <linux/vmalloc.h>*/
  25.114 -
  25.115  /*
  25.116   * Temporary debugging check to catch old code using
  25.117   * unmapped ISA addresses. Will be removed in 2.4.
  25.118   */
  25.119 -#if CONFIG_DEBUG_IOVIRT
  25.120 +#ifdef CONFIG_IO_DEBUG
  25.121    extern void *__io_virt_debug(unsigned long x, const char *file, int line);
  25.122    extern unsigned long __io_phys_debug(unsigned long x, const char *file, int line);
  25.123    #define __io_virt(x) __io_virt_debug((unsigned long)(x), __FILE__, __LINE__)
  25.124 @@ -22,59 +119,32 @@
  25.125  //#define __io_phys(x) __pa(x)
  25.126  #endif
  25.127  
  25.128 -
  25.129 -/**
  25.130 - *  virt_to_phys    -   map virtual addresses to physical
  25.131 - *  @address: address to remap
  25.132 - *
  25.133 - *  The returned physical address is the physical (CPU) mapping for
  25.134 - *  the memory address given. It is only valid to use this function on
  25.135 - *  addresses directly mapped or allocated via kmalloc.
  25.136 - *
  25.137 - *  This function does not give bus mappings for DMA transfers. In
  25.138 - *  almost all conceivable cases a device driver should not be using
  25.139 - *  this function
  25.140 +/*
  25.141 + * Change virtual addresses to physical addresses and vv.
  25.142 + * These are pretty trivial
  25.143   */
  25.144 -
  25.145 -static inline unsigned long virt_to_phys(volatile void * address)
  25.146 +extern inline unsigned long virt_to_phys(volatile void * address)
  25.147  {
  25.148 -    return __pa(address);
  25.149 +	return __pa(address);
  25.150  }
  25.151  
  25.152 -/**
  25.153 - *  phys_to_virt    -   map physical address to virtual
  25.154 - *  @address: address to remap
  25.155 - *
  25.156 - *  The returned virtual address is a current CPU mapping for
  25.157 - *  the memory address given. It is only valid to use this function on
  25.158 - *  addresses that have a kernel mapping
  25.159 - *
  25.160 - *  This function does not handle bus mappings for DMA transfers. In
  25.161 - *  almost all conceivable cases a device driver should not be using
  25.162 - *  this function
  25.163 - */
  25.164 -
  25.165 -static inline void * phys_to_virt(unsigned long address)
  25.166 +extern inline void * phys_to_virt(unsigned long address)
  25.167  {
  25.168 -    return __va(address);
  25.169 +	return __va(address);
  25.170  }
  25.171  
  25.172  /*
  25.173 - * Change "struct pfn_info" to physical address.
  25.174 + * Change "struct page" to physical address.
  25.175   */
  25.176 -#ifdef CONFIG_HIGHMEM64G
  25.177 -#define page_to_phys(page)  ((u64)(page - frame_table) << PAGE_SHIFT)
  25.178 +#ifdef CONFIG_DISCONTIGMEM
  25.179 +#include <asm/mmzone.h>
  25.180  #else
  25.181 -#define page_to_phys(page)  ((page - frame_table) << PAGE_SHIFT)
  25.182 +#define page_to_phys(page)	(((page) - frame_table) << PAGE_SHIFT)
  25.183  #endif
  25.184  
  25.185 -#define page_to_pfn(_page)  ((unsigned long)((_page) - frame_table))
  25.186 -#define page_to_virt(_page) phys_to_virt(page_to_phys(_page))
  25.187 -
  25.188 -
  25.189  extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
  25.190  
  25.191 -static inline void * ioremap (unsigned long offset, unsigned long size)
  25.192 +extern inline void * ioremap (unsigned long offset, unsigned long size)
  25.193  {
  25.194  	return __ioremap(offset, size, 0);
  25.195  }
  25.196 @@ -84,7 +154,7 @@ static inline void * ioremap (unsigned l
  25.197   * it's useful if some control registers are in such an area and write combining
  25.198   * or read caching is not desirable:
  25.199   */
  25.200 -static inline void * ioremap_nocache (unsigned long offset, unsigned long size)
  25.201 +extern inline void * ioremap_nocache (unsigned long offset, unsigned long size)
  25.202  {
  25.203          return __ioremap(offset, size, _PAGE_PCD);
  25.204  }
  25.205 @@ -108,20 +178,25 @@ extern void iounmap(void *addr);
  25.206  #define readb(addr) (*(volatile unsigned char *) __io_virt(addr))
  25.207  #define readw(addr) (*(volatile unsigned short *) __io_virt(addr))
  25.208  #define readl(addr) (*(volatile unsigned int *) __io_virt(addr))
  25.209 +#define readq(addr) (*(volatile unsigned long *) __io_virt(addr))
  25.210  #define __raw_readb readb
  25.211  #define __raw_readw readw
  25.212  #define __raw_readl readl
  25.213 +#define __raw_readq readq
  25.214  
  25.215  #define writeb(b,addr) (*(volatile unsigned char *) __io_virt(addr) = (b))
  25.216  #define writew(b,addr) (*(volatile unsigned short *) __io_virt(addr) = (b))
  25.217  #define writel(b,addr) (*(volatile unsigned int *) __io_virt(addr) = (b))
  25.218 +#define writeq(b,addr) (*(volatile unsigned long *) __io_virt(addr) = (b))
  25.219  #define __raw_writeb writeb
  25.220  #define __raw_writew writew
  25.221  #define __raw_writel writel
  25.222 +#define __raw_writeq writeq
  25.223 +
  25.224 +void *memcpy_fromio(void*,const void*,unsigned); 
  25.225 +void *memcpy_toio(void*,const void*,unsigned); 
  25.226  
  25.227  #define memset_io(a,b,c)	memset(__io_virt(a),(b),(c))
  25.228 -#define memcpy_fromio(a,b,c)	memcpy((a),__io_virt(b),(c))
  25.229 -#define memcpy_toio(a,b,c)	memcpy(__io_virt(a),(b),(c))
  25.230  
  25.231  /*
  25.232   * ISA space is 'always mapped' on a typical x86 system, no need to
  25.233 @@ -145,7 +220,7 @@ extern void iounmap(void *addr);
  25.234  
  25.235  
  25.236  /*
  25.237 - * Again, i386 does not require mem IO specific function.
  25.238 + * Again, x86-64 does not require mem IO specific function.
  25.239   */
  25.240  
  25.241  #define eth_io_copy_and_sum(a,b,c,d)		eth_copy_and_sum((a),__io_virt(b),(c),(d))
  25.242 @@ -183,102 +258,12 @@ out:
  25.243  	return retval;
  25.244  }
  25.245  
  25.246 -/*
  25.247 - *	Cache management
  25.248 - *
  25.249 - *	This needed for two cases
  25.250 - *	1. Out of order aware processors
  25.251 - *	2. Accidentally out of order processors (PPro errata #51)
  25.252 - */
  25.253 - 
  25.254 -#if defined(CONFIG_X86_OOSTORE) || defined(CONFIG_X86_PPRO_FENCE)
  25.255 -
  25.256 -static inline void flush_write_buffers(void)
  25.257 -{
  25.258 -	__asm__ __volatile__ ("lock; addl $0,0(%%esp)": : :"memory");
  25.259 -}
  25.260 -
  25.261 -#define dma_cache_inv(_start,_size)		flush_write_buffers()
  25.262 -#define dma_cache_wback(_start,_size)		flush_write_buffers()
  25.263 -#define dma_cache_wback_inv(_start,_size)	flush_write_buffers()
  25.264 -
  25.265 -#else
  25.266 -
  25.267  /* Nothing to do */
  25.268  
  25.269  #define dma_cache_inv(_start,_size)		do { } while (0)
  25.270  #define dma_cache_wback(_start,_size)		do { } while (0)
  25.271  #define dma_cache_wback_inv(_start,_size)	do { } while (0)
  25.272 -#define flush_write_buffers()
  25.273 +
  25.274 +#define flush_write_buffers() 
  25.275  
  25.276  #endif
  25.277 -
  25.278 -#ifdef SLOW_IO_BY_JUMPING
  25.279 -#define __SLOW_DOWN_IO "\njmp 1f\n1:\tjmp 1f\n1:"
  25.280 -#else
  25.281 -#define __SLOW_DOWN_IO "\noutb %%al,$0x80"
  25.282 -#endif
  25.283 -
  25.284 -#ifdef REALLY_SLOW_IO
  25.285 -#define __FULL_SLOW_DOWN_IO __SLOW_DOWN_IO __SLOW_DOWN_IO __SLOW_DOWN_IO __SLOW_DOWN_IO
  25.286 -#else
  25.287 -#define __FULL_SLOW_DOWN_IO __SLOW_DOWN_IO
  25.288 -#endif
  25.289 -
  25.290 -
  25.291 -/*
  25.292 - * Talk about misusing macros..
  25.293 - */
  25.294 -#define __OUT1(s,x) \
  25.295 -static inline void out##s(unsigned x value, unsigned short port) {
  25.296 -
  25.297 -#define __OUT2(s,s1,s2) \
  25.298 -__asm__ __volatile__ ("out" #s " %" s1 "0,%" s2 "1"
  25.299 -
  25.300 -#define __OUT(s,s1,x) \
  25.301 -__OUT1(s,x) __OUT2(s,s1,"w") : : "a" (value), "Nd" (port)); } \
  25.302 -__OUT1(s##_p,x) __OUT2(s,s1,"w") __FULL_SLOW_DOWN_IO : : "a" (value), "Nd" (port));} 
  25.303 -
  25.304 -#define __IN1(s) \
  25.305 -static inline RETURN_TYPE in##s(unsigned short port) { RETURN_TYPE _v;
  25.306 -
  25.307 -#define __IN2(s,s1,s2) \
  25.308 -__asm__ __volatile__ ("in" #s " %" s2 "1,%" s1 "0"
  25.309 -
  25.310 -#define __IN(s,s1,i...) \
  25.311 -__IN1(s) __IN2(s,s1,"w") : "=a" (_v) : "Nd" (port) ,##i ); return _v; } \
  25.312 -__IN1(s##_p) __IN2(s,s1,"w") __FULL_SLOW_DOWN_IO : "=a" (_v) : "Nd" (port) ,##i ); return _v; } 
  25.313 -
  25.314 -#define __INS(s) \
  25.315 -static inline void ins##s(unsigned short port, void * addr, unsigned long count) \
  25.316 -{ __asm__ __volatile__ ("rep ; ins" #s \
  25.317 -: "=D" (addr), "=c" (count) : "d" (port),"0" (addr),"1" (count)); }
  25.318 -
  25.319 -#define __OUTS(s) \
  25.320 -static inline void outs##s(unsigned short port, const void * addr, unsigned long count) \
  25.321 -{ __asm__ __volatile__ ("rep ; outs" #s \
  25.322 -: "=S" (addr), "=c" (count) : "d" (port),"0" (addr),"1" (count)); }
  25.323 -
  25.324 -#define RETURN_TYPE unsigned char
  25.325 -__IN(b,"")
  25.326 -#undef RETURN_TYPE
  25.327 -#define RETURN_TYPE unsigned short
  25.328 -__IN(w,"")
  25.329 -#undef RETURN_TYPE
  25.330 -#define RETURN_TYPE unsigned int
  25.331 -__IN(l,"")
  25.332 -#undef RETURN_TYPE
  25.333 -
  25.334 -__OUT(b,"b",char)
  25.335 -__OUT(w,"w",short)
  25.336 -__OUT(l,,int)
  25.337 -
  25.338 -__INS(b)
  25.339 -__INS(w)
  25.340 -__INS(l)
  25.341 -
  25.342 -__OUTS(b)
  25.343 -__OUTS(w)
  25.344 -__OUTS(l)
  25.345 -
  25.346 -#endif
    26.1 --- a/xen/include/asm-x86_64/io_apic.h	Wed Mar 10 13:44:42 2004 +0000
    26.2 +++ b/xen/include/asm-x86_64/io_apic.h	Wed Mar 10 13:46:20 2004 +0000
    26.3 @@ -97,7 +97,7 @@ extern struct mpc_config_ioapic mp_ioapi
    26.4  extern int mp_irq_entries;
    26.5  
    26.6  /* MP IRQ source entries */
    26.7 -extern struct mpc_config_intsrc *mp_irqs;
    26.8 +extern struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
    26.9  
   26.10  /* non-0 if default (table-less) MP configuration */
   26.11  extern int mpc_default_type;
    27.1 --- a/xen/include/asm-x86_64/ioctl.h	Wed Mar 10 13:44:42 2004 +0000
    27.2 +++ b/xen/include/asm-x86_64/ioctl.h	Wed Mar 10 13:46:20 2004 +0000
    27.3 @@ -1,10 +1,10 @@
    27.4 -/* $Id: ioctl.h,v 1.5 1993/07/19 21:53:50 root Exp root $
    27.5 +/* $Id: ioctl.h,v 1.2 2001/07/04 09:08:13 ak Exp $
    27.6   *
    27.7   * linux/ioctl.h for Linux by H.H. Bergman.
    27.8   */
    27.9  
   27.10 -#ifndef _ASMI386_IOCTL_H
   27.11 -#define _ASMI386_IOCTL_H
   27.12 +#ifndef _ASMX8664_IOCTL_H
   27.13 +#define _ASMX8664_IOCTL_H
   27.14  
   27.15  /* ioctl command encoding: 32 bits total, command in lower 16 bits,
   27.16   * size of the parameter structure in the lower 14 bits of the
   27.17 @@ -72,4 +72,4 @@
   27.18  #define IOCSIZE_MASK	(_IOC_SIZEMASK << _IOC_SIZESHIFT)
   27.19  #define IOCSIZE_SHIFT	(_IOC_SIZESHIFT)
   27.20  
   27.21 -#endif /* _ASMI386_IOCTL_H */
   27.22 +#endif /* _ASMX8664_IOCTL_H */
    28.1 --- a/xen/include/asm-x86_64/irq.h	Wed Mar 10 13:44:42 2004 +0000
    28.2 +++ b/xen/include/asm-x86_64/irq.h	Wed Mar 10 13:46:20 2004 +0000
    28.3 @@ -22,9 +22,14 @@ extern void enable_irq(unsigned int);
    28.4   * IDT vectors usable for external interrupt sources start
    28.5   * at 0x20:
    28.6   */
    28.7 +#define NR_VECTORS 256
    28.8  #define FIRST_EXTERNAL_VECTOR	0x30
    28.9  
   28.10 -#define NR_IRQS (256 - FIRST_EXTERNAL_VECTOR)
   28.11 +#ifdef CONFIG_X86_IO_APIC
   28.12 +#define NR_IRQS 224
   28.13 +#else
   28.14 +#define NR_IRQS 16
   28.15 +#endif
   28.16  
   28.17  #define HYPERVISOR_CALL_VECTOR	0x82
   28.18  
   28.19 @@ -47,6 +52,7 @@ extern void enable_irq(unsigned int);
   28.20  #define EVENT_CHECK_VECTOR	0xfc
   28.21  #define CALL_FUNCTION_VECTOR	0xfb
   28.22  #define KDB_VECTOR		0xfa
   28.23 +#define TASK_MIGRATION_VECTOR	0xf9
   28.24  
   28.25  /*
   28.26   * Local APIC timer IRQ vector is on a different priority level,
   28.27 @@ -100,89 +106,15 @@ extern char _stext, _etext;
   28.28  #define __STR(x) #x
   28.29  #define STR(x) __STR(x)
   28.30  
   28.31 -#define SAVE_ALL \
   28.32 -	"cld\n\t" \
   28.33 -	"pushl %gs\n\t" \
   28.34 -	"pushl %fs\n\t" \
   28.35 -	"pushl %es\n\t" \
   28.36 -	"pushl %ds\n\t" \
   28.37 -	"pushl %eax\n\t" \
   28.38 -	"pushl %ebp\n\t" \
   28.39 -	"pushl %edi\n\t" \
   28.40 -	"pushl %esi\n\t" \
   28.41 -	"pushl %edx\n\t" \
   28.42 -	"pushl %ecx\n\t" \
   28.43 -	"pushl %ebx\n\t" \
   28.44 -	"movl $" STR(__HYPERVISOR_DS) ",%edx\n\t" \
   28.45 -	"movl %edx,%ds\n\t" \
   28.46 -	"movl %edx,%es\n\t" \
   28.47 -	"movl %edx,%fs\n\t" \
   28.48 -	"movl %edx,%gs\n\t"
   28.49 -
   28.50  #define IRQ_NAME2(nr) nr##_interrupt(void)
   28.51  #define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr)
   28.52  
   28.53 -/*
   28.54 - *	SMP has a few special interrupts for IPI messages
   28.55 - */
   28.56 -
   28.57 -	/* there is a second layer of macro just to get the symbolic
   28.58 -	   name for the vector evaluated. This change is for RTLinux */
   28.59 -#define BUILD_SMP_INTERRUPT(x,v) XBUILD_SMP_INTERRUPT(x,v)
   28.60 -#define XBUILD_SMP_INTERRUPT(x,v)\
   28.61 -asmlinkage void x(void); \
   28.62 -asmlinkage void call_##x(void); \
   28.63 -__asm__( \
   28.64 -"\n"__ALIGN_STR"\n" \
   28.65 -SYMBOL_NAME_STR(x) ":\n\t" \
   28.66 -	"pushl $"#v"-256\n\t" \
   28.67 -	SAVE_ALL \
   28.68 -	SYMBOL_NAME_STR(call_##x)":\n\t" \
   28.69 -	"call "SYMBOL_NAME_STR(smp_##x)"\n\t" \
   28.70 -	"jmp ret_from_intr\n");
   28.71 -
   28.72 -#define BUILD_SMP_TIMER_INTERRUPT(x,v) XBUILD_SMP_TIMER_INTERRUPT(x,v)
   28.73 -#define XBUILD_SMP_TIMER_INTERRUPT(x,v) \
   28.74 -asmlinkage void x(struct pt_regs * regs); \
   28.75 -asmlinkage void call_##x(void); \
   28.76 -__asm__( \
   28.77 -"\n"__ALIGN_STR"\n" \
   28.78 -SYMBOL_NAME_STR(x) ":\n\t" \
   28.79 -	"pushl $"#v"-256\n\t" \
   28.80 -	SAVE_ALL \
   28.81 -	"movl %esp,%eax\n\t" \
   28.82 -	"pushl %eax\n\t" \
   28.83 -	SYMBOL_NAME_STR(call_##x)":\n\t" \
   28.84 -	"call "SYMBOL_NAME_STR(smp_##x)"\n\t" \
   28.85 -	"addl $4,%esp\n\t" \
   28.86 -	"jmp ret_from_intr\n");
   28.87 -
   28.88 -#define BUILD_COMMON_IRQ() \
   28.89 -asmlinkage void call_do_IRQ(void); \
   28.90 -__asm__( \
   28.91 -	"\n" __ALIGN_STR"\n" \
   28.92 -	"common_interrupt:\n\t" \
   28.93 -	SAVE_ALL \
   28.94 -	SYMBOL_NAME_STR(call_do_IRQ)":\n\t" \
   28.95 -	"call " SYMBOL_NAME_STR(do_IRQ) "\n\t" \
   28.96 -	"jmp ret_from_intr\n");
   28.97 -
   28.98 -/* 
   28.99 - * subtle. orig_eax is used by the signal code to distinct between
  28.100 - * system calls and interrupted 'random user-space'. Thus we have
  28.101 - * to put a negative value into orig_eax here. (the problem is that
  28.102 - * both system calls and IRQs want to have small integer numbers in
  28.103 - * orig_eax, and the syscall code has won the optimization conflict ;)
  28.104 - *
  28.105 - * Subtle as a pigs ear.  VY
  28.106 - */
  28.107 -
  28.108  #define BUILD_IRQ(nr) \
  28.109  asmlinkage void IRQ_NAME(nr); \
  28.110  __asm__( \
  28.111 -"\n"__ALIGN_STR"\n" \
  28.112 +"\n.p2align\n" \
  28.113  SYMBOL_NAME_STR(IRQ) #nr "_interrupt:\n\t" \
  28.114 -	"pushl $"#nr"-256\n\t" \
  28.115 +	"push $"#nr"-256\n\t" \
  28.116  	"jmp common_interrupt");
  28.117  
  28.118  extern unsigned long prof_cpu_mask;
    29.1 --- a/xen/include/asm-x86_64/mpspec.h	Wed Mar 10 13:44:42 2004 +0000
    29.2 +++ b/xen/include/asm-x86_64/mpspec.h	Wed Mar 10 13:46:20 2004 +0000
    29.3 @@ -29,7 +29,7 @@
    29.4  struct intel_mp_floating
    29.5  {
    29.6  	char mpf_signature[4];		/* "_MP_" 			*/
    29.7 -	unsigned long mpf_physptr;	/* Configuration table address	*/
    29.8 +	unsigned int mpf_physptr;	/* Configuration table address	*/
    29.9  	unsigned char mpf_length;	/* Our length (paragraphs)	*/
   29.10  	unsigned char mpf_specification;/* Specification version	*/
   29.11  	unsigned char mpf_checksum;	/* Checksum (makes sum 0)	*/
   29.12 @@ -49,11 +49,11 @@ struct mp_config_table
   29.13  	char  mpc_checksum;
   29.14  	char  mpc_oem[8];
   29.15  	char  mpc_productid[12];
   29.16 -	unsigned long mpc_oemptr;	/* 0 if not present */
   29.17 +	unsigned int mpc_oemptr;	/* 0 if not present */
   29.18  	unsigned short mpc_oemsize;	/* 0 if not present */
   29.19  	unsigned short mpc_oemcount;
   29.20 -	unsigned long mpc_lapic;	/* APIC address */
   29.21 -	unsigned long reserved;
   29.22 +	unsigned int mpc_lapic;	/* APIC address */
   29.23 +	unsigned int reserved;
   29.24  };
   29.25  
   29.26  /* Followed by entries */
   29.27 @@ -73,12 +73,12 @@ struct mpc_config_processor
   29.28  	unsigned char mpc_cpuflag;
   29.29  #define CPU_ENABLED		1	/* Processor is available */
   29.30  #define CPU_BOOTPROCESSOR	2	/* Processor is the BP */
   29.31 -	unsigned long mpc_cpufeature;		
   29.32 +	unsigned int mpc_cpufeature;		
   29.33  #define CPU_STEPPING_MASK 0x0F
   29.34  #define CPU_MODEL_MASK	0xF0
   29.35  #define CPU_FAMILY_MASK	0xF00
   29.36 -	unsigned long mpc_featureflag;	/* CPUID feature value */
   29.37 -	unsigned long mpc_reserved[2];
   29.38 +	unsigned int mpc_featureflag;	/* CPUID feature value */
   29.39 +	unsigned int mpc_reserved[2];
   29.40  };
   29.41  
   29.42  struct mpc_config_bus
   29.43 @@ -115,7 +115,7 @@ struct mpc_config_ioapic
   29.44  	unsigned char mpc_apicver;
   29.45  	unsigned char mpc_flags;
   29.46  #define MPC_APIC_USABLE		0x01
   29.47 -	unsigned long mpc_apicaddr;
   29.48 +	unsigned int mpc_apicaddr;
   29.49  };
   29.50  
   29.51  struct mpc_config_intsrc
   29.52 @@ -186,23 +186,18 @@ struct mpc_config_translation
   29.53   *	7	2 CPU MCA+PCI
   29.54   */
   29.55  
   29.56 -#ifdef CONFIG_MULTIQUAD
   29.57 -#define MAX_IRQ_SOURCES 512
   29.58 -#else /* !CONFIG_MULTIQUAD */
   29.59 -#define MAX_IRQ_SOURCES 256
   29.60 -#endif /* CONFIG_MULTIQUAD */
   29.61 -
   29.62 -#define MAX_MP_BUSSES 32
   29.63 +#define MAX_MP_BUSSES 257
   29.64 +#define MAX_IRQ_SOURCES (MAX_MP_BUSSES*4)
   29.65  enum mp_bustype {
   29.66  	MP_BUS_ISA = 1,
   29.67  	MP_BUS_EISA,
   29.68  	MP_BUS_PCI,
   29.69  	MP_BUS_MCA
   29.70  };
   29.71 -extern int *mp_bus_id_to_type;
   29.72 -extern int *mp_bus_id_to_node;
   29.73 -extern int *mp_bus_id_to_local;
   29.74 -extern int *mp_bus_id_to_pci_bus;
   29.75 +extern int mp_bus_id_to_type [MAX_MP_BUSSES];
   29.76 +extern int mp_bus_id_to_node [MAX_MP_BUSSES];
   29.77 +extern int mp_bus_id_to_local [MAX_MP_BUSSES];
   29.78 +extern int mp_bus_id_to_pci_bus [MAX_MP_BUSSES];
   29.79  extern int quad_local_to_mp_bus_id [NR_CPUS/4][4];
   29.80  
   29.81  extern unsigned int boot_cpu_physical_apicid;
    30.1 --- a/xen/include/asm-x86_64/msr.h	Wed Mar 10 13:44:42 2004 +0000
    30.2 +++ b/xen/include/asm-x86_64/msr.h	Wed Mar 10 13:46:20 2004 +0000
    30.3 @@ -1,6 +1,7 @@
    30.4 -#ifndef __ASM_MSR_H
    30.5 -#define __ASM_MSR_H
    30.6 +#ifndef X86_64_MSR_H
    30.7 +#define X86_64_MSR_H 1
    30.8  
    30.9 +#ifndef __ASSEMBLY__
   30.10  /*
   30.11   * Access to machine-specific registers (available on 586 and better only)
   30.12   * Note: the rd* operations modify the parameters directly (without using
   30.13 @@ -8,9 +9,17 @@
   30.14   */
   30.15  
   30.16  #define rdmsr(msr,val1,val2) \
   30.17 -     __asm__ __volatile__("rdmsr" \
   30.18 -			  : "=a" (val1), "=d" (val2) \
   30.19 -			  : "c" (msr))
   30.20 +       __asm__ __volatile__("rdmsr" \
   30.21 +			    : "=a" (val1), "=d" (val2) \
   30.22 +			    : "c" (msr))
   30.23 +
   30.24 +
   30.25 +#define rdmsrl(msr,val) do { unsigned long a__,b__; \
   30.26 +       __asm__ __volatile__("rdmsr" \
   30.27 +			    : "=a" (a__), "=d" (b__) \
   30.28 +			    : "c" (msr)); \
   30.29 +       val = a__ | (b__<<32); \
   30.30 +} while(0); 
   30.31  
   30.32  #define wrmsr(msr,val1,val2) \
   30.33       __asm__ __volatile__("wrmsr" \
   30.34 @@ -23,8 +32,11 @@
   30.35  #define rdtscl(low) \
   30.36       __asm__ __volatile__("rdtsc" : "=a" (low) : : "edx")
   30.37  
   30.38 -#define rdtscll(val) \
   30.39 -     __asm__ __volatile__("rdtsc" : "=A" (val))
   30.40 +#define rdtscll(val) do { \
   30.41 +     unsigned int a,d; \
   30.42 +     asm volatile("rdtsc" : "=a" (a), "=d" (d)); \
   30.43 +     (val) = ((unsigned long)a) | (((unsigned long)d)<<32); \
   30.44 +} while(0)
   30.45  
   30.46  #define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
   30.47  
   30.48 @@ -33,64 +45,94 @@
   30.49  			  : "=a" (low), "=d" (high) \
   30.50  			  : "c" (counter))
   30.51  
   30.52 -/* symbolic names for some interesting MSRs */
   30.53 -/* Intel defined MSRs. */
   30.54 -#define MSR_IA32_P5_MC_ADDR		0
   30.55 -#define MSR_IA32_P5_MC_TYPE		1
   30.56 -#define MSR_IA32_PLATFORM_ID		0x17
   30.57 -#define MSR_IA32_EBL_CR_POWERON		0x2a
   30.58 +#endif
   30.59  
   30.60 -#define MSR_IA32_APICBASE		0x1b
   30.61 -#define MSR_IA32_APICBASE_BSP		(1<<8)
   30.62 -#define MSR_IA32_APICBASE_ENABLE	(1<<11)
   30.63 -#define MSR_IA32_APICBASE_BASE		(0xfffff<<12)
   30.64 +/* AMD/K8 specific MSRs */ 
   30.65 +#define MSR_EFER 0xc0000080		/* extended feature register */
   30.66 +#define MSR_STAR 0xc0000081		/* legacy mode SYSCALL target */
   30.67 +#define MSR_LSTAR 0xc0000082 		/* long mode SYSCALL target */
   30.68 +#define MSR_CSTAR 0xc0000083		/* compatibility mode SYSCALL target */
   30.69 +#define MSR_SYSCALL_MASK 0xc0000084	/* EFLAGS mask for syscall */
   30.70 +#define MSR_FS_BASE 0xc0000100		/* 64bit GS base */
   30.71 +#define MSR_GS_BASE 0xc0000101		/* 64bit FS base */
   30.72 +#define MSR_KERNEL_GS_BASE  0xc0000102	/* SwapGS GS shadow (or USER_GS from kernel) */ 
   30.73 +/* EFER bits: */ 
   30.74 +#define _EFER_SCE 0  /* SYSCALL/SYSRET */
   30.75 +#define _EFER_LME 8  /* Long mode enable */
   30.76 +#define _EFER_LMA 10 /* Long mode active (read-only) */
   30.77 +#define _EFER_NX 11  /* No execute enable */
   30.78  
   30.79 -#define MSR_IA32_UCODE_WRITE		0x79
   30.80 -#define MSR_IA32_UCODE_REV		0x8b
   30.81 +#define EFER_SCE (1<<_EFER_SCE)
   30.82 +#define EFER_LME (1<<EFER_LME)
   30.83 +#define EFER_LMA (1<<EFER_LMA)
   30.84 +#define EFER_NX (1<<_EFER_NX)
   30.85  
   30.86 -#define MSR_IA32_BBL_CR_CTL		0x119
   30.87 +/* Intel MSRs. Some also available on other CPUs */
   30.88 +#define MSR_IA32_PLATFORM_ID	0x17
   30.89 +
   30.90 +#define MSR_IA32_PERFCTR0      0xc1
   30.91 +#define MSR_IA32_PERFCTR1      0xc2
   30.92 +
   30.93 +#define MSR_MTRRcap		0x0fe
   30.94 +#define MSR_IA32_BBL_CR_CTL        0x119
   30.95  
   30.96 -#define MSR_IA32_MCG_CAP		0x179
   30.97 -#define MSR_IA32_MCG_STATUS		0x17a
   30.98 -#define MSR_IA32_MCG_CTL		0x17b
   30.99 +#define MSR_IA32_MCG_CAP       0x179
  30.100 +#define MSR_IA32_MCG_STATUS        0x17a
  30.101 +#define MSR_IA32_MCG_CTL       0x17b
  30.102  
  30.103 -#define MSR_IA32_THERM_CONTROL		0x19a
  30.104 -#define MSR_IA32_THERM_INTERRUPT	0x19b
  30.105 -#define MSR_IA32_THERM_STATUS		0x19c
  30.106 -#define MSR_IA32_MISC_ENABLE		0x1a0
  30.107 +#define MSR_IA32_EVNTSEL0      0x186
  30.108 +#define MSR_IA32_EVNTSEL1      0x187
  30.109 +
  30.110 +#define MSR_IA32_DEBUGCTLMSR       0x1d9
  30.111 +#define MSR_IA32_LASTBRANCHFROMIP  0x1db
  30.112 +#define MSR_IA32_LASTBRANCHTOIP        0x1dc
  30.113 +#define MSR_IA32_LASTINTFROMIP     0x1dd
  30.114 +#define MSR_IA32_LASTINTTOIP       0x1de
  30.115  
  30.116 -#define MSR_IA32_DEBUGCTLMSR		0x1d9
  30.117 -#define MSR_IA32_LASTBRANCHFROMIP	0x1db
  30.118 -#define MSR_IA32_LASTBRANCHTOIP		0x1dc
  30.119 -#define MSR_IA32_LASTINTFROMIP		0x1dd
  30.120 -#define MSR_IA32_LASTINTTOIP		0x1de
  30.121 +#define MSR_MTRRfix64K_00000	0x250
  30.122 +#define MSR_MTRRfix16K_80000	0x258
  30.123 +#define MSR_MTRRfix16K_A0000	0x259
  30.124 +#define MSR_MTRRfix4K_C0000	0x268
  30.125 +#define MSR_MTRRfix4K_C8000	0x269
  30.126 +#define MSR_MTRRfix4K_D0000	0x26a
  30.127 +#define MSR_MTRRfix4K_D8000	0x26b
  30.128 +#define MSR_MTRRfix4K_E0000	0x26c
  30.129 +#define MSR_MTRRfix4K_E8000	0x26d
  30.130 +#define MSR_MTRRfix4K_F0000	0x26e
  30.131 +#define MSR_MTRRfix4K_F8000	0x26f
  30.132 +#define MSR_MTRRdefType		0x2ff
  30.133  
  30.134 -#define MSR_IA32_MC0_CTL		0x400
  30.135 -#define MSR_IA32_MC0_STATUS		0x401
  30.136 -#define MSR_IA32_MC0_ADDR		0x402
  30.137 -#define MSR_IA32_MC0_MISC		0x403
  30.138 +#define MSR_IA32_MC0_CTL       0x400
  30.139 +#define MSR_IA32_MC0_STATUS        0x401
  30.140 +#define MSR_IA32_MC0_ADDR      0x402
  30.141 +#define MSR_IA32_MC0_MISC      0x403
  30.142  
  30.143  #define MSR_P6_PERFCTR0			0xc1
  30.144  #define MSR_P6_PERFCTR1			0xc2
  30.145  #define MSR_P6_EVNTSEL0			0x186
  30.146  #define MSR_P6_EVNTSEL1			0x187
  30.147  
  30.148 -/* AMD Defined MSRs */
  30.149 +/* K7/K8 MSRs. Not complete. See the architecture manual for a more complete list. */
  30.150 +#define MSR_K7_EVNTSEL0            0xC0010000
  30.151 +#define MSR_K7_PERFCTR0            0xC0010004
  30.152 +#define MSR_K7_EVNTSEL1            0xC0010001
  30.153 +#define MSR_K7_PERFCTR1            0xC0010005
  30.154 +#define MSR_K7_EVNTSEL2            0xC0010002
  30.155 +#define MSR_K7_PERFCTR2            0xC0010006
  30.156 +#define MSR_K7_EVNTSEL3            0xC0010003
  30.157 +#define MSR_K7_PERFCTR3            0xC0010007
  30.158 +#define MSR_K8_TOP_MEM1		   0xC001001A
  30.159 +#define MSR_K8_TOP_MEM2		   0xC001001D
  30.160 +#define MSR_K8_SYSCFG		   0xC0000010	
  30.161 +
  30.162 +/* K6 MSRs */
  30.163  #define MSR_K6_EFER			0xC0000080
  30.164  #define MSR_K6_STAR			0xC0000081
  30.165  #define MSR_K6_WHCR			0xC0000082
  30.166  #define MSR_K6_UWCCR			0xC0000085
  30.167 -#define MSR_K6_EPMR			0xC0000086
  30.168  #define MSR_K6_PSOR			0xC0000087
  30.169  #define MSR_K6_PFIR			0xC0000088
  30.170  
  30.171 -#define MSR_K7_EVNTSEL0			0xC0010000
  30.172 -#define MSR_K7_PERFCTR0			0xC0010004
  30.173 -#define MSR_K7_HWCR			0xC0010015
  30.174 -#define MSR_K7_CLK_CTL			0xC001001b
  30.175 -#define MSR_K7_FID_VID_CTL		0xC0010041
  30.176 -#define MSR_K7_VID_STATUS		0xC0010042
  30.177 -
  30.178  /* Centaur-Hauls/IDT defined MSRs. */
  30.179  #define MSR_IDT_FCR1			0x107
  30.180  #define MSR_IDT_FCR2			0x108
  30.181 @@ -109,13 +151,16 @@
  30.182  
  30.183  /* VIA Cyrix defined MSRs*/
  30.184  #define MSR_VIA_FCR			0x1107
  30.185 -#define MSR_VIA_LONGHAUL		0x110a
  30.186 -#define MSR_VIA_BCR2			0x1147
  30.187 +
  30.188 +/* Intel defined MSRs. */
  30.189 +#define MSR_IA32_P5_MC_ADDR		0
  30.190 +#define MSR_IA32_P5_MC_TYPE		1
  30.191 +#define MSR_IA32_PLATFORM_ID		0x17
  30.192 +#define MSR_IA32_EBL_CR_POWERON		0x2a
  30.193  
  30.194 -/* Transmeta defined MSRs */
  30.195 -#define MSR_TMTA_LONGRUN_CTRL		0x80868010
  30.196 -#define MSR_TMTA_LONGRUN_FLAGS		0x80868011
  30.197 -#define MSR_TMTA_LRTI_READOUT		0x80868018
  30.198 -#define MSR_TMTA_LRTI_VOLT_MHZ		0x8086801a
  30.199 +#define MSR_IA32_APICBASE               0x1b
  30.200 +#define MSR_IA32_APICBASE_BSP           (1<<8)
  30.201 +#define MSR_IA32_APICBASE_ENABLE        (1<<11)
  30.202 +#define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
  30.203  
  30.204 -#endif /* __ASM_MSR_H */
  30.205 +#endif
    31.1 --- a/xen/include/asm-x86_64/page.h	Wed Mar 10 13:44:42 2004 +0000
    31.2 +++ b/xen/include/asm-x86_64/page.h	Wed Mar 10 13:46:20 2004 +0000
    31.3 @@ -1,20 +1,47 @@
    31.4 -#ifndef _I386_PAGE_H
    31.5 -#define _I386_PAGE_H
    31.6 +#ifndef _X86_64_PAGE_H
    31.7 +#define _X86_64_PAGE_H
    31.8  
    31.9  #define BUG() do {					\
   31.10  	printk("BUG at %s:%d\n", __FILE__, __LINE__);	\
   31.11  	__asm__ __volatile__("ud2");			\
   31.12  } while (0)
   31.13 + 
   31.14 +#define __PHYSICAL_MASK       0x0000ffffffffffffUL
   31.15 +#define PHYSICAL_PAGE_MASK    0x0000fffffffff000UL
   31.16 +#define PTE_MASK	PHYSICAL_PAGE_MASK
   31.17 +
   31.18 +/* PAGE_SHIFT determines the page size */
   31.19 +#define PAGE_SHIFT	12
   31.20 +#ifdef __ASSEMBLY__
   31.21 +#define PAGE_SIZE	(0x1 << PAGE_SHIFT)
   31.22 +#else
   31.23 +#define PAGE_SIZE	(1UL << PAGE_SHIFT)
   31.24 +#endif
   31.25 +#define PAGE_MASK	(~(PAGE_SIZE-1))
   31.26 +#define LARGE_PAGE_MASK (~(LARGE_PAGE_SIZE-1))
   31.27 +#define LARGE_PAGE_SIZE (1UL << PMD_SHIFT)
   31.28  
   31.29  #define L1_PAGETABLE_SHIFT       12
   31.30 -#define L2_PAGETABLE_SHIFT       22
   31.31 +#define L2_PAGETABLE_SHIFT       21
   31.32 +#define L3_PAGETABLE_SHIFT	 30
   31.33 +#define L4_PAGETABLE_SHIFT	 39
   31.34 +#define LARGE_PFN	(LARGE_PAGE_SIZE / PAGE_SIZE)
   31.35 +
   31.36 +#define ENTRIES_PER_L1_PAGETABLE 512 
   31.37 +#define ENTRIES_PER_L2_PAGETABLE 512 
   31.38 +#define ENTRIES_PER_L3_PAGETABLE 512
   31.39 +#define ENTRIES_PER_L4_PAGETABLE 512
   31.40  
   31.41 -#define ENTRIES_PER_L1_PAGETABLE 1024
   31.42 -#define ENTRIES_PER_L2_PAGETABLE 1024
   31.43 +#define KERNEL_TEXT_SIZE  (40UL*1024*1024)
   31.44 +#define KERNEL_TEXT_START 0xffffffff80000000UL 
   31.45  
   31.46 -#define PAGE_SHIFT               L1_PAGETABLE_SHIFT
   31.47 -#define PAGE_SIZE	         (1UL << PAGE_SHIFT)
   31.48 -#define PAGE_MASK	         (~(PAGE_SIZE-1))
   31.49 +/* Changing the next two defines should be enough to increase the kernel stack */
   31.50 +/* We still hope 8K is enough, but ... */
   31.51 +#define THREAD_ORDER    1
   31.52 +#define THREAD_SIZE    (2*PAGE_SIZE)
   31.53 +
   31.54 +#define INIT_TASK_SIZE THREAD_SIZE
   31.55 +#define CURRENT_MASK (~(THREAD_SIZE-1))
   31.56  
   31.57  #define clear_page(_p)           memset((void *)(_p), 0, PAGE_SIZE)
   31.58  #define copy_page(_t,_f)         memcpy((void *)(_t), (void *)(_f), PAGE_SIZE)
   31.59 @@ -23,53 +50,84 @@
   31.60  #include <xeno/config.h>
   31.61  typedef struct { unsigned long l1_lo; } l1_pgentry_t;
   31.62  typedef struct { unsigned long l2_lo; } l2_pgentry_t;
   31.63 +typedef struct { unsigned long l3_lo; } l3_pgentry_t;
   31.64 +typedef struct { unsigned long l4_lo; } l4_pgentry_t;
   31.65  typedef l1_pgentry_t *l1_pagetable_t;
   31.66  typedef l2_pgentry_t *l2_pagetable_t;
   31.67 +typedef l3_pgentry_t *l3_pagetable_t;
   31.68 +typedef l4_pgentry_t *l4_pagetable_t;
   31.69  typedef struct { unsigned long pt_lo; } pagetable_t;
   31.70 +typedef struct { unsigned long pgprot; } pgprot_t;
   31.71  #endif /* !__ASSEMBLY__ */
   31.72  
   31.73  /* Strip type from a table entry. */
   31.74  #define l1_pgentry_val(_x) ((_x).l1_lo)
   31.75  #define l2_pgentry_val(_x) ((_x).l2_lo)
   31.76 +#define l3_pgentry_val(_x) ((_x).l3_lo)
   31.77 +#define l4_pgentry_val(_x) ((_x).l4_lo)
   31.78  #define pagetable_val(_x)  ((_x).pt_lo)
   31.79  
   31.80  #define alloc_l1_pagetable()  ((l1_pgentry_t *)get_free_page(GFP_KERNEL))
   31.81  #define alloc_l2_pagetable()  ((l2_pgentry_t *)get_free_page(GFP_KERNEL))
   31.82 +#define alloc_l3_pagetable()  ((l3_pgentry_t *)get_free_page(GFP_KERNEL))
   31.83 +#define alloc_l4_pagetable()  ((l4_pgentry_t *)get_free_page(GFP_KERNEL))
   31.84  
   31.85  /* Add type to a table entry. */
   31.86  #define mk_l1_pgentry(_x)  ( (l1_pgentry_t) { (_x) } )
   31.87  #define mk_l2_pgentry(_x)  ( (l2_pgentry_t) { (_x) } )
   31.88 +#define mk_l3_pgentry(_x)  ( (l3_pgentry_t) { (_x) } )
   31.89 +#define mk_l4_pgentry(_x)  ( (l4_pgentry_t) { (_x) } )
   31.90  #define mk_pagetable(_x)   ( (pagetable_t) { (_x) } )
   31.91  
   31.92  /* Turn a typed table entry into a page index. */
   31.93  #define l1_pgentry_to_pagenr(_x) (l1_pgentry_val(_x) >> PAGE_SHIFT) 
   31.94  #define l2_pgentry_to_pagenr(_x) (l2_pgentry_val(_x) >> PAGE_SHIFT)
   31.95 +#define l3_pgentry_to_pagenr(_x) (l3_pgentry_val(_x) >> PAGE_SHIFT) 
   31.96 +#define l4_pgentry_to_pagenr(_x) (l4_pgentry_val(_x) >> PAGE_SHIFT)
   31.97  
   31.98  /* Turn a typed table entry into a physical address. */
   31.99  #define l1_pgentry_to_phys(_x) (l1_pgentry_val(_x) & PAGE_MASK)
  31.100  #define l2_pgentry_to_phys(_x) (l2_pgentry_val(_x) & PAGE_MASK)
  31.101 +#define l3_pgentry_to_phys(_x) (l3_pgentry_val(_x) & PAGE_MASK)
  31.102 +#define l4_pgentry_to_phys(_x) (l4_pgentry_val(_x) & PAGE_MASK)
  31.103  
  31.104  /* Dereference a typed level-2 entry to yield a typed level-1 table. */
  31.105  #define l2_pgentry_to_l1(_x)     \
  31.106    ((l1_pgentry_t *)__va(l2_pgentry_val(_x) & PAGE_MASK))
  31.107  
  31.108 +/* Dereference a typed level-4 entry to yield a typed level-3 table. */
  31.109 +#define l4_pgentry_to_l3(_x)     \
  31.110 +  ((l3_pgentry_t *)__va(l4_pgentry_val(_x) & PAGE_MASK))
  31.111 +
  31.112 +/* Dereference a typed level-3 entry to yield a typed level-2 table. */
  31.113 +#define l3_pgentry_to_l2(_x)     \
  31.114 +  ((l2_pgentry_t *)__va(l3_pgentry_val(_x) & PAGE_MASK))
  31.115 +
  31.116  /* Given a virtual address, get an entry offset into a page table. */
  31.117  #define l1_table_offset(_a) \
  31.118    (((_a) >> L1_PAGETABLE_SHIFT) & (ENTRIES_PER_L1_PAGETABLE - 1))
  31.119  #define l2_table_offset(_a) \
  31.120 -  ((_a) >> L2_PAGETABLE_SHIFT)
  31.121 +  (((_a) >> L2_PAGETABLE_SHIFT) & (ENTRIES_PER_L2_PAGETABLE - 1))
  31.122 +#define l3_table_offset(_a) \
  31.123 +  (((_a) >> L3_PAGETABLE_SHIFT) & (ENTRIES_PER_L3_PAGETABLE - 1))
  31.124 +#define l4_table_offset(_a) \
  31.125 +  ((_a) >> L4_PAGETABLE_SHIFT)
  31.126  
  31.127  /* Hypervisor table entries use zero to sugnify 'empty'. */
  31.128  #define l1_pgentry_empty(_x) (!l1_pgentry_val(_x))
  31.129  #define l2_pgentry_empty(_x) (!l2_pgentry_val(_x))
  31.130 +#define l3_pgentry_empty(_x) (!l3_pgentry_val(_x))
  31.131 +#define l4_pgentry_empty(_x) (!l4_pgentry_val(_x))
  31.132  
  31.133 -#define __PAGE_OFFSET		(0xFC400000)
  31.134 -#define PAGE_OFFSET		((unsigned long)__PAGE_OFFSET)
  31.135 -#define __pa(x)			((unsigned long)(x)-PAGE_OFFSET)
  31.136 -#define __va(x)			((void *)((unsigned long)(x)+PAGE_OFFSET))
  31.137 -#define page_address(_p)        (__va(((_p) - frame_table) << PAGE_SHIFT))
  31.138 -#define virt_to_page(kaddr)	(frame_table + (__pa(kaddr) >> PAGE_SHIFT))
  31.139 -#define VALID_PAGE(page)	((page - frame_table) < max_mapnr)
  31.140 +
  31.141 +#define pgprot_val(x)	((x).pgprot)
  31.142 +#define __pgprot(x)	((pgprot_t) { (x) } )
  31.143 + 
  31.144 +#define clear_user_page(page, vaddr)	clear_page(page)
  31.145 +#define copy_user_page(to, from, vaddr)	copy_page(to, from)
  31.146 +
  31.147 +/* to align the pointer to the (next) page boundary */
  31.148 +#define PAGE_ALIGN(addr)	(((addr)+PAGE_SIZE-1)&PAGE_MASK)
  31.149  
  31.150  /*
  31.151   * NB. We don't currently track I/O holes in the physical RAM space.
  31.152 @@ -79,10 +137,15 @@ typedef struct { unsigned long pt_lo; } 
  31.153  #define pfn_is_ram(_pfn)        (((_pfn) > 0x100) && ((_pfn) < max_page))
  31.154  
  31.155  /* High table entries are reserved by the hypervisor. */
  31.156 -#define DOMAIN_ENTRIES_PER_L2_PAGETABLE	    \
  31.157 -  (HYPERVISOR_VIRT_START >> L2_PAGETABLE_SHIFT)
  31.158 -#define HYPERVISOR_ENTRIES_PER_L2_PAGETABLE \
  31.159 -  (ENTRIES_PER_L2_PAGETABLE - DOMAIN_ENTRIES_PER_L2_PAGETABLE)
  31.160 +#define DOMAIN_ENTRIES_PER_L4_PAGETABLE	    \
  31.161 +  (HYPERVISOR_VIRT_START >> L4_PAGETABLE_SHIFT)
  31.162 +#define HYPERVISOR_ENTRIES_PER_L4_PAGETABLE \
  31.163 +  (ENTRIES_PER_L4_PAGETABLE - DOMAIN_ENTRIES_PER_L4_PAGETABLE)
  31.164 +
  31.165 +#define __START_KERNEL		0xffffffff80100000
  31.166 +#define __START_KERNEL_map	0xffffffff80000000
  31.167 +#define __PAGE_OFFSET           0x0000010000000000
  31.168 +#define PAGE_OFFSET		((unsigned long)__PAGE_OFFSET)
  31.169  
  31.170  #ifndef __ASSEMBLY__
  31.171  #include <asm/processor.h>
  31.172 @@ -90,6 +153,10 @@ typedef struct { unsigned long pt_lo; } 
  31.173  #include <asm/bitops.h>
  31.174  #include <asm/flushtlb.h>
  31.175  
  31.176 +extern unsigned long vm_stack_flags, vm_stack_flags32;
  31.177 +extern unsigned long vm_data_default_flags, vm_data_default_flags32;
  31.178 +extern unsigned long vm_force_exec32;
  31.179 +
  31.180  #define linear_pg_table ((l1_pgentry_t *)LINEAR_PT_VIRT_START)
  31.181  
  31.182  extern l2_pgentry_t idle_pg_table[ENTRIES_PER_L2_PAGETABLE];
  31.183 @@ -124,8 +191,21 @@ extern void paging_init(void);
  31.184  #define __flush_tlb_one(__addr) \
  31.185  __asm__ __volatile__("invlpg %0": :"m" (*(char *) (__addr)))
  31.186  
  31.187 -#endif /* !__ASSEMBLY__ */
  31.188 +#include <linux/config.h>
  31.189  
  31.190 +/*
  31.191 + * Tell the user there is some problem.  The exception handler decodes this frame.
  31.192 + */
  31.193 +struct bug_frame { 
  31.194 +       unsigned char ud2[2];          
  31.195 +       char *filename;    /* should use 32bit offset instead, but the assembler doesn't like it */ 
  31.196 +       unsigned short line; 
  31.197 +} __attribute__((packed)); 
  31.198 +#define HEADER_BUG() asm volatile("ud2 ; .quad %P1 ; .short %P0" :: "i"(__LINE__), \
  31.199 +		"i" (__stringify(__FILE__)))
  31.200 +#define PAGE_BUG(page) BUG()
  31.201 +
  31.202 +#endif /* ASSEMBLY */
  31.203  
  31.204  #define _PAGE_PRESENT	0x001
  31.205  #define _PAGE_RW	0x002
  31.206 @@ -151,6 +231,14 @@ extern void paging_init(void);
  31.207  #define PAGE_HYPERVISOR_RO MAKE_GLOBAL(__PAGE_HYPERVISOR_RO)
  31.208  #define PAGE_HYPERVISOR_NOCACHE MAKE_GLOBAL(__PAGE_HYPERVISOR_NOCACHE)
  31.209  
  31.210 +#define mk_l4_writeable(_p) \
  31.211 +    (*(_p) = mk_l4_pgentry(l4_pgentry_val(*(_p)) |  _PAGE_RW))
  31.212 +#define mk_l4_readonly(_p) \
  31.213 +    (*(_p) = mk_l4_pgentry(l4_pgentry_val(*(_p)) & ~_PAGE_RW))
  31.214 +#define mk_l3_writeable(_p) \
  31.215 +    (*(_p) = mk_l3_pgentry(l3_pgentry_val(*(_p)) |  _PAGE_RW))
  31.216 +#define mk_l3_readonly(_p) \
  31.217 +    (*(_p) = mk_l3_pgentry(l3_pgentry_val(*(_p)) & ~_PAGE_RW))
  31.218  #define mk_l2_writeable(_p) \
  31.219      (*(_p) = mk_l2_pgentry(l2_pgentry_val(*(_p)) |  _PAGE_RW))
  31.220  #define mk_l2_readonly(_p) \
  31.221 @@ -160,6 +248,27 @@ extern void paging_init(void);
  31.222  #define mk_l1_readonly(_p) \
  31.223      (*(_p) = mk_l1_pgentry(l1_pgentry_val(*(_p)) & ~_PAGE_RW))
  31.224  
  31.225 +/* Note: __pa(&symbol_visible_to_c) should be always replaced with __pa_symbol.
  31.226 +   Otherwise you risk miscompilation. */ 
  31.227 +#define __pa(x)			(((unsigned long)(x)>=__START_KERNEL_map)?(unsigned long)(x) - (unsigned long)__START_KERNEL_map:(unsigned long)(x) - PAGE_OFFSET)
  31.228 +/* __pa_symbol should use for C visible symbols, but only for them. 
  31.229 +   This seems to be the official gcc blessed way to do such arithmetic. */ 
  31.230 +#define __pa_symbol(x)		\
  31.231 +	({unsigned long v;  \
  31.232 +	  asm("" : "=r" (v) : "0" (x)); \
  31.233 +	 v - __START_KERNEL_map; })
  31.234 +#define __pa_maybe_symbol(x)		\
  31.235 +	({unsigned long v;  \
  31.236 +	  asm("" : "=r" (v) : "0" (x)); \
  31.237 +	  __pa(v); })
  31.238 +#define __va(x)			((void *)((unsigned long)(x)+PAGE_OFFSET))
  31.239 +#ifndef CONFIG_DISCONTIGMEM
  31.240 +#define virt_to_page(kaddr)	(frame_table + (__pa(kaddr) >> PAGE_SHIFT))
  31.241 +#define pfn_to_page(pfn)	(frame_table + (pfn)) 
  31.242 +#define page_to_pfn(page)   ((page) - frame_table)
  31.243 +#define page_address(_p)        (__va(((_p) - frame_table) << PAGE_SHIFT))
  31.244 +#define VALID_PAGE(page)	(((page) - frame_table) < max_mapnr)
  31.245 +#endif
  31.246  
  31.247  #ifndef __ASSEMBLY__
  31.248  static __inline__ int get_order(unsigned long size)
  31.249 @@ -176,4 +285,16 @@ static __inline__ int get_order(unsigned
  31.250  }
  31.251  #endif
  31.252  
  31.253 -#endif /* _I386_PAGE_H */
  31.254 +#define phys_to_pfn(phys)	((phys) >> PAGE_SHIFT)
  31.255 +
  31.256 +#define __VM_DATA_DEFAULT_FLAGS	(VM_READ | VM_WRITE | VM_EXEC | \
  31.257 +				 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
  31.258 +#define __VM_STACK_FLAGS 	(VM_GROWSDOWN | VM_READ | VM_WRITE | VM_EXEC | \
  31.259 +				 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
  31.260 +
  31.261 +#define VM_DATA_DEFAULT_FLAGS \
  31.262 +	((current->thread.flags & THREAD_IA32) ? vm_data_default_flags32 : \
  31.263 +	  vm_data_default_flags) 
  31.264 +#define VM_STACK_FLAGS	vm_stack_flags
  31.265 +
  31.266 +#endif /* _X86_64_PAGE_H */
    32.1 --- a/xen/include/asm-x86_64/param.h	Wed Mar 10 13:44:42 2004 +0000
    32.2 +++ b/xen/include/asm-x86_64/param.h	Wed Mar 10 13:46:20 2004 +0000
    32.3 @@ -1,5 +1,5 @@
    32.4 -#ifndef _ASMi386_PARAM_H
    32.5 -#define _ASMi386_PARAM_H
    32.6 +#ifndef _ASMx86_64_PARAM_H
    32.7 +#define _ASMx86_64_PARAM_H
    32.8  
    32.9  #ifndef HZ
   32.10  #define HZ 100
    33.1 --- a/xen/include/asm-x86_64/pci.h	Wed Mar 10 13:44:42 2004 +0000
    33.2 +++ b/xen/include/asm-x86_64/pci.h	Wed Mar 10 13:46:20 2004 +0000
    33.3 @@ -1,9 +1,9 @@
    33.4 -#ifndef __i386_PCI_H
    33.5 -#define __i386_PCI_H
    33.6 +#ifndef __x8664_PCI_H
    33.7 +#define __x8664_PCI_H
    33.8  
    33.9  #include <linux/config.h>
   33.10 +#include <asm/io.h>
   33.11  
   33.12 -#ifdef __KERNEL__
   33.13  
   33.14  /* Can be used to override the logic in pci_scan_bus for skipping
   33.15     already-configured bus numbers - to be used for buggy BIOSes
   33.16 @@ -24,23 +24,16 @@ void pcibios_penalize_isa_irq(int irq);
   33.17  struct irq_routing_table *pcibios_get_irq_routing_table(void);
   33.18  int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq);
   33.19  
   33.20 -/* Dynamic DMA mapping stuff.
   33.21 - * i386 has everything mapped statically.
   33.22 - */
   33.23 -
   33.24  #include <linux/types.h>
   33.25  #include <linux/slab.h>
   33.26  #include <asm/scatterlist.h>
   33.27  /*#include <linux/string.h>*/
   33.28  #include <asm/io.h>
   33.29 +#include <asm/page.h>
   33.30 +#include <asm/mmzone.h>
   33.31  
   33.32  struct pci_dev;
   33.33 -
   33.34 -/* The PCI address space does equal the physical memory
   33.35 - * address space.  The networking and block device layers use
   33.36 - * this boolean for bounce buffer decisions.
   33.37 - */
   33.38 -#define PCI_DMA_BUS_IS_PHYS	(1)
   33.39 +extern int force_mmu;
   33.40  
   33.41  /* Allocate and map kernel buffer using consistent mode DMA for a device.
   33.42   * hwdev should be valid struct pci_dev pointer for PCI devices,
   33.43 @@ -63,28 +56,82 @@ extern void *pci_alloc_consistent(struct
   33.44  extern void pci_free_consistent(struct pci_dev *hwdev, size_t size,
   33.45  				void *vaddr, dma_addr_t dma_handle);
   33.46  
   33.47 +#ifdef CONFIG_GART_IOMMU
   33.48 +
   33.49  /* Map a single buffer of the indicated size for DMA in streaming mode.
   33.50   * The 32-bit bus address to use is returned.
   33.51   *
   33.52   * Once the device is given the dma address, the device owns this memory
   33.53   * until either pci_unmap_single or pci_dma_sync_single is performed.
   33.54   */
   33.55 +extern dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr,
   33.56 +				 size_t size, int direction);
   33.57 +
   33.58 +
   33.59 +void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t addr,
   33.60 +				   size_t size, int direction);
   33.61 +
   33.62 +/*
   33.63 + * pci_{map,unmap}_single_page maps a kernel page to a dma_addr_t. identical
   33.64 + * to pci_map_single, but takes a struct pfn_info instead of a virtual address
   33.65 + */
   33.66 +
   33.67 +#define pci_map_page(dev,page,offset,size,dir) \
   33.68 +	pci_map_single((dev), page_address(page)+(offset), (size), (dir)) 
   33.69 +
   33.70 +#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)	\
   33.71 +	dma_addr_t ADDR_NAME;
   33.72 +#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)		\
   33.73 +	__u32 LEN_NAME;
   33.74 +#define pci_unmap_addr(PTR, ADDR_NAME)			\
   33.75 +	((PTR)->ADDR_NAME)
   33.76 +#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)		\
   33.77 +	(((PTR)->ADDR_NAME) = (VAL))
   33.78 +#define pci_unmap_len(PTR, LEN_NAME)			\
   33.79 +	((PTR)->LEN_NAME)
   33.80 +#define pci_unmap_len_set(PTR, LEN_NAME, VAL)		\
   33.81 +	(((PTR)->LEN_NAME) = (VAL))
   33.82 +
   33.83 +static inline void pci_dma_sync_single(struct pci_dev *hwdev, 
   33.84 +				       dma_addr_t dma_handle,
   33.85 +				       size_t size, int direction)
   33.86 +{
   33.87 +	BUG_ON(direction == PCI_DMA_NONE); 
   33.88 +} 
   33.89 +
   33.90 +static inline void pci_dma_sync_sg(struct pci_dev *hwdev, 
   33.91 +				   struct scatterlist *sg,
   33.92 +				   int nelems, int direction)
   33.93 +{ 
   33.94 +	BUG_ON(direction == PCI_DMA_NONE); 
   33.95 +} 
   33.96 +
   33.97 +/* The PCI address space does equal the physical memory
   33.98 + * address space.  The networking and block device layers use
   33.99 + * this boolean for bounce buffer decisions.
  33.100 + */
  33.101 +#define PCI_DMA_BUS_IS_PHYS	(0)
  33.102 +
  33.103 +
  33.104 +#else
  33.105  static inline dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr,
  33.106  					size_t size, int direction)
  33.107  {
  33.108 +	dma_addr_t addr; 
  33.109 +
  33.110  	if (direction == PCI_DMA_NONE)
  33.111 -		out_of_line_bug();
  33.112 -	flush_write_buffers();
  33.113 -	return virt_to_bus(ptr);
  33.114 +		out_of_line_bug();	
  33.115 +	addr = virt_to_bus(ptr); 
  33.116 +
  33.117 +	/* 
  33.118 +	 * This is gross, but what should I do.
  33.119 +	 * Unfortunately drivers do not test the return value of this.
  33.120 +	 */
  33.121 +	if ((addr+size) & ~hwdev->dma_mask) 
  33.122 +		out_of_line_bug(); 
  33.123 +	return addr;
  33.124  }
  33.125  
  33.126 -/* Unmap a single streaming mode DMA translation.  The dma_addr and size
  33.127 - * must match what was provided for in a previous pci_map_single call.  All
  33.128 - * other usages are undefined.
  33.129 - *
  33.130 - * After this call, reads by the cpu to the buffer are guarenteed to see
  33.131 - * whatever the device wrote there.
  33.132 - */
  33.133  static inline void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr,
  33.134  				    size_t size, int direction)
  33.135  {
  33.136 @@ -93,25 +140,16 @@ static inline void pci_unmap_single(stru
  33.137  	/* Nothing to do */
  33.138  }
  33.139  
  33.140 -/*
  33.141 - * pci_{map,unmap}_single_page maps a kernel page to a dma_addr_t. identical
  33.142 - * to pci_map_single, but takes a struct pfn_info instead of a virtual address
  33.143 - */
  33.144  static inline dma_addr_t pci_map_page(struct pci_dev *hwdev, struct pfn_info *page,
  33.145  				      unsigned long offset, size_t size, int direction)
  33.146  {
  33.147 +	dma_addr_t addr;
  33.148  	if (direction == PCI_DMA_NONE)
  33.149 +		out_of_line_bug();	
  33.150 + 	addr = (page - frame_table) * PAGE_SIZE + offset;
  33.151 +	if ((addr+size) & ~hwdev->dma_mask) 
  33.152  		out_of_line_bug();
  33.153 -
  33.154 -	return (dma_addr_t)(page - frame_table) * PAGE_SIZE + offset;
  33.155 -}
  33.156 -
  33.157 -static inline void pci_unmap_page(struct pci_dev *hwdev, dma_addr_t dma_address,
  33.158 -				  size_t size, int direction)
  33.159 -{
  33.160 -	if (direction == PCI_DMA_NONE)
  33.161 -		out_of_line_bug();
  33.162 -	/* Nothing to do */
  33.163 +	return addr;
  33.164  }
  33.165  
  33.166  /* pci_unmap_{page,single} is a nop so... */
  33.167 @@ -122,6 +160,8 @@ static inline void pci_unmap_page(struct
  33.168  #define pci_unmap_len(PTR, LEN_NAME)		(0)
  33.169  #define pci_unmap_len_set(PTR, LEN_NAME, VAL)	do { } while (0)
  33.170  
  33.171 +#define BAD_DMA_ADDRESS (-1UL)
  33.172 +
  33.173  /* Map a set of buffers described by scatterlist in streaming
  33.174   * mode for DMA.  This is the scather-gather version of the
  33.175   * above pci_map_single interface.  Here the scatter gather list
  33.176 @@ -141,45 +181,47 @@ static inline int pci_map_sg(struct pci_
  33.177  			     int nents, int direction)
  33.178  {
  33.179  	int i;
  33.180 -
  33.181 -	if (direction == PCI_DMA_NONE)
  33.182 -		out_of_line_bug();
  33.183 - 
  33.184 - 	/*
  33.185 - 	 * temporary 2.4 hack
  33.186 - 	 */
  33.187 - 	for (i = 0; i < nents; i++ ) {
  33.188 - 		if (sg[i].address && sg[i].page)
  33.189 - 			out_of_line_bug();
  33.190 +											   
  33.191 +	BUG_ON(direction == PCI_DMA_NONE);
  33.192 +											   
  33.193 +	/*
  33.194 +	 * temporary 2.4 hack
  33.195 +	 */
  33.196 +	for (i = 0; i < nents; i++ ) {
  33.197 +		struct scatterlist *s = &sg[i];
  33.198 +		void *addr = s->address;
  33.199 +		if (addr)
  33.200 +			BUG_ON(s->page || s->offset);
  33.201 +		else if (s->page)
  33.202 +			addr = page_address(s->page) + s->offset;
  33.203  #if 0
  33.204  		/* Invalid check, since address==0 is valid. */
  33.205 -		else if (!sg[i].address && !sg[i].page)
  33.206 - 			out_of_line_bug();
  33.207 +		else
  33.208 +			BUG();
  33.209  #endif
  33.210 - 
  33.211 -		/* XXX Switched round, since address==0 is valid. */
  33.212 - 		if (sg[i].page)
  33.213 - 			sg[i].dma_address = page_to_bus(sg[i].page) + sg[i].offset;
  33.214 - 		else
  33.215 - 			sg[i].dma_address = virt_to_bus(sg[i].address);
  33.216 - 	}
  33.217 - 
  33.218 -	flush_write_buffers();
  33.219 +		s->dma_address = pci_map_single(hwdev, addr, s->length, direction);
  33.220 +		if (unlikely(s->dma_address == BAD_DMA_ADDRESS))
  33.221 +			goto error;
  33.222 +	}
  33.223  	return nents;
  33.224 +											   
  33.225 + error:
  33.226 +	pci_unmap_sg(hwdev, sg, i, direction);
  33.227 +	return 0;
  33.228  }
  33.229 -
  33.230 +											   
  33.231  /* Unmap a set of streaming mode DMA translations.
  33.232   * Again, cpu read rules concerning calls here are the same as for
  33.233   * pci_unmap_single() above.
  33.234   */
  33.235 -static inline void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg,
  33.236 -				int nents, int direction)
  33.237 +static inline void pci_unmap_sg(struct pci_dev *dev, struct scatterlist *sg,
  33.238 +                                  int nents, int dir)
  33.239  {
  33.240  	if (direction == PCI_DMA_NONE)
  33.241  		out_of_line_bug();
  33.242 -	/* Nothing to do */
  33.243  }
  33.244  
  33.245 +	
  33.246  /* Make physical memory consistent for a single
  33.247   * streaming mode DMA translation after a transfer.
  33.248   *
  33.249 @@ -213,6 +255,17 @@ static inline void pci_dma_sync_sg(struc
  33.250  	flush_write_buffers();
  33.251  }
  33.252  
  33.253 +#define PCI_DMA_BUS_IS_PHYS	1
  33.254 +
  33.255 +#endif
  33.256 +
  33.257 +extern int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg,
  33.258 +		      int nents, int direction);
  33.259 +extern void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg,
  33.260 +			 int nents, int direction);
  33.261 +
  33.262 +#define pci_unmap_page pci_unmap_single
  33.263 +
  33.264  /* Return whether the given PCI device DMA address mask can
  33.265   * be supported properly.  For example, if your device can
  33.266   * only drive the low 24-bits during PCI bus mastering, then
  33.267 @@ -244,8 +297,6 @@ pci_dac_page_to_dma(struct pci_dev *pdev
  33.268  static __inline__ struct pfn_info *
  33.269  pci_dac_dma_to_page(struct pci_dev *pdev, dma64_addr_t dma_addr)
  33.270  {
  33.271 -	unsigned long poff = (dma_addr >> PAGE_SHIFT);
  33.272 -
  33.273  	return frame_table + poff;
  33.274  }
  33.275  
  33.276 @@ -281,6 +332,5 @@ extern int pci_mmap_page_range(struct pc
  33.277  			       enum pci_mmap_state mmap_state, int write_combine);
  33.278  #endif
  33.279  
  33.280 -#endif /* __KERNEL__ */
  33.281  
  33.282 -#endif /* __i386_PCI_H */
  33.283 +#endif /* __x8664_PCI_H */
    34.1 --- a/xen/include/asm-x86_64/pgalloc.h	Wed Mar 10 13:44:42 2004 +0000
    34.2 +++ b/xen/include/asm-x86_64/pgalloc.h	Wed Mar 10 13:46:20 2004 +0000
    34.3 @@ -1,38 +1,12 @@
    34.4 -#ifndef _I386_PGALLOC_H
    34.5 -#define _I386_PGALLOC_H
    34.6 +#ifndef _X86_64_PGALLOC_H
    34.7 +#define _X86_64_PGALLOC_H
    34.8  
    34.9  #include <xeno/config.h>
   34.10  #include <xeno/sched.h>
   34.11  #include <asm/processor.h>
   34.12  #include <asm/fixmap.h>
   34.13  
   34.14 -#define pgd_quicklist (current_cpu_data.pgd_quick)
   34.15 -#define pmd_quicklist (current_cpu_data.pmd_quick)
   34.16 -#define pte_quicklist (current_cpu_data.pte_quick)
   34.17 -#define pgtable_cache_size (current_cpu_data.pgtable_cache_sz)
   34.18 -
   34.19 -
   34.20 -/*
   34.21 - * Allocate and free page tables.
   34.22 - */
   34.23 -
   34.24 -
   34.25 -#define pte_free(pte)		pte_free_fast(pte)
   34.26 -#define pgd_alloc(mm)		get_pgd_fast()
   34.27 -#define pgd_free(pgd)		free_pgd_fast(pgd)
   34.28 -
   34.29 -/*
   34.30 - * allocating and freeing a pmd is trivial: the 1-entry pmd is
   34.31 - * inside the pgd, so has no extra memory associated with it.
   34.32 - * (In the PAE case we free the pmds as part of the pgd.)
   34.33 - */
   34.34 -
   34.35 -#define pmd_alloc_one_fast(mm, addr)	({ BUG(); ((pmd_t *)1); })
   34.36 -#define pmd_alloc_one(mm, addr)		({ BUG(); ((pmd_t *)2); })
   34.37 -#define pmd_free_slow(x)		do { } while (0)
   34.38 -#define pmd_free_fast(x)		do { } while (0)
   34.39 -#define pmd_free(x)			do { } while (0)
   34.40 -#define pgd_populate(mm, pmd, pte)	BUG()
   34.41 +/* XXX probably should be moved to flushtlb.h */
   34.42  
   34.43  /*
   34.44   * TLB flushing:
   34.45 @@ -40,9 +14,6 @@
   34.46   *  - flush_tlb() flushes the current mm struct TLBs
   34.47   *  - flush_tlb_all() flushes all processes TLBs
   34.48   *  - flush_tlb_pgtables(mm, start, end) flushes a range of page tables
   34.49 - *
   34.50 - * ..but the i386 has somewhat limited tlb flushing capabilities,
   34.51 - * and page-granular flushes are available only on i486 and up.
   34.52   */
   34.53  
   34.54  #ifndef CONFIG_SMP
   34.55 @@ -56,7 +27,6 @@
   34.56  #define try_flush_tlb_mask(_mask) __flush_tlb()
   34.57  
   34.58  #else
   34.59 -
   34.60  #include <xeno/smp.h>
   34.61  
   34.62  extern int try_flush_tlb_mask(unsigned long mask);
   34.63 @@ -70,10 +40,4 @@ extern void flush_tlb_all_pge(void);
   34.64  
   34.65  #endif
   34.66  
   34.67 -static inline void flush_tlb_pgtables(struct mm_struct *mm,
   34.68 -				      unsigned long start, unsigned long end)
   34.69 -{
   34.70 -	/* i386 does not keep any page table caches in TLB */
   34.71 -}
   34.72 -
   34.73 -#endif /* _I386_PGALLOC_H */
   34.74 +#endif /* _X86_64_PGALLOC_H */
    35.1 --- a/xen/include/asm-x86_64/processor.h	Wed Mar 10 13:44:42 2004 +0000
    35.2 +++ b/xen/include/asm-x86_64/processor.h	Wed Mar 10 13:46:20 2004 +0000
    35.3 @@ -1,11 +1,11 @@
    35.4  /*
    35.5 - * include/asm-i386/processor.h
    35.6 + * include/asm-x86_64/processor.h
    35.7   *
    35.8   * Copyright (C) 1994 Linus Torvalds
    35.9   */
   35.10  
   35.11 -#ifndef __ASM_I386_PROCESSOR_H
   35.12 -#define __ASM_I386_PROCESSOR_H
   35.13 +#ifndef __ASM_X86_64_PROCESSOR_H
   35.14 +#define __ASM_X86_64_PROCESSOR_H
   35.15  
   35.16  #include <asm/page.h>
   35.17  #include <asm/types.h>
   35.18 @@ -16,12 +16,21 @@
   35.19  
   35.20  struct task_struct;
   35.21  
   35.22 +#define TF_MASK		0x00000100
   35.23 +#define IF_MASK		0x00000200
   35.24 +#define IOPL_MASK	0x00003000
   35.25 +#define NT_MASK		0x00004000
   35.26 +#define VM_MASK		0x00020000
   35.27 +#define AC_MASK		0x00040000
   35.28 +#define VIF_MASK	0x00080000	/* virtual interrupt flag */
   35.29 +#define VIP_MASK	0x00100000	/* virtual interrupt pending */
   35.30 +#define ID_MASK		0x00200000
   35.31 +
   35.32  /*
   35.33   * Default implementation of macro that returns current
   35.34   * instruction pointer ("program counter").
   35.35   */
   35.36 -#define current_text_addr() \
   35.37 -  ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
   35.38 +#define current_text_addr() ({ void *pc; asm volatile("leaq 1f(%%rip),%0\n1:":"=r"(pc)); pc; })
   35.39  
   35.40  /*
   35.41   *  CPU type and hardware bug flags. Kept separately for each CPU.
   35.42 @@ -30,18 +39,22 @@ struct task_struct;
   35.43   */
   35.44  
   35.45  struct cpuinfo_x86 {
   35.46 -    __u8	x86;		/* CPU family */
   35.47 -    __u8	x86_vendor;	/* CPU vendor */
   35.48 -    __u8	x86_model;
   35.49 -    __u8	x86_mask;
   35.50 -    int	cpuid_level;	/* Maximum supported CPUID level, -1=no CPUID */
   35.51 -    __u32	x86_capability[NCAPINTS];
   35.52 -    char    x86_vendor_id[16];
   35.53 -    unsigned long *pgd_quick;
   35.54 -    unsigned long *pmd_quick;
   35.55 -    unsigned long *pte_quick;
   35.56 -    unsigned long pgtable_cache_sz;
   35.57 -} __attribute__((__aligned__(SMP_CACHE_BYTES)));
   35.58 +	__u8	x86;		/* CPU family */
   35.59 +	__u8	x86_vendor;	/* CPU vendor */
   35.60 +	__u8	x86_model;
   35.61 +	__u8	x86_mask;
   35.62 +	int	cpuid_level;	/* Maximum supported CPUID level, -1=no CPUID */
   35.63 +	__u32	x86_capability[NCAPINTS];
   35.64 +	char	x86_vendor_id[16];
   35.65 +	char	x86_model_id[64];
   35.66 +	int 	x86_cache_size;  /* in KB - valid for CPUS which support this
   35.67 +				    call  */
   35.68 +	int	x86_clflush_size;
   35.69 +	int	x86_tlbsize;	/* number of 4K pages in DTLB/ITLB combined(in pages)*/
   35.70 +        __u8    x86_virt_bits, x86_phys_bits;
   35.71 +        __u32   x86_power; 
   35.72 +	unsigned long loops_per_jiffy;
   35.73 +} ____cacheline_aligned;
   35.74  
   35.75  #define X86_VENDOR_INTEL 0
   35.76  #define X86_VENDOR_CYRIX 1
   35.77 @@ -68,16 +81,17 @@ extern struct cpuinfo_x86 cpu_data[];
   35.78  #define current_cpu_data boot_cpu_data
   35.79  #endif
   35.80  
   35.81 -#define cpu_has_pge	(test_bit(X86_FEATURE_PGE,  boot_cpu_data.x86_capability))
   35.82 -#define cpu_has_pse	(test_bit(X86_FEATURE_PSE,  boot_cpu_data.x86_capability))
   35.83 -#define cpu_has_pae	(test_bit(X86_FEATURE_PAE,  boot_cpu_data.x86_capability))
   35.84 -#define cpu_has_tsc	(test_bit(X86_FEATURE_TSC,  boot_cpu_data.x86_capability))
   35.85 -#define cpu_has_de	(test_bit(X86_FEATURE_DE,   boot_cpu_data.x86_capability))
   35.86 -#define cpu_has_vme	(test_bit(X86_FEATURE_VME,  boot_cpu_data.x86_capability))
   35.87 -#define cpu_has_fxsr	(test_bit(X86_FEATURE_FXSR, boot_cpu_data.x86_capability))
   35.88 -#define cpu_has_xmm	(test_bit(X86_FEATURE_XMM,  boot_cpu_data.x86_capability))
   35.89 -#define cpu_has_fpu	(test_bit(X86_FEATURE_FPU,  boot_cpu_data.x86_capability))
   35.90 -#define cpu_has_apic	(test_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability))
   35.91 +#define cpu_has_pge 1
   35.92 +#define cpu_has_pse 1
   35.93 +#define cpu_has_pae 1
   35.94 +#define cpu_has_tsc 1
   35.95 +#define cpu_has_de 1
   35.96 +#define cpu_has_vme 1
   35.97 +#define cpu_has_fxsr 1
   35.98 +#define cpu_has_xmm 1
   35.99 +#define cpu_has_apic (test_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability))
  35.100 +
  35.101 +extern char ignore_irq13;
  35.102  
  35.103  extern void identify_cpu(struct cpuinfo_x86 *);
  35.104  extern void print_cpu_info(struct cpuinfo_x86 *);
  35.105 @@ -105,60 +119,61 @@ extern void dodgy_tsc(void);
  35.106  #define X86_EFLAGS_ID	0x00200000 /* CPUID detection flag */
  35.107  
  35.108  /*
  35.109 - * Generic CPUID function
  35.110 + *	Generic CPUID function
  35.111 + * 	FIXME: This really belongs to msr.h
  35.112   */
  35.113 -static inline void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx)
  35.114 +extern inline void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx)
  35.115  {
  35.116 -    __asm__("cpuid"
  35.117 -            : "=a" (*eax),
  35.118 -            "=b" (*ebx),
  35.119 -            "=c" (*ecx),
  35.120 -            "=d" (*edx)
  35.121 -            : "0" (op));
  35.122 +	__asm__("cpuid"
  35.123 +		: "=a" (*eax),
  35.124 +		  "=b" (*ebx),
  35.125 +		  "=c" (*ecx),
  35.126 +		  "=d" (*edx)
  35.127 +		: "0" (op));
  35.128  }
  35.129  
  35.130  /*
  35.131   * CPUID functions returning a single datum
  35.132   */
  35.133 -static inline unsigned int cpuid_eax(unsigned int op)
  35.134 +extern inline unsigned int cpuid_eax(unsigned int op)
  35.135  {
  35.136 -    unsigned int eax;
  35.137 +	unsigned int eax;
  35.138  
  35.139 -    __asm__("cpuid"
  35.140 -            : "=a" (eax)
  35.141 -            : "0" (op)
  35.142 -            : "bx", "cx", "dx");
  35.143 -    return eax;
  35.144 +	__asm__("cpuid"
  35.145 +		: "=a" (eax)
  35.146 +		: "0" (op)
  35.147 +		: "bx", "cx", "dx");
  35.148 +	return eax;
  35.149  }
  35.150 -static inline unsigned int cpuid_ebx(unsigned int op)
  35.151 +extern inline unsigned int cpuid_ebx(unsigned int op)
  35.152  {
  35.153 -    unsigned int eax, ebx;
  35.154 +	unsigned int eax, ebx;
  35.155  
  35.156 -    __asm__("cpuid"
  35.157 -            : "=a" (eax), "=b" (ebx)
  35.158 -            : "0" (op)
  35.159 -            : "cx", "dx" );
  35.160 -    return ebx;
  35.161 +	__asm__("cpuid"
  35.162 +		: "=a" (eax), "=b" (ebx)
  35.163 +		: "0" (op)
  35.164 +		: "cx", "dx" );
  35.165 +	return ebx;
  35.166  }
  35.167 -static inline unsigned int cpuid_ecx(unsigned int op)
  35.168 +extern inline unsigned int cpuid_ecx(unsigned int op)
  35.169  {
  35.170 -    unsigned int eax, ecx;
  35.171 +	unsigned int eax, ecx;
  35.172  
  35.173 -    __asm__("cpuid"
  35.174 -            : "=a" (eax), "=c" (ecx)
  35.175 -            : "0" (op)
  35.176 -            : "bx", "dx" );
  35.177 -    return ecx;
  35.178 +	__asm__("cpuid"
  35.179 +		: "=a" (eax), "=c" (ecx)
  35.180 +		: "0" (op)
  35.181 +		: "bx", "dx" );
  35.182 +	return ecx;
  35.183  }
  35.184 -static inline unsigned int cpuid_edx(unsigned int op)
  35.185 +extern inline unsigned int cpuid_edx(unsigned int op)
  35.186  {
  35.187 -    unsigned int eax, edx;
  35.188 +	unsigned int eax, edx;
  35.189  
  35.190 -    __asm__("cpuid"
  35.191 -            : "=a" (eax), "=d" (edx)
  35.192 -            : "0" (op)
  35.193 -            : "bx", "cx");
  35.194 -    return edx;
  35.195 +	__asm__("cpuid"
  35.196 +		: "=a" (eax), "=d" (edx)
  35.197 +		: "0" (op)
  35.198 +		: "bx", "cx");
  35.199 +	return edx;
  35.200  }
  35.201  
  35.202  
  35.203 @@ -177,15 +192,15 @@ static inline unsigned int cpuid_edx(uns
  35.204  #define X86_CR0_PG              0x80000000 /* Paging                   (RW) */
  35.205  
  35.206  #define read_cr0() ({ \
  35.207 -	unsigned int __dummy; \
  35.208 +	unsigned long __dummy; \
  35.209  	__asm__( \
  35.210 -		"movl %%cr0,%0\n\t" \
  35.211 +		"movq %%cr0,%0\n\t" \
  35.212  		:"=r" (__dummy)); \
  35.213  	__dummy; \
  35.214  })
  35.215  
  35.216  #define write_cr0(x) \
  35.217 -	__asm__("movl %0,%%cr0": :"r" (x));
  35.218 +	__asm__("movq %0,%%cr0": :"r" (x));
  35.219  
  35.220  
  35.221  
  35.222 @@ -214,22 +229,22 @@ extern unsigned long mmu_cr4_features;
  35.223  
  35.224  static inline void set_in_cr4 (unsigned long mask)
  35.225  {
  35.226 -    mmu_cr4_features |= mask;
  35.227 -    __asm__("movl %%cr4,%%eax\n\t"
  35.228 -            "orl %0,%%eax\n\t"
  35.229 -            "movl %%eax,%%cr4\n"
  35.230 -            : : "irg" (mask)
  35.231 -            :"ax");
  35.232 +	mmu_cr4_features |= mask;
  35.233 +	__asm__("movq %%cr4,%%rax\n\t"
  35.234 +		"orq %0,%%rax\n\t"
  35.235 +		"movq %%rax,%%cr4\n"
  35.236 +		: : "irg" (mask)
  35.237 +		:"ax");
  35.238  }
  35.239  
  35.240  static inline void clear_in_cr4 (unsigned long mask)
  35.241  {
  35.242 -    mmu_cr4_features &= ~mask;
  35.243 -    __asm__("movl %%cr4,%%eax\n\t"
  35.244 -            "andl %0,%%eax\n\t"
  35.245 -            "movl %%eax,%%cr4\n"
  35.246 -            : : "irg" (~mask)
  35.247 -            :"ax");
  35.248 +	mmu_cr4_features &= ~mask;
  35.249 +	__asm__("movq %%cr4,%%rax\n\t"
  35.250 +		"andq %0,%%rax\n\t"
  35.251 +		"movq %%rax,%%cr4\n"
  35.252 +		: : "irg" (~mask)
  35.253 +		:"ax");
  35.254  }
  35.255  
  35.256  /*
  35.257 @@ -259,25 +274,26 @@ static inline void clear_in_cr4 (unsigne
  35.258  	outb((data), 0x23); \
  35.259  } while (0)
  35.260  
  35.261 -#define EISA_bus (0)
  35.262 -#define MCA_bus  (0)
  35.263 +/*
  35.264 + * Bus types
  35.265 + */
  35.266 +#define EISA_bus 0
  35.267 +#define MCA_bus 0
  35.268 +#define MCA_bus__is_a_macro
  35.269  
  35.270 -/* from system description table in BIOS.  Mostly for MCA use, but
  35.271 -others may find it useful. */
  35.272 -extern unsigned int machine_id;
  35.273 -extern unsigned int machine_submodel_id;
  35.274 -extern unsigned int BIOS_revision;
  35.275 -extern unsigned int mca_pentium_flag;
  35.276  
  35.277  /*
  35.278 - * User space process size: 3GB (default).
  35.279 + * User space process size: 512GB - 1GB (default).
  35.280   */
  35.281 -#define TASK_SIZE	(PAGE_OFFSET)
  35.282 +#define TASK_SIZE	(0x0000007fc0000000)
  35.283  
  35.284  /* This decides where the kernel will search for a free chunk of vm
  35.285   * space during mmap's.
  35.286   */
  35.287 -#define TASK_UNMAPPED_BASE	(TASK_SIZE / 3)
  35.288 +#define TASK_UNMAPPED_32 0xa0000000
  35.289 +#define TASK_UNMAPPED_64 (TASK_SIZE/3) 
  35.290 +#define TASK_UNMAPPED_BASE	\
  35.291 +	((current->thread.flags & THREAD_IA32) ? TASK_UNMAPPED_32 : TASK_UNMAPPED_64)  
  35.292  
  35.293  /*
  35.294   * Size of io_bitmap in longwords: 32 is ports 0-0x3ff.
  35.295 @@ -286,125 +302,84 @@ extern unsigned int mca_pentium_flag;
  35.296  #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
  35.297  #define INVALID_IO_BITMAP_OFFSET 0x8000
  35.298  
  35.299 -struct i387_fsave_struct {
  35.300 -    long	cwd;
  35.301 -    long	swd;
  35.302 -    long	twd;
  35.303 -    long	fip;
  35.304 -    long	fcs;
  35.305 -    long	foo;
  35.306 -    long	fos;
  35.307 -    long	st_space[20];	/* 8*10 bytes for each FP-reg = 80 bytes */
  35.308 -};
  35.309 -
  35.310  struct i387_fxsave_struct {
  35.311 -    unsigned short	cwd;
  35.312 -    unsigned short	swd;
  35.313 -    unsigned short	twd;
  35.314 -    unsigned short	fop;
  35.315 -    long	fip;
  35.316 -    long	fcs;
  35.317 -    long	foo;
  35.318 -    long	fos;
  35.319 -    long	mxcsr;
  35.320 -    long	reserved;
  35.321 -    long	st_space[32];	/* 8*16 bytes for each FP-reg = 128 bytes */
  35.322 -    long	xmm_space[32];	/* 8*16 bytes for each XMM-reg = 128 bytes */
  35.323 -    long	padding[56];
  35.324 +	u16	cwd;
  35.325 +	u16	swd;
  35.326 +	u16	twd;
  35.327 +	u16	fop;
  35.328 +	u64	rip;
  35.329 +	u64	rdp; 
  35.330 +	u32	mxcsr;
  35.331 +	u32	mxcsr_mask;
  35.332 +	u32	st_space[32];	/* 8*16 bytes for each FP-reg = 128 bytes */
  35.333 +	u32	xmm_space[64];	/* 16*16 bytes for each XMM-reg = 128 bytes */
  35.334 +	u32	padding[24];
  35.335  } __attribute__ ((aligned (16)));
  35.336  
  35.337  union i387_union {
  35.338 -    struct i387_fsave_struct	fsave;
  35.339 -    struct i387_fxsave_struct	fxsave;
  35.340 +	struct i387_fxsave_struct	fxsave;
  35.341  };
  35.342  
  35.343  typedef struct {
  35.344 -    unsigned long seg;
  35.345 +	unsigned long seg;
  35.346  } mm_segment_t;
  35.347  
  35.348  struct tss_struct {
  35.349 -    unsigned short	back_link,__blh;
  35.350 -    unsigned long	esp0;
  35.351 -    unsigned short	ss0,__ss0h;
  35.352 -    unsigned long	esp1;
  35.353 -    unsigned short	ss1,__ss1h;
  35.354 -    unsigned long	esp2;
  35.355 -    unsigned short	ss2,__ss2h;
  35.356 -    unsigned long	__cr3;
  35.357 -    unsigned long	eip;
  35.358 -    unsigned long	eflags;
  35.359 -    unsigned long	eax,ecx,edx,ebx;
  35.360 -    unsigned long	esp;
  35.361 -    unsigned long	ebp;
  35.362 -    unsigned long	esi;
  35.363 -    unsigned long	edi;
  35.364 -    unsigned short	es, __esh;
  35.365 -    unsigned short	cs, __csh;
  35.366 -    unsigned short	ss, __ssh;
  35.367 -    unsigned short	ds, __dsh;
  35.368 -    unsigned short	fs, __fsh;
  35.369 -    unsigned short	gs, __gsh;
  35.370 -    unsigned short	ldt, __ldth;
  35.371 -    unsigned short	trace, bitmap;
  35.372 -    unsigned long	io_bitmap[IO_BITMAP_SIZE+1];
  35.373 -    /*
  35.374 -     * pads the TSS to be cacheline-aligned (size is 0x100)
  35.375 -     */
  35.376 -    unsigned long __cacheline_filler[5];
  35.377 -};
  35.378 +	unsigned short back_link,__blh;
  35.379 +/*	u32 reserved1; */
  35.380 +	u64 rsp0;	
  35.381 +	u64 rsp1;
  35.382 +	u64 rsp2;
  35.383 +	u64 reserved2;
  35.384 +	u64 ist[7];
  35.385 +	u32 reserved3;
  35.386 +	u32 reserved4;
  35.387 +	u16 reserved5;
  35.388 +	u16 io_map_base;
  35.389 +	u32 io_bitmap[IO_BITMAP_SIZE];
  35.390 +} __attribute__((packed)) ____cacheline_aligned;
  35.391  
  35.392  struct thread_struct {
  35.393 -    unsigned long esp1, ss1;
  35.394 +	unsigned long	rsp0;
  35.395 +	unsigned long	rip;
  35.396 +	unsigned long	rsp;
  35.397 +	unsigned long 	userrsp;	/* Copy from PDA */ 
  35.398 +	unsigned long	fs;
  35.399 +	unsigned long	gs;
  35.400 +	unsigned short	es, ds, fsindex, gsindex;	
  35.401 +	enum { 
  35.402 +		THREAD_IA32 = 0x0001,
  35.403 +	} flags;
  35.404  /* Hardware debugging registers */
  35.405 -    unsigned long	debugreg[8];  /* %%db0-7 debug registers */
  35.406 +	unsigned long	debugreg[8];  /* %%db0-7 debug registers */
  35.407  /* floating point info */
  35.408 -    union i387_union	i387;
  35.409 +	union i387_union	i387;
  35.410  /* Trap info. */
  35.411 -    int                 fast_trap_idx;
  35.412 -    struct desc_struct  fast_trap_desc;
  35.413 -    trap_info_t         traps[256];
  35.414 +	trap_info_t		traps[256];
  35.415  };
  35.416  
  35.417  #define IDT_ENTRIES 256
  35.418 -extern struct desc_struct idt_table[];
  35.419 -extern struct desc_struct *idt_tables[];
  35.420 -
  35.421 -#define SET_DEFAULT_FAST_TRAP(_p) \
  35.422 -    (_p)->fast_trap_idx = 0x20;   \
  35.423 -    (_p)->fast_trap_desc.a = 0;   \
  35.424 -    (_p)->fast_trap_desc.b = 0;
  35.425 -
  35.426 -#define CLEAR_FAST_TRAP(_p) \
  35.427 -    (memset(idt_tables[smp_processor_id()] + (_p)->fast_trap_idx, \
  35.428 -     0, 8))
  35.429 -
  35.430 -#define SET_FAST_TRAP(_p)   \
  35.431 -    (memcpy(idt_tables[smp_processor_id()] + (_p)->fast_trap_idx, \
  35.432 -     &((_p)->fast_trap_desc), 8))
  35.433 -
  35.434 -long set_fast_trap(struct task_struct *p, int idx);
  35.435 +extern struct gate_struct idt_table[];
  35.436 +extern struct gate_struct *idt_tables[];
  35.437  
  35.438  #define INIT_THREAD  {						\
  35.439  	0, 0,		      		       			\
  35.440 +	0, 0, 0, 0,						\
  35.441 +	0, 0, 0, 0,						\
  35.442 +	0,			/* flags */			\
  35.443  	{ [0 ... 7] = 0 },	/* debugging registers */	\
  35.444  	{ { 0, }, },		/* 387 state */			\
  35.445 -	0x20, { 0, 0 },		/* DEFAULT_FAST_TRAP */		\
  35.446  	{ {0} }			/* io permissions */		\
  35.447  }
  35.448  
  35.449  #define INIT_TSS  {						\
  35.450  	0,0, /* back_link, __blh */				\
  35.451 -	0, /* esp0 */						\
  35.452 -	0, 0, /* ss0 */						\
  35.453 -	0,0,0,0,0,0, /* stack1, stack2 */			\
  35.454 -	0, /* cr3 */						\
  35.455 -	0,0, /* eip,eflags */					\
  35.456 -	0,0,0,0, /* eax,ecx,edx,ebx */				\
  35.457 -	0,0,0,0, /* esp,ebp,esi,edi */				\
  35.458 -	0,0,0,0,0,0, /* es,cs,ss */				\
  35.459 -	0,0,0,0,0,0, /* ds,fs,gs */				\
  35.460 -	0,0, /* ldt */						\
  35.461 -	0, INVALID_IO_BITMAP_OFFSET, /* tace, bitmap */		\
  35.462 +	0, /* rsp0 */						\
  35.463 +	0, 0, /* rsp1, rsp2 */					\
  35.464 +	0, /* reserved */					\
  35.465 +	{ [0 ... 6] = 0 }, /* ist[] */				\
  35.466 +	0,0, /* reserved */					\
  35.467 +	0, INVALID_IO_BITMAP_OFFSET, /* trace, bitmap */	\
  35.468  	{~0, } /* ioperm */					\
  35.469  }
  35.470  
  35.471 @@ -418,7 +393,7 @@ struct mm_struct {
  35.472      /* Current LDT details. */
  35.473      unsigned long ldt_base, ldt_ents, shadow_ldt_mapcnt;
  35.474      /* Next entry is passed to LGDT on domain switch. */
  35.475 -    char gdt[6];
  35.476 +    char gdt[10];
  35.477  };
  35.478  
  35.479  #define IDLE0_MM                                                    \
  35.480 @@ -429,9 +404,9 @@ struct mm_struct {
  35.481  
  35.482  /* Convenient accessor for mm.gdt. */
  35.483  #define SET_GDT_ENTRIES(_p, _e) ((*(u16 *)((_p)->mm.gdt + 0)) = (_e))
  35.484 -#define SET_GDT_ADDRESS(_p, _a) ((*(u32 *)((_p)->mm.gdt + 2)) = (_a))
  35.485 +#define SET_GDT_ADDRESS(_p, _a) ((*(u64 *)((_p)->mm.gdt + 2)) = (_a))
  35.486  #define GET_GDT_ENTRIES(_p)     ((*(u16 *)((_p)->mm.gdt + 0)))
  35.487 -#define GET_GDT_ADDRESS(_p)     ((*(u32 *)((_p)->mm.gdt + 2)))
  35.488 +#define GET_GDT_ADDRESS(_p)     ((*(u64 *)((_p)->mm.gdt + 2)))
  35.489  
  35.490  long set_gdt(struct task_struct *p, 
  35.491               unsigned long *frames, 
  35.492 @@ -462,32 +437,26 @@ static inline void rep_nop(void)
  35.493  
  35.494  #define cpu_relax()	rep_nop()
  35.495  
  35.496 -/* Prefetch instructions for Pentium III and AMD Athlon */
  35.497 -#ifdef 	CONFIG_MPENTIUMIII
  35.498 +#define init_task	(init_task_union.task)
  35.499 +#define init_stack	(init_task_union.stack)
  35.500  
  35.501 -#define ARCH_HAS_PREFETCH
  35.502 -extern inline void prefetch(const void *x)
  35.503 -{
  35.504 -    __asm__ __volatile__ ("prefetchnta (%0)" : : "r"(x));
  35.505 -}
  35.506 +/* Avoid speculative execution by the CPU */
  35.507 +extern inline void sync_core(void)
  35.508 +{ 
  35.509 +	int tmp;
  35.510 +	asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
  35.511 +} 
  35.512  
  35.513 -#elif CONFIG_X86_USE_3DNOW
  35.514 +#define cpu_has_fpu 1
  35.515  
  35.516  #define ARCH_HAS_PREFETCH
  35.517  #define ARCH_HAS_PREFETCHW
  35.518  #define ARCH_HAS_SPINLOCK_PREFETCH
  35.519  
  35.520 -extern inline void prefetch(const void *x)
  35.521 -{
  35.522 -    __asm__ __volatile__ ("prefetch (%0)" : : "r"(x));
  35.523 -}
  35.524 +#define prefetch(x) __builtin_prefetch((x),0)
  35.525 +#define prefetchw(x) __builtin_prefetch((x),1)
  35.526 +#define spin_lock_prefetch(x)  prefetchw(x)
  35.527 +#define cpu_relax()   rep_nop()
  35.528  
  35.529 -extern inline void prefetchw(const void *x)
  35.530 -{
  35.531 -    __asm__ __volatile__ ("prefetchw (%0)" : : "r"(x));
  35.532 -}
  35.533 -#define spin_lock_prefetch(x)	prefetchw(x)
  35.534  
  35.535 -#endif
  35.536 -
  35.537 -#endif /* __ASM_I386_PROCESSOR_H */
  35.538 +#endif /* __ASM_X86_64_PROCESSOR_H */
    36.1 --- a/xen/include/asm-x86_64/ptrace.h	Wed Mar 10 13:44:42 2004 +0000
    36.2 +++ b/xen/include/asm-x86_64/ptrace.h	Wed Mar 10 13:46:20 2004 +0000
    36.3 @@ -1,27 +1,92 @@
    36.4 -#ifndef _I386_PTRACE_H
    36.5 -#define _I386_PTRACE_H
    36.6 +#ifndef _X86_64_PTRACE_H
    36.7 +#define _X86_64_PTRACE_H
    36.8 +
    36.9 +#if defined(__ASSEMBLY__) || defined(__FRAME_OFFSETS) 
   36.10 +#define R15 0
   36.11 +#define R14 8
   36.12 +#define R13 16
   36.13 +#define R12 24
   36.14 +#define RBP 36
   36.15 +#define RBX 40
   36.16 +/* arguments: interrupts/non tracing syscalls only save upto here*/
   36.17 +#define R11 48
   36.18 +#define R10 56	
   36.19 +#define R9 64
   36.20 +#define R8 72
   36.21 +#define RAX 80
   36.22 +#define RCX 88
   36.23 +#define RDX 96
   36.24 +#define RSI 104
   36.25 +#define RDI 112
   36.26 +#define ORIG_RAX 120       /* = ERROR */ 
   36.27 +/* end of arguments */ 	
   36.28 +/* cpu exception frame or undefined in case of fast syscall. */
   36.29 +#define RIP 128
   36.30 +#define CS 136
   36.31 +#define EFLAGS 144
   36.32 +#define RSP 152
   36.33 +#define SS 160
   36.34 +#define ARGOFFSET R11
   36.35 +#endif /* __ASSEMBLY__ */
   36.36 +
   36.37 +/* top of stack page */ 
   36.38 +#define FRAME_SIZE 168
   36.39 +
   36.40 +#define PTRACE_SETOPTIONS         21
   36.41 +
   36.42 +/* options set using PTRACE_SETOPTIONS */
   36.43 +#define PTRACE_O_TRACESYSGOOD     0x00000001
   36.44 +
   36.45 +/* Dummy values for ptrace */ 
   36.46 +#define FS 1000 
   36.47 +#define GS 1008
   36.48 +
   36.49 +#ifndef __ASSEMBLY__ 
   36.50  
   36.51  struct pt_regs {
   36.52 -	long ebx;
   36.53 -	long ecx;
   36.54 -	long edx;
   36.55 -	long esi;
   36.56 -	long edi;
   36.57 -	long ebp;
   36.58 -	long eax;
   36.59 -	int  xds;
   36.60 -	int  xes;
   36.61 -	int  xfs;
   36.62 -	int  xgs;
   36.63 -	long orig_eax;
   36.64 -	long eip;
   36.65 -	int  xcs;
   36.66 -	long eflags;
   36.67 -	long esp;
   36.68 -	int  xss;
   36.69 +	unsigned long r15;
   36.70 +	unsigned long r14;
   36.71 +	unsigned long r13;
   36.72 +	unsigned long r12;
   36.73 +	unsigned long rbp;
   36.74 +	unsigned long rbx;
   36.75 +/* arguments: non interrupts/non tracing syscalls only save upto here*/
   36.76 + 	unsigned long r11;
   36.77 +	unsigned long r10;	
   36.78 +	unsigned long r9;
   36.79 +	unsigned long r8;
   36.80 +	unsigned long rax;
   36.81 +	unsigned long rcx;
   36.82 +	unsigned long rdx;
   36.83 +	unsigned long rsi;
   36.84 +	unsigned long rdi;
   36.85 +	unsigned long orig_rax;
   36.86 +/* end of arguments */ 	
   36.87 +/* cpu exception frame or undefined */
   36.88 +	unsigned long rip;
   36.89 +	unsigned long cs;
   36.90 +	unsigned long eflags; 
   36.91 +	unsigned long rsp; 
   36.92 +	unsigned long ss;
   36.93 +/* top of stack page */ 
   36.94  };
   36.95  
   36.96 -enum EFLAGS {
   36.97 +#endif
   36.98 +
   36.99 +/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
  36.100 +#define PTRACE_GETREGS            12
  36.101 +#define PTRACE_SETREGS            13
  36.102 +#define PTRACE_GETFPREGS          14
  36.103 +#define PTRACE_SETFPREGS          15
  36.104 +#define PTRACE_GETFPXREGS         18
  36.105 +#define PTRACE_SETFPXREGS         19
  36.106 +
  36.107 +#if defined(__KERNEL__) && !defined(__ASSEMBLY__) 
  36.108 +#define user_mode(regs) (!!((regs)->cs & 3))
  36.109 +#define instruction_pointer(regs) ((regs)->rip)
  36.110 +extern void show_regs(struct pt_regs *);
  36.111 +
  36.112 +enum {
  36.113          EF_CF   = 0x00000001,
  36.114          EF_PF   = 0x00000004,
  36.115          EF_AF   = 0x00000010,
  36.116 @@ -44,8 +109,6 @@ enum EFLAGS {
  36.117          EF_ID   = 0x00200000,   /* id */
  36.118  };
  36.119  
  36.120 -#ifdef __KERNEL__
  36.121 -#define user_mode(regs) ((3 & (regs)->xcs))
  36.122  #endif
  36.123  
  36.124  #endif
    37.1 --- a/xen/include/asm-x86_64/rwlock.h	Wed Mar 10 13:44:42 2004 +0000
    37.2 +++ b/xen/include/asm-x86_64/rwlock.h	Wed Mar 10 13:46:20 2004 +0000
    37.3 @@ -1,4 +1,4 @@
    37.4 -/* include/asm-i386/rwlock.h
    37.5 +/* include/asm-x86_64/rwlock.h
    37.6   *
    37.7   *	Helpers used by both rw spinlocks and rw semaphores.
    37.8   *
    37.9 @@ -6,6 +6,7 @@
   37.10   *	spinlock.h Copyright 1996 Linus Torvalds.
   37.11   *
   37.12   *	Copyright 1999 Red Hat, Inc.
   37.13 + *	Copyright 2001,2002 SuSE labs 
   37.14   *
   37.15   *	Written by Benjamin LaHaise.
   37.16   *
   37.17 @@ -14,8 +15,8 @@
   37.18   *	as published by the Free Software Foundation; either version
   37.19   *	2 of the License, or (at your option) any later version.
   37.20   */
   37.21 -#ifndef _ASM_I386_RWLOCK_H
   37.22 -#define _ASM_I386_RWLOCK_H
   37.23 +#ifndef _ASM_X86_64_RWLOCK_H
   37.24 +#define _ASM_X86_64_RWLOCK_H
   37.25  
   37.26  #define RW_LOCK_BIAS		 0x01000000
   37.27  #define RW_LOCK_BIAS_STR	"0x01000000"
   37.28 @@ -35,10 +36,10 @@
   37.29  		     "js 2f\n" \
   37.30  		     "1:\n" \
   37.31  		     ".section .text.lock,\"ax\"\n" \
   37.32 -		     "2:\tpushl %%eax\n\t" \
   37.33 -		     "leal %0,%%eax\n\t" \
   37.34 +		     "2:\tpushq %%rax\n\t" \
   37.35 +		     "leaq %0,%%rax\n\t" \
   37.36  		     "call " helper "\n\t" \
   37.37 -		     "popl %%eax\n\t" \
   37.38 +		     "popq %%rax\n\t" \
   37.39  		     "jmp 1b\n" \
   37.40  		     ".previous" \
   37.41  		     :"=m" (*(volatile int *)rw) : : "memory")
   37.42 @@ -65,10 +66,10 @@
   37.43  		     "jnz 2f\n" \
   37.44  		     "1:\n" \
   37.45  		     ".section .text.lock,\"ax\"\n" \
   37.46 -		     "2:\tpushl %%eax\n\t" \
   37.47 -		     "leal %0,%%eax\n\t" \
   37.48 +		     "2:\tpushq %%rax\n\t" \
   37.49 +		     "leaq %0,%%rax\n\t" \
   37.50  		     "call " helper "\n\t" \
   37.51 -		     "popl %%eax\n\t" \
   37.52 +		     "popq %%rax\n\t" \
   37.53  		     "jmp 1b\n" \
   37.54  		     ".previous" \
   37.55  		     :"=m" (*(volatile int *)rw) : : "memory")
    38.1 --- a/xen/include/asm-x86_64/scatterlist.h	Wed Mar 10 13:44:42 2004 +0000
    38.2 +++ b/xen/include/asm-x86_64/scatterlist.h	Wed Mar 10 13:46:20 2004 +0000
    38.3 @@ -1,5 +1,5 @@
    38.4 -#ifndef _I386_SCATTERLIST_H
    38.5 -#define _I386_SCATTERLIST_H
    38.6 +#ifndef _X8664_SCATTERLIST_H
    38.7 +#define _X8664_SCATTERLIST_H
    38.8  
    38.9  struct scatterlist {
   38.10      char *  address;    /* Location data is to be transferred to, NULL for
    39.1 --- a/xen/include/asm-x86_64/smp.h	Wed Mar 10 13:44:42 2004 +0000
    39.2 +++ b/xen/include/asm-x86_64/smp.h	Wed Mar 10 13:46:20 2004 +0000
    39.3 @@ -5,12 +5,9 @@
    39.4  #include <asm/ptrace.h>
    39.5  
    39.6  #ifdef CONFIG_SMP
    39.7 -#define TARGET_CPUS cpu_online_map
    39.8 -#else
    39.9 -#define TARGET_CPUS 0x01
   39.10 -#endif
   39.11 +#ifndef ASSEMBLY
   39.12 +#include <asm/pda.h>
   39.13  
   39.14 -#ifdef CONFIG_SMP
   39.15  /*
   39.16   * Private routines/data
   39.17   */
   39.18 @@ -62,7 +59,7 @@ extern void smp_store_cpu_info(int id);	
   39.19   * so this is correct in the x86 case.
   39.20   */
   39.21  
   39.22 -#define smp_processor_id() (current->processor)
   39.23 +#define smp_processor_id() read_pda(cpunumber) 
   39.24  
   39.25  #include <asm/fixmap.h>
   39.26  #include <asm/apic.h>
   39.27 @@ -70,14 +67,37 @@ extern void smp_store_cpu_info(int id);	
   39.28  static __inline int hard_smp_processor_id(void)
   39.29  {
   39.30  	/* we don't want to mark this access volatile - bad code generation */
   39.31 -	return GET_APIC_ID(*(unsigned long *)(APIC_BASE+APIC_ID));
   39.32 +	return GET_APIC_ID(*(unsigned *)(APIC_BASE+APIC_ID));
   39.33  }
   39.34  
   39.35 -static __inline int logical_smp_processor_id(void)
   39.36 -{
   39.37 -	/* we don't want to mark this access volatile - bad code generation */
   39.38 -	return GET_APIC_LOGICAL_ID(*(unsigned long *)(APIC_BASE+APIC_LDR));
   39.39 -}
   39.40 +extern int apic_disabled;
   39.41 +extern int slow_smp_processor_id(void);
   39.42 +#define safe_smp_processor_id() \
   39.43 +	(!apic_disabled ? hard_smp_processor_id() : slow_smp_processor_id())
   39.44 +
   39.45 +#endif /* !ASSEMBLY */
   39.46 +
   39.47 +#define NO_PROC_ID		0xFF		/* No processor magic marker */
   39.48 +
   39.49 +/*
   39.50 + *	This magic constant controls our willingness to transfer
   39.51 + *	a process across CPUs. Such a transfer incurs misses on the L1
   39.52 + *	cache, and on a P6 or P5 with multiple L2 caches L2 hits. My
   39.53 + *	gut feeling is this will vary by board in value. For a board
   39.54 + *	with separate L2 cache it probably depends also on the RSS, and
   39.55 + *	for a board with shared L2 cache it ought to decay fast as other
   39.56 + *	processes are run.
   39.57 + */
   39.58 + 
   39.59 +#define PROC_CHANGE_PENALTY	15		/* Schedule penalty */
   39.60 +
   39.61 +
   39.62  
   39.63  #endif
   39.64 +#define INT_DELIVERY_MODE 1     /* logical delivery */
   39.65 +#define TARGET_CPUS 1
   39.66 +
   39.67 +#ifndef CONFIG_SMP
   39.68 +#define safe_smp_processor_id() 0
   39.69  #endif
   39.70 +#endif
    40.1 --- a/xen/include/asm-x86_64/spinlock.h	Wed Mar 10 13:44:42 2004 +0000
    40.2 +++ b/xen/include/asm-x86_64/spinlock.h	Wed Mar 10 13:46:20 2004 +0000
    40.3 @@ -59,52 +59,9 @@ typedef struct {
    40.4  
    40.5  /*
    40.6   * This works. Despite all the confusion.
    40.7 - * (except on PPro SMP or if we are using OOSTORE)
    40.8 - * (PPro errata 66, 92)
    40.9   */
   40.10 - 
   40.11 -#if !defined(CONFIG_X86_OOSTORE) && !defined(CONFIG_X86_PPRO_FENCE)
   40.12 -
   40.13  #define spin_unlock_string \
   40.14 -	"movb $1,%0" \
   40.15 -		:"=m" (lock->lock) : : "memory"
   40.16 -
   40.17 -
   40.18 -static inline void spin_unlock(spinlock_t *lock)
   40.19 -{
   40.20 -#if SPINLOCK_DEBUG
   40.21 -	if (lock->magic != SPINLOCK_MAGIC)
   40.22 -		BUG();
   40.23 -	if (!spin_is_locked(lock))
   40.24 -		BUG();
   40.25 -#endif
   40.26 -	__asm__ __volatile__(
   40.27 -		spin_unlock_string
   40.28 -	);
   40.29 -}
   40.30 -
   40.31 -#else
   40.32 -
   40.33 -#define spin_unlock_string \
   40.34 -	"xchgb %b0, %1" \
   40.35 -		:"=q" (oldval), "=m" (lock->lock) \
   40.36 -		:"0" (oldval) : "memory"
   40.37 -
   40.38 -static inline void spin_unlock(spinlock_t *lock)
   40.39 -{
   40.40 -	char oldval = 1;
   40.41 -#if SPINLOCK_DEBUG
   40.42 -	if (lock->magic != SPINLOCK_MAGIC)
   40.43 -		BUG();
   40.44 -	if (!spin_is_locked(lock))
   40.45 -		BUG();
   40.46 -#endif
   40.47 -	__asm__ __volatile__(
   40.48 -		spin_unlock_string
   40.49 -	);
   40.50 -}
   40.51 -
   40.52 -#endif
   40.53 +	"movb $1,%0"
   40.54  
   40.55  static inline int spin_trylock(spinlock_t *lock)
   40.56  {
   40.57 @@ -131,6 +88,18 @@ printk("eip: %p\n", &&here);
   40.58  		:"=m" (lock->lock) : : "memory");
   40.59  }
   40.60  
   40.61 +static inline void spin_unlock(spinlock_t *lock)
   40.62 +{
   40.63 +#if SPINLOCK_DEBUG
   40.64 +	if (lock->magic != SPINLOCK_MAGIC)
   40.65 +		BUG();
   40.66 +	if (!spin_is_locked(lock))
   40.67 +		BUG();
   40.68 +#endif
   40.69 +	__asm__ __volatile__(
   40.70 +		spin_unlock_string
   40.71 +		:"=m" (lock->lock) : : "memory");
   40.72 +}
   40.73  
   40.74  /*
   40.75   * Read-write spinlocks, allowing multiple readers
   40.76 @@ -170,7 +139,7 @@ typedef struct {
   40.77   * Changed to use the same technique as rw semaphores.  See
   40.78   * semaphore.h for details.  -ben
   40.79   */
   40.80 -/* the spinlock helpers are in arch/i386/kernel/semaphore.c */
   40.81 +/* the spinlock helpers are in arch/x86_64/kernel/semaphore.S */
   40.82  
   40.83  static inline void read_lock(rwlock_t *rw)
   40.84  {
    41.1 --- a/xen/include/asm-x86_64/string.h	Wed Mar 10 13:44:42 2004 +0000
    41.2 +++ b/xen/include/asm-x86_64/string.h	Wed Mar 10 13:46:20 2004 +0000
    41.3 @@ -1,205 +1,14 @@
    41.4 -#ifndef _I386_STRING_H_
    41.5 -#define _I386_STRING_H_
    41.6 +#ifndef _X86_64_STRING_H_
    41.7 +#define _X86_64_STRING_H_
    41.8  
    41.9  #ifdef __KERNEL__
   41.10 -#include <linux/config.h>
   41.11 -/*
   41.12 - * On a 486 or Pentium, we are better off not using the
   41.13 - * byte string operations. But on a 386 or a PPro the
   41.14 - * byte string ops are faster than doing it by hand
   41.15 - * (MUCH faster on a Pentium).
   41.16 - *
   41.17 - * Also, the byte strings actually work correctly. Forget
   41.18 - * the i486 routines for now as they may be broken..
   41.19 - */
   41.20 -#if FIXED_486_STRING && defined(CONFIG_X86_USE_STRING_486)
   41.21 -#include <asm/string-486.h>
   41.22 -#else
   41.23  
   41.24 -/*
   41.25 - * This string-include defines all string functions as inline
   41.26 - * functions. Use gcc. It also assumes ds=es=data space, this should be
   41.27 - * normal. Most of the string-functions are rather heavily hand-optimized,
   41.28 - * see especially strtok,strstr,str[c]spn. They should work, but are not
   41.29 - * very easy to understand. Everything is done entirely within the register
   41.30 - * set, making the functions fast and clean. String instructions have been
   41.31 - * used through-out, making for "slightly" unclear code :-)
   41.32 - *
   41.33 - *		NO Copyright (C) 1991, 1992 Linus Torvalds,
   41.34 - *		consider these trivial functions to be PD.
   41.35 - */
   41.36 -
   41.37 +/* Written 2002 by Andi Kleen */ 
   41.38  
   41.39 -#define __HAVE_ARCH_STRCPY
   41.40 -static inline char * strcpy(char * dest,const char *src)
   41.41 -{
   41.42 -int d0, d1, d2;
   41.43 -__asm__ __volatile__(
   41.44 -	"1:\tlodsb\n\t"
   41.45 -	"stosb\n\t"
   41.46 -	"testb %%al,%%al\n\t"
   41.47 -	"jne 1b"
   41.48 -	: "=&S" (d0), "=&D" (d1), "=&a" (d2)
   41.49 -	:"0" (src),"1" (dest) : "memory");
   41.50 -return dest;
   41.51 -}
   41.52 -
   41.53 -#define __HAVE_ARCH_STRNCPY
   41.54 -static inline char * strncpy(char * dest,const char *src,size_t count)
   41.55 -{
   41.56 -int d0, d1, d2, d3;
   41.57 -__asm__ __volatile__(
   41.58 -	"1:\tdecl %2\n\t"
   41.59 -	"js 2f\n\t"
   41.60 -	"lodsb\n\t"
   41.61 -	"stosb\n\t"
   41.62 -	"testb %%al,%%al\n\t"
   41.63 -	"jne 1b\n\t"
   41.64 -	"rep\n\t"
   41.65 -	"stosb\n"
   41.66 -	"2:"
   41.67 -	: "=&S" (d0), "=&D" (d1), "=&c" (d2), "=&a" (d3)
   41.68 -	:"0" (src),"1" (dest),"2" (count) : "memory");
   41.69 -return dest;
   41.70 -}
   41.71 -
   41.72 -#define __HAVE_ARCH_STRCAT
   41.73 -static inline char * strcat(char * dest,const char * src)
   41.74 -{
   41.75 -int d0, d1, d2, d3;
   41.76 -__asm__ __volatile__(
   41.77 -	"repne\n\t"
   41.78 -	"scasb\n\t"
   41.79 -	"decl %1\n"
   41.80 -	"1:\tlodsb\n\t"
   41.81 -	"stosb\n\t"
   41.82 -	"testb %%al,%%al\n\t"
   41.83 -	"jne 1b"
   41.84 -	: "=&S" (d0), "=&D" (d1), "=&a" (d2), "=&c" (d3)
   41.85 -	: "0" (src), "1" (dest), "2" (0), "3" (0xffffffff):"memory");
   41.86 -return dest;
   41.87 -}
   41.88 -
   41.89 -#define __HAVE_ARCH_STRNCAT
   41.90 -static inline char * strncat(char * dest,const char * src,size_t count)
   41.91 +/* Only used for special circumstances. Stolen from i386/string.h */ 
   41.92 +static inline void * __inline_memcpy(void * to, const void * from, size_t n)
   41.93  {
   41.94 -int d0, d1, d2, d3;
   41.95 -__asm__ __volatile__(
   41.96 -	"repne\n\t"
   41.97 -	"scasb\n\t"
   41.98 -	"decl %1\n\t"
   41.99 -	"movl %8,%3\n"
  41.100 -	"1:\tdecl %3\n\t"
  41.101 -	"js 2f\n\t"
  41.102 -	"lodsb\n\t"
  41.103 -	"stosb\n\t"
  41.104 -	"testb %%al,%%al\n\t"
  41.105 -	"jne 1b\n"
  41.106 -	"2:\txorl %2,%2\n\t"
  41.107 -	"stosb"
  41.108 -	: "=&S" (d0), "=&D" (d1), "=&a" (d2), "=&c" (d3)
  41.109 -	: "0" (src),"1" (dest),"2" (0),"3" (0xffffffff), "g" (count)
  41.110 -	: "memory");
  41.111 -return dest;
  41.112 -}
  41.113 -
  41.114 -#define __HAVE_ARCH_STRCMP
  41.115 -static inline int strcmp(const char * cs,const char * ct)
  41.116 -{
  41.117 -int d0, d1;
  41.118 -register int __res;
  41.119 -__asm__ __volatile__(
  41.120 -	"1:\tlodsb\n\t"
  41.121 -	"scasb\n\t"
  41.122 -	"jne 2f\n\t"
  41.123 -	"testb %%al,%%al\n\t"
  41.124 -	"jne 1b\n\t"
  41.125 -	"xorl %%eax,%%eax\n\t"
  41.126 -	"jmp 3f\n"
  41.127 -	"2:\tsbbl %%eax,%%eax\n\t"
  41.128 -	"orb $1,%%al\n"
  41.129 -	"3:"
  41.130 -	:"=a" (__res), "=&S" (d0), "=&D" (d1)
  41.131 -		     :"1" (cs),"2" (ct));
  41.132 -return __res;
  41.133 -}
  41.134 -
  41.135 -#define __HAVE_ARCH_STRNCMP
  41.136 -static inline int strncmp(const char * cs,const char * ct,size_t count)
  41.137 -{
  41.138 -register int __res;
  41.139 -int d0, d1, d2;
  41.140 -__asm__ __volatile__(
  41.141 -	"1:\tdecl %3\n\t"
  41.142 -	"js 2f\n\t"
  41.143 -	"lodsb\n\t"
  41.144 -	"scasb\n\t"
  41.145 -	"jne 3f\n\t"
  41.146 -	"testb %%al,%%al\n\t"
  41.147 -	"jne 1b\n"
  41.148 -	"2:\txorl %%eax,%%eax\n\t"
  41.149 -	"jmp 4f\n"
  41.150 -	"3:\tsbbl %%eax,%%eax\n\t"
  41.151 -	"orb $1,%%al\n"
  41.152 -	"4:"
  41.153 -		     :"=a" (__res), "=&S" (d0), "=&D" (d1), "=&c" (d2)
  41.154 -		     :"1" (cs),"2" (ct),"3" (count));
  41.155 -return __res;
  41.156 -}
  41.157 -
  41.158 -#define __HAVE_ARCH_STRCHR
  41.159 -static inline char * strchr(const char * s, int c)
  41.160 -{
  41.161 -int d0;
  41.162 -register char * __res;
  41.163 -__asm__ __volatile__(
  41.164 -	"movb %%al,%%ah\n"
  41.165 -	"1:\tlodsb\n\t"
  41.166 -	"cmpb %%ah,%%al\n\t"
  41.167 -	"je 2f\n\t"
  41.168 -	"testb %%al,%%al\n\t"
  41.169 -	"jne 1b\n\t"
  41.170 -	"movl $1,%1\n"
  41.171 -	"2:\tmovl %1,%0\n\t"
  41.172 -	"decl %0"
  41.173 -	:"=a" (__res), "=&S" (d0) : "1" (s),"0" (c));
  41.174 -return __res;
  41.175 -}
  41.176 -
  41.177 -#define __HAVE_ARCH_STRRCHR
  41.178 -static inline char * strrchr(const char * s, int c)
  41.179 -{
  41.180 -int d0, d1;
  41.181 -register char * __res;
  41.182 -__asm__ __volatile__(
  41.183 -	"movb %%al,%%ah\n"
  41.184 -	"1:\tlodsb\n\t"
  41.185 -	"cmpb %%ah,%%al\n\t"
  41.186 -	"jne 2f\n\t"
  41.187 -	"leal -1(%%esi),%0\n"
  41.188 -	"2:\ttestb %%al,%%al\n\t"
  41.189 -	"jne 1b"
  41.190 -	:"=g" (__res), "=&S" (d0), "=&a" (d1) :"0" (0),"1" (s),"2" (c));
  41.191 -return __res;
  41.192 -}
  41.193 -
  41.194 -#define __HAVE_ARCH_STRLEN
  41.195 -static inline size_t strlen(const char * s)
  41.196 -{
  41.197 -int d0;
  41.198 -register int __res;
  41.199 -__asm__ __volatile__(
  41.200 -	"repne\n\t"
  41.201 -	"scasb\n\t"
  41.202 -	"notl %0\n\t"
  41.203 -	"decl %0"
  41.204 -	:"=c" (__res), "=&D" (d0) :"1" (s),"a" (0), "0" (0xffffffff));
  41.205 -return __res;
  41.206 -}
  41.207 -
  41.208 -static inline void * __memcpy(void * to, const void * from, size_t n)
  41.209 -{
  41.210 -int d0, d1, d2;
  41.211 +unsigned long d0, d1, d2;
  41.212  __asm__ __volatile__(
  41.213  	"rep ; movsl\n\t"
  41.214  	"testb $2,%b4\n\t"
  41.215 @@ -215,286 +24,27 @@ int d0, d1, d2;
  41.216  return (to);
  41.217  }
  41.218  
  41.219 -/*
  41.220 - * This looks horribly ugly, but the compiler can optimize it totally,
  41.221 - * as the count is constant.
  41.222 - */
  41.223 -static inline void * __constant_memcpy(void * to, const void * from, size_t n)
  41.224 -{
  41.225 -	switch (n) {
  41.226 -		case 0:
  41.227 -			return to;
  41.228 -		case 1:
  41.229 -			*(unsigned char *)to = *(const unsigned char *)from;
  41.230 -			return to;
  41.231 -		case 2:
  41.232 -			*(unsigned short *)to = *(const unsigned short *)from;
  41.233 -			return to;
  41.234 -		case 3:
  41.235 -			*(unsigned short *)to = *(const unsigned short *)from;
  41.236 -			*(2+(unsigned char *)to) = *(2+(const unsigned char *)from);
  41.237 -			return to;
  41.238 -		case 4:
  41.239 -			*(unsigned long *)to = *(const unsigned long *)from;
  41.240 -			return to;
  41.241 -		case 6:	/* for Ethernet addresses */
  41.242 -			*(unsigned long *)to = *(const unsigned long *)from;
  41.243 -			*(2+(unsigned short *)to) = *(2+(const unsigned short *)from);
  41.244 -			return to;
  41.245 -		case 8:
  41.246 -			*(unsigned long *)to = *(const unsigned long *)from;
  41.247 -			*(1+(unsigned long *)to) = *(1+(const unsigned long *)from);
  41.248 -			return to;
  41.249 -		case 12:
  41.250 -			*(unsigned long *)to = *(const unsigned long *)from;
  41.251 -			*(1+(unsigned long *)to) = *(1+(const unsigned long *)from);
  41.252 -			*(2+(unsigned long *)to) = *(2+(const unsigned long *)from);
  41.253 -			return to;
  41.254 -		case 16:
  41.255 -			*(unsigned long *)to = *(const unsigned long *)from;
  41.256 -			*(1+(unsigned long *)to) = *(1+(const unsigned long *)from);
  41.257 -			*(2+(unsigned long *)to) = *(2+(const unsigned long *)from);
  41.258 -			*(3+(unsigned long *)to) = *(3+(const unsigned long *)from);
  41.259 -			return to;
  41.260 -		case 20:
  41.261 -			*(unsigned long *)to = *(const unsigned long *)from;
  41.262 -			*(1+(unsigned long *)to) = *(1+(const unsigned long *)from);
  41.263 -			*(2+(unsigned long *)to) = *(2+(const unsigned long *)from);
  41.264 -			*(3+(unsigned long *)to) = *(3+(const unsigned long *)from);
  41.265 -			*(4+(unsigned long *)to) = *(4+(const unsigned long *)from);
  41.266 -			return to;
  41.267 -	}
  41.268 -#define COMMON(x) \
  41.269 -__asm__ __volatile__( \
  41.270 -	"rep ; movsl" \
  41.271 -	x \
  41.272 -	: "=&c" (d0), "=&D" (d1), "=&S" (d2) \
  41.273 -	: "0" (n/4),"1" ((long) to),"2" ((long) from) \
  41.274 -	: "memory");
  41.275 -{
  41.276 -	int d0, d1, d2;
  41.277 -	switch (n % 4) {
  41.278 -		case 0: COMMON(""); return to;
  41.279 -		case 1: COMMON("\n\tmovsb"); return to;
  41.280 -		case 2: COMMON("\n\tmovsw"); return to;
  41.281 -		default: COMMON("\n\tmovsw\n\tmovsb"); return to;
  41.282 -	}
  41.283 -}
  41.284 -  
  41.285 -#undef COMMON
  41.286 -}
  41.287 +/* Even with __builtin_ the compiler may decide to use the out of line
  41.288 +   function. */
  41.289  
  41.290 -#define __HAVE_ARCH_MEMCPY
  41.291 -
  41.292 -#define memcpy(t, f, n) \
  41.293 -(__builtin_constant_p(n) ? \
  41.294 - __constant_memcpy((t),(f),(n)) : \
  41.295 - __memcpy((t),(f),(n)))
  41.296 +#define __HAVE_ARCH_MEMCPY 1
  41.297 +extern void *__memcpy(void *to, const void *from, size_t len); 
  41.298 +#define memcpy(dst,src,len) \
  41.299 +	({ size_t __len = (len);				\
  41.300 +	   void *__ret;						\
  41.301 +	   if (__builtin_constant_p(len) && __len >= 64)	\
  41.302 +		 __ret = __memcpy((dst),(src),__len);		\
  41.303 +	   else							\
  41.304 +		 __ret = __builtin_memcpy((dst),(src),__len);	\
  41.305 +	   __ret; }) 
  41.306  
  41.307  
  41.308 -/*
  41.309 - * struct_cpy(x,y), copy structure *x into (matching structure) *y.
  41.310 - *
  41.311 - * We get link-time errors if the structure sizes do not match.
  41.312 - * There is no runtime overhead, it's all optimized away at
  41.313 - * compile time.
  41.314 - */
  41.315 -//extern void __struct_cpy_bug (void);
  41.316 -
  41.317 -/*
  41.318 -#define struct_cpy(x,y) 			\
  41.319 -({						\
  41.320 -	if (sizeof(*(x)) != sizeof(*(y))) 	\
  41.321 -		__struct_cpy_bug;		\
  41.322 -	memcpy(x, y, sizeof(*(x)));		\
  41.323 -})
  41.324 -*/
  41.325 +#define __HAVE_ARCH_MEMSET
  41.326 +#define memset __builtin_memset
  41.327  
  41.328  #define __HAVE_ARCH_MEMMOVE
  41.329 -static inline void * memmove(void * dest,const void * src, size_t n)
  41.330 -{
  41.331 -int d0, d1, d2;
  41.332 -if (dest<src)
  41.333 -__asm__ __volatile__(
  41.334 -	"rep\n\t"
  41.335 -	"movsb"
  41.336 -	: "=&c" (d0), "=&S" (d1), "=&D" (d2)
  41.337 -	:"0" (n),"1" (src),"2" (dest)
  41.338 -	: "memory");
  41.339 -else
  41.340 -__asm__ __volatile__(
  41.341 -	"std\n\t"
  41.342 -	"rep\n\t"
  41.343 -	"movsb\n\t"
  41.344 -	"cld"
  41.345 -	: "=&c" (d0), "=&S" (d1), "=&D" (d2)
  41.346 -	:"0" (n),
  41.347 -	 "1" (n-1+(const char *)src),
  41.348 -	 "2" (n-1+(char *)dest)
  41.349 -	:"memory");
  41.350 -return dest;
  41.351 -}
  41.352 -
  41.353 -#define memcmp __builtin_memcmp
  41.354 -
  41.355 -#define __HAVE_ARCH_MEMCHR
  41.356 -static inline void * memchr(const void * cs,int c,size_t count)
  41.357 -{
  41.358 -int d0;
  41.359 -register void * __res;
  41.360 -if (!count)
  41.361 -	return NULL;
  41.362 -__asm__ __volatile__(
  41.363 -	"repne\n\t"
  41.364 -	"scasb\n\t"
  41.365 -	"je 1f\n\t"
  41.366 -	"movl $1,%0\n"
  41.367 -	"1:\tdecl %0"
  41.368 -	:"=D" (__res), "=&c" (d0) : "a" (c),"0" (cs),"1" (count));
  41.369 -return __res;
  41.370 -}
  41.371 -
  41.372 -static inline void * __memset_generic(void * s, char c,size_t count)
  41.373 -{
  41.374 -int d0, d1;
  41.375 -__asm__ __volatile__(
  41.376 -	"rep\n\t"
  41.377 -	"stosb"
  41.378 -	: "=&c" (d0), "=&D" (d1)
  41.379 -	:"a" (c),"1" (s),"0" (count)
  41.380 -	:"memory");
  41.381 -return s;
  41.382 -}
  41.383 -
  41.384 -/* we might want to write optimized versions of these later */
  41.385 -#define __constant_count_memset(s,c,count) __memset_generic((s),(c),(count))
  41.386 -
  41.387 -/*
  41.388 - * memset(x,0,y) is a reasonably common thing to do, so we want to fill
  41.389 - * things 32 bits at a time even when we don't know the size of the
  41.390 - * area at compile-time..
  41.391 - */
  41.392 -static inline void * __constant_c_memset(void * s, unsigned long c, size_t count)
  41.393 -{
  41.394 -int d0, d1;
  41.395 -__asm__ __volatile__(
  41.396 -	"rep ; stosl\n\t"
  41.397 -	"testb $2,%b3\n\t"
  41.398 -	"je 1f\n\t"
  41.399 -	"stosw\n"
  41.400 -	"1:\ttestb $1,%b3\n\t"
  41.401 -	"je 2f\n\t"
  41.402 -	"stosb\n"
  41.403 -	"2:"
  41.404 -	: "=&c" (d0), "=&D" (d1)
  41.405 -	:"a" (c), "q" (count), "0" (count/4), "1" ((long) s)
  41.406 -	:"memory");
  41.407 -return (s);	
  41.408 -}
  41.409 +void * memmove(void * dest,const void *src,size_t count);
  41.410  
  41.411 -/* Added by Gertjan van Wingerde to make minix and sysv module work */
  41.412 -#define __HAVE_ARCH_STRNLEN
  41.413 -static inline size_t strnlen(const char * s, size_t count)
  41.414 -{
  41.415 -int d0;
  41.416 -register int __res;
  41.417 -__asm__ __volatile__(
  41.418 -	"movl %2,%0\n\t"
  41.419 -	"jmp 2f\n"
  41.420 -	"1:\tcmpb $0,(%0)\n\t"
  41.421 -	"je 3f\n\t"
  41.422 -	"incl %0\n"
  41.423 -	"2:\tdecl %1\n\t"
  41.424 -	"cmpl $-1,%1\n\t"
  41.425 -	"jne 1b\n"
  41.426 -	"3:\tsubl %2,%0"
  41.427 -	:"=a" (__res), "=&d" (d0)
  41.428 -	:"c" (s),"1" (count));
  41.429 -return __res;
  41.430 -}
  41.431 -/* end of additional stuff */
  41.432 -
  41.433 -//#define __HAVE_ARCH_STRSTR
  41.434 -
  41.435 -//extern char *strstr(const char *cs, const char *ct);
  41.436 -
  41.437 -/*
  41.438 - * This looks horribly ugly, but the compiler can optimize it totally,
  41.439 - * as we by now know that both pattern and count is constant..
  41.440 - */
  41.441 -static inline void * __constant_c_and_count_memset(void * s, unsigned long pattern, size_t count)
  41.442 -{
  41.443 -	switch (count) {
  41.444 -		case 0:
  41.445 -			return s;
  41.446 -		case 1:
  41.447 -			*(unsigned char *)s = pattern;
  41.448 -			return s;
  41.449 -		case 2:
  41.450 -			*(unsigned short *)s = pattern;
  41.451 -			return s;
  41.452 -		case 3:
  41.453 -			*(unsigned short *)s = pattern;
  41.454 -			*(2+(unsigned char *)s) = pattern;
  41.455 -			return s;
  41.456 -		case 4:
  41.457 -			*(unsigned long *)s = pattern;
  41.458 -			return s;
  41.459 -	}
  41.460 -#define COMMON(x) \
  41.461 -__asm__  __volatile__( \
  41.462 -	"rep ; stosl" \
  41.463 -	x \
  41.464 -	: "=&c" (d0), "=&D" (d1) \
  41.465 -	: "a" (pattern),"0" (count/4),"1" ((long) s) \
  41.466 -	: "memory")
  41.467 -{
  41.468 -	int d0, d1;
  41.469 -	switch (count % 4) {
  41.470 -		case 0: COMMON(""); return s;
  41.471 -		case 1: COMMON("\n\tstosb"); return s;
  41.472 -		case 2: COMMON("\n\tstosw"); return s;
  41.473 -		default: COMMON("\n\tstosw\n\tstosb"); return s;
  41.474 -	}
  41.475 -}
  41.476 -  
  41.477 -#undef COMMON
  41.478 -}
  41.479 -
  41.480 -#define __constant_c_x_memset(s, c, count) \
  41.481 -(__builtin_constant_p(count) ? \
  41.482 - __constant_c_and_count_memset((s),(c),(count)) : \
  41.483 - __constant_c_memset((s),(c),(count)))
  41.484 -
  41.485 -#define __memset(s, c, count) \
  41.486 -(__builtin_constant_p(count) ? \
  41.487 - __constant_count_memset((s),(c),(count)) : \
  41.488 - __memset_generic((s),(c),(count)))
  41.489 -
  41.490 -#define __HAVE_ARCH_MEMSET
  41.491 -#define memset(s, c, count) \
  41.492 -(__builtin_constant_p(c) ? \
  41.493 - __constant_c_x_memset((s),(0x01010101UL*(unsigned char)(c)),(count)) : \
  41.494 - __memset((s),(c),(count)))
  41.495 -
  41.496 -/*
  41.497 - * find the first occurrence of byte 'c', or 1 past the area if none
  41.498 - */
  41.499 -#define __HAVE_ARCH_MEMSCAN
  41.500 -static inline void * memscan(void * addr, int c, size_t size)
  41.501 -{
  41.502 -	if (!size)
  41.503 -		return addr;
  41.504 -	__asm__("repnz; scasb\n\t"
  41.505 -		"jnz 1f\n\t"
  41.506 -		"dec %%edi\n"
  41.507 -		"1:"
  41.508 -		: "=D" (addr), "=c" (size)
  41.509 -		: "0" (addr), "1" (size), "a" (c));
  41.510 -	return addr;
  41.511 -}
  41.512 -
  41.513 -#endif /* CONFIG_X86_USE_STRING_486 */
  41.514  #endif /* __KERNEL__ */
  41.515  
  41.516  #endif
    42.1 --- a/xen/include/asm-x86_64/system.h	Wed Mar 10 13:44:42 2004 +0000
    42.2 +++ b/xen/include/asm-x86_64/system.h	Wed Mar 10 13:46:20 2004 +0000
    42.3 @@ -23,9 +23,14 @@ static inline unsigned long get_limit(un
    42.4  
    42.5  #define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
    42.6  
    42.7 -struct __xchg_dummy { unsigned long a[100]; };
    42.8 -#define __xg(x) ((struct __xchg_dummy *)(x))
    42.9 +#define __xg(x) ((volatile long *)(x))
   42.10  
   42.11 +extern inline void set_64bit(volatile unsigned long *ptr, unsigned long val)
   42.12 +{
   42.13 +	*ptr = val;
   42.14 +}
   42.15 +
   42.16 +#define _set_64bit set_64bit
   42.17  
   42.18  /*
   42.19   * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
   42.20 @@ -48,7 +53,13 @@ static inline unsigned long __xchg(unsig
   42.21  				:"memory");
   42.22  			break;
   42.23  		case 4:
   42.24 -			__asm__ __volatile__("xchgl %0,%1"
   42.25 +			__asm__ __volatile__("xchgl %k0,%1"
   42.26 +				:"=r" (x)
   42.27 +				:"m" (*__xg(ptr)), "0" (x)
   42.28 +				:"memory");
   42.29 +			break;
   42.30 +		case 8:
   42.31 +			__asm__ __volatile__("xchgq %0,%1"
   42.32  				:"=r" (x)
   42.33  				:"m" (*__xg(ptr)), "0" (x)
   42.34  				:"memory");
   42.35 @@ -63,6 +74,8 @@ static inline unsigned long __xchg(unsig
   42.36   * indicated by comparing RETURN with OLD.
   42.37   */
   42.38  
   42.39 +#define __HAVE_ARCH_CMPXCHG 1
   42.40 +
   42.41  static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
   42.42  				      unsigned long new, int size)
   42.43  {
   42.44 @@ -81,7 +94,13 @@ static inline unsigned long __cmpxchg(vo
   42.45  				     : "memory");
   42.46  		return prev;
   42.47  	case 4:
   42.48 -		__asm__ __volatile__(LOCK_PREFIX "cmpxchgl %1,%2"
   42.49 +		__asm__ __volatile__(LOCK_PREFIX "cmpxchgl %k1,%2"
   42.50 +				     : "=a"(prev)
   42.51 +				     : "q"(new), "m"(*__xg(ptr)), "0"(old)
   42.52 +				     : "memory");
   42.53 +		return prev;
   42.54 +	case 8:
   42.55 +		__asm__ __volatile__(LOCK_PREFIX "cmpxchgq %1,%2"
   42.56  				     : "=a"(prev)
   42.57  				     : "q"(new), "m"(*__xg(ptr)), "0"(old)
   42.58  				     : "memory");
   42.59 @@ -105,7 +124,7 @@ static inline unsigned long __cmpxchg(vo
   42.60  ({                                                                      \
   42.61      int _rc;                                                            \
   42.62      __asm__ __volatile__ (                                              \
   42.63 -        "1: " LOCK_PREFIX "cmpxchgl %2,%3\n"                            \
   42.64 +        "1: " LOCK_PREFIX "cmpxchgq %2,%3\n"                            \
   42.65          "2:\n"                                                          \
   42.66          ".section .fixup,\"ax\"\n"                                      \
   42.67          "3:     movl $1,%1\n"                                           \
   42.68 @@ -121,6 +140,16 @@ static inline unsigned long __cmpxchg(vo
   42.69      _rc;                                                                \
   42.70  })
   42.71  
   42.72 +#ifdef CONFIG_SMP
   42.73 +#define smp_mb()	mb()
   42.74 +#define smp_rmb()	rmb()
   42.75 +#define smp_wmb()	wmb()
   42.76 +#else
   42.77 +#define smp_mb()	barrier()
   42.78 +#define smp_rmb()	barrier()
   42.79 +#define smp_wmb()	barrier()
   42.80 +#endif
   42.81 +
   42.82  /*
   42.83   * Force strict CPU ordering.
   42.84   * And yes, this is required on UP too when we're talking
   42.85 @@ -134,44 +163,27 @@ static inline unsigned long __cmpxchg(vo
   42.86   * I expect future Intel CPU's to have a weaker ordering,
   42.87   * but I'd also expect them to finally get their act together
   42.88   * and add some real memory barriers if so.
   42.89 - *
   42.90 - * Some non intel clones support out of order store. wmb() ceases to be a
   42.91 - * nop for these.
   42.92   */
   42.93 - 
   42.94 -#define mb() 	__asm__ __volatile__ ("lock; addl $0,0(%%esp)": : :"memory")
   42.95 -#define rmb()	mb()
   42.96 -
   42.97 -#ifdef CONFIG_X86_OOSTORE
   42.98 -#define wmb() 	__asm__ __volatile__ ("lock; addl $0,0(%%esp)": : :"memory")
   42.99 -#else
  42.100 -#define wmb()	__asm__ __volatile__ ("": : :"memory")
  42.101 -#endif
  42.102 -
  42.103 -#ifdef CONFIG_SMP
  42.104 -#define smp_mb()	mb()
  42.105 -#define smp_rmb()	rmb()
  42.106 -#define smp_wmb()	wmb()
  42.107 -#else
  42.108 -#define smp_mb()	barrier()
  42.109 -#define smp_rmb()	barrier()
  42.110 -#define smp_wmb()	barrier()
  42.111 -#endif
  42.112 -
  42.113 +#define mb() 	asm volatile("mfence":::"memory")
  42.114 +#define rmb()	asm volatile("lfence":::"memory")
  42.115 +#define wmb()	asm volatile("sfence":::"memory")
  42.116  #define set_mb(var, value) do { xchg(&var, value); } while (0)
  42.117  #define set_wmb(var, value) do { var = value; wmb(); } while (0)
  42.118  
  42.119 +#define warn_if_not_ulong(x) do { unsigned long foo; (void) (&(x) == &foo); } while (0)
  42.120 +
  42.121  /* interrupt control.. */
  42.122 -#define __save_flags(x)		__asm__ __volatile__("pushfl ; popl %0":"=g" (x): /* no input */)
  42.123 -#define __restore_flags(x) 	__asm__ __volatile__("pushl %0 ; popfl": /* no output */ :"g" (x):"memory", "cc")
  42.124 +#define __save_flags(x)		do { warn_if_not_ulong(x); __asm__ __volatile__("# save_flags \n\t pushfq ; popq %q0":"=g" (x): /* no input */ :"memory"); } while (0)
  42.125 +#define __restore_flags(x) 	__asm__ __volatile__("# restore_flags \n\t pushq %0 ; popfq": /* no output */ :"g" (x):"memory", "cc")
  42.126  #define __cli() 		__asm__ __volatile__("cli": : :"memory")
  42.127  #define __sti()			__asm__ __volatile__("sti": : :"memory")
  42.128  /* used in the idle loop; sti takes one instruction cycle to complete */
  42.129  #define safe_halt()		__asm__ __volatile__("sti; hlt": : :"memory")
  42.130  
  42.131  /* For spinlocks etc */
  42.132 -#define local_irq_save(x)	__asm__ __volatile__("pushfl ; popl %0 ; cli":"=g" (x): /* no input */ :"memory")
  42.133 -#define local_irq_restore(x)	__restore_flags(x)
  42.134 +#define local_irq_save(x) 	do { warn_if_not_ulong(x); __asm__ __volatile__("# local_irq_save \n\t pushfq ; popq %0 ; cli":"=g" (x): /* no input */ :"memory"); } while (0)
  42.135 +#define local_irq_set(x) 	do { warn_if_not_ulong(x); __asm__ __volatile__("# local_irq_set \n\t pushfq ; popq %0 ; sti":"=g" (x): /* no input */ :"memory"); } while (0)
  42.136 +#define local_irq_restore(x)	__asm__ __volatile__("# local_irq_restore \n\t pushq %0 ; popfq": /* no output */ :"g" (x):"memory")
  42.137  #define local_irq_disable()	__cli()
  42.138  #define local_irq_enable()	__sti()
  42.139  
  42.140 @@ -195,6 +207,9 @@ extern void __global_restore_flags(unsig
  42.141  
  42.142  #endif
  42.143  
  42.144 +/* Default simics "magic" breakpoint */
  42.145 +#define icebp() asm volatile("xchg %%bx,%%bx" ::: "ebx")
  42.146 +
  42.147  /*
  42.148   * disable hlt during certain critical i/o operations
  42.149   */
  42.150 @@ -202,7 +217,4 @@ extern void __global_restore_flags(unsig
  42.151  void disable_hlt(void);
  42.152  void enable_hlt(void);
  42.153  
  42.154 -#define BROKEN_ACPI_Sx		0x0001
  42.155 -#define BROKEN_INIT_AFTER_S1	0x0002
  42.156 -
  42.157  #endif
    43.1 --- a/xen/include/asm-x86_64/timex.h	Wed Mar 10 13:44:42 2004 +0000
    43.2 +++ b/xen/include/asm-x86_64/timex.h	Wed Mar 10 13:46:20 2004 +0000
    43.3 @@ -1,38 +1,23 @@
    43.4  /*
    43.5 - * linux/include/asm-i386/timex.h
    43.6 + * linux/include/asm-x8664/timex.h
    43.7   *
    43.8 - * i386 architecture timex specifications
    43.9 + * x8664 architecture timex specifications
   43.10   */
   43.11 -#ifndef _ASMi386_TIMEX_H
   43.12 -#define _ASMi386_TIMEX_H
   43.13 +#ifndef _ASMx8664_TIMEX_H
   43.14 +#define _ASMx8664_TIMEX_H
   43.15  
   43.16  #include <linux/config.h>
   43.17  #include <asm/msr.h>
   43.18  
   43.19 -#ifdef CONFIG_MELAN
   43.20 -#  define CLOCK_TICK_RATE 1189200 /* AMD Elan has different frequency! */
   43.21 -#else
   43.22 -#  define CLOCK_TICK_RATE 1193180 /* Underlying HZ */
   43.23 -#endif
   43.24 -
   43.25 -#define CLOCK_TICK_FACTOR	20	/* Factor of both 1000000 and CLOCK_TICK_RATE */
   43.26 -#define FINETUNE ((((((long)LATCH * HZ - CLOCK_TICK_RATE) << SHIFT_HZ) * \
   43.27 -	(1000000/CLOCK_TICK_FACTOR) / (CLOCK_TICK_RATE/CLOCK_TICK_FACTOR)) \
   43.28 -		<< (SHIFT_SCALE-SHIFT_HZ)) / HZ)
   43.29 +#define CLOCK_TICK_RATE (vxtime_hz)
   43.30 +#define FINETUNE	((((((long)LATCH * HZ - CLOCK_TICK_RATE) << SHIFT_HZ) * \
   43.31 +			1000000 / CLOCK_TICK_RATE) << (SHIFT_SCALE - SHIFT_HZ)) / HZ)
   43.32  
   43.33  /*
   43.34 - * Standard way to access the cycle counter on i586+ CPUs.
   43.35 - * Currently only used on SMP.
   43.36 - *
   43.37 - * If you really have a SMP machine with i486 chips or older,
   43.38 - * compile for that, and this will just always return zero.
   43.39 - * That's ok, it just means that the nicer scheduling heuristics
   43.40 - * won't work for you.
   43.41 - *
   43.42   * We only use the low 32 bits, and we'd simply better make sure
   43.43   * that we reschedule before that wraps. Scheduling at least every
   43.44   * four billion cycles just basically sounds like a good idea,
   43.45 - * regardless of how fast the machine is. 
   43.46 + * regardless of how fast the machine is.
   43.47   */
   43.48  typedef unsigned long long cycles_t;
   43.49  
   43.50 @@ -40,19 +25,43 @@ extern cycles_t cacheflush_time;
   43.51  
   43.52  static inline cycles_t get_cycles (void)
   43.53  {
   43.54 -#ifndef CONFIG_X86_TSC
   43.55 -	return 0;
   43.56 -#else
   43.57  	unsigned long long ret;
   43.58 -
   43.59  	rdtscll(ret);
   43.60  	return ret;
   43.61 -#endif
   43.62  }
   43.63  
   43.64 -extern unsigned long cpu_khz;
   43.65 +extern unsigned int cpu_khz;
   43.66 +
   43.67 +/*
   43.68 + * Documentation on HPET can be found at:
   43.69 + *      http://www.intel.com/ial/home/sp/pcmmspec.htm
   43.70 + *      ftp://download.intel.com/ial/home/sp/mmts098.pdf
   43.71 + */
   43.72 +
   43.73 +#define HPET_ID		0x000
   43.74 +#define HPET_PERIOD	0x004
   43.75 +#define HPET_CFG	0x010
   43.76 +#define HPET_STATUS	0x020
   43.77 +#define HPET_COUNTER	0x0f0
   43.78 +#define HPET_T0_CFG	0x100
   43.79 +#define HPET_T0_CMP	0x108
   43.80 +#define HPET_T0_ROUTE	0x110
   43.81  
   43.82 -#define vxtime_lock()		do {} while (0)
   43.83 -#define vxtime_unlock()		do {} while (0)
   43.84 +#define HPET_ID_VENDOR	0xffff0000
   43.85 +#define HPET_ID_LEGSUP	0x00008000
   43.86 +#define HPET_ID_NUMBER	0x00000f00
   43.87 +#define HPET_ID_REV	0x000000ff
   43.88 +
   43.89 +#define HPET_CFG_ENABLE	0x001
   43.90 +#define HPET_CFG_LEGACY	0x002
   43.91 +
   43.92 +#define HPET_T0_ENABLE		0x004
   43.93 +#define HPET_T0_PERIODIC	0x008
   43.94 +#define HPET_T0_SETVAL		0x040
   43.95 +#define HPET_T0_32BIT		0x100
   43.96 +
   43.97 +/*extern struct vxtime_data vxtime; */
   43.98 +extern unsigned long vxtime_hz;
   43.99 +extern unsigned long hpet_address;
  43.100  
  43.101  #endif
    44.1 --- a/xen/include/asm-x86_64/types.h	Wed Mar 10 13:44:42 2004 +0000
    44.2 +++ b/xen/include/asm-x86_64/types.h	Wed Mar 10 13:46:20 2004 +0000
    44.3 @@ -1,5 +1,5 @@
    44.4 -#ifndef _I386_TYPES_H
    44.5 -#define _I386_TYPES_H
    44.6 +#ifndef _X86_64_TYPES_H
    44.7 +#define _X86_64_TYPES_H
    44.8  
    44.9  typedef unsigned short umode_t;
   44.10  
   44.11 @@ -17,10 +17,8 @@ typedef unsigned short __u16;
   44.12  typedef __signed__ int __s32;
   44.13  typedef unsigned int __u32;
   44.14  
   44.15 -#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
   44.16  typedef __signed__ long long __s64;
   44.17  typedef unsigned long long __u64;
   44.18 -#endif
   44.19  
   44.20  #include <xeno/config.h>
   44.21  
   44.22 @@ -36,15 +34,9 @@ typedef unsigned int u32;
   44.23  typedef signed long long s64;
   44.24  typedef unsigned long long u64;
   44.25  
   44.26 -#define BITS_PER_LONG 32
   44.27 -
   44.28 -/* DMA addresses come in generic and 64-bit flavours.  */
   44.29 +#define BITS_PER_LONG 64
   44.30  
   44.31 -#ifdef CONFIG_HIGHMEM
   44.32 +typedef u64 dma64_addr_t;
   44.33  typedef u64 dma_addr_t;
   44.34 -#else
   44.35 -typedef u32 dma_addr_t;
   44.36 -#endif
   44.37 -typedef u64 dma64_addr_t;
   44.38  
   44.39  #endif
    45.1 --- a/xen/include/asm-x86_64/uaccess.h	Wed Mar 10 13:44:42 2004 +0000
    45.2 +++ b/xen/include/asm-x86_64/uaccess.h	Wed Mar 10 13:46:20 2004 +0000
    45.3 @@ -1,13 +1,13 @@
    45.4 -#ifndef __i386_UACCESS_H
    45.5 -#define __i386_UACCESS_H
    45.6 +#ifndef __X86_64_UACCESS_H
    45.7 +#define __X86_64_UACCESS_H
    45.8  
    45.9  /*
   45.10   * User space memory access functions
   45.11   */
   45.12  #include <linux/config.h>
   45.13 -#include <linux/errno.h>
   45.14  #include <linux/sched.h>
   45.15  #include <linux/prefetch.h>
   45.16 +#include <linux/errno.h>
   45.17  #include <asm/page.h>
   45.18  
   45.19  #define VERIFY_READ 0
   45.20 @@ -23,8 +23,7 @@
   45.21  
   45.22  #define MAKE_MM_SEG(s)	((mm_segment_t) { (s) })
   45.23  
   45.24 -
   45.25 -#define KERNEL_DS	MAKE_MM_SEG(0xFFFFFFFF)
   45.26 +#define KERNEL_DS	MAKE_MM_SEG(0xFFFFFFFFFFFFFFFF)
   45.27  #define USER_DS		MAKE_MM_SEG(PAGE_OFFSET)
   45.28  
   45.29  #define get_ds()	(KERNEL_DS)
   45.30 @@ -33,23 +32,22 @@
   45.31  
   45.32  #define segment_eq(a,b)	((a).seg == (b).seg)
   45.33  
   45.34 -extern int __verify_write(const void *, unsigned long);
   45.35 -
   45.36 -#define __addr_ok(addr) ((unsigned long)(addr) < (current->addr_limit.seg))
   45.37 +#define __addr_ok(addr) (!((unsigned long)(addr) & (current->addr_limit.seg)))
   45.38  
   45.39  /*
   45.40 - * Uhhuh, this needs 33-bit arithmetic. We have a carry..
   45.41 + * Uhhuh, this needs 65-bit arithmetic. We have a carry..
   45.42   */
   45.43 -#define __range_ok(addr,size) ({ \
   45.44 +#define __range_not_ok(addr,size) ({ \
   45.45  	unsigned long flag,sum; \
   45.46 -	asm("addl %3,%1 ; sbbl %0,%0; cmpl %1,%4; sbbl $0,%0" \
   45.47 +	asm("# range_ok\n\r" \
   45.48 +		"addq %3,%1 ; sbbq %0,%0 ; cmpq %1,%4 ; sbbq $0,%0"  \
   45.49  		:"=&r" (flag), "=r" (sum) \
   45.50 -		:"1" (addr),"g" ((int)(size)),"g" (current->addr_limit.seg)); \
   45.51 +		:"1" (addr),"g" ((long)(size)),"g" (current->addr_limit.seg)); \
   45.52  	flag; })
   45.53  
   45.54 -#define access_ok(type,addr,size) (__range_ok(addr,size) == 0)
   45.55 +#define access_ok(type,addr,size) (__range_not_ok(addr,size) == 0)
   45.56  
   45.57 -static inline int verify_area(int type, const void * addr, unsigned long size)
   45.58 +extern inline int verify_area(int type, const void * addr, unsigned long size)
   45.59  {
   45.60  	return access_ok(type,addr,size) ? 0 : -EFAULT;
   45.61  }
   45.62 @@ -73,9 +71,6 @@ struct exception_table_entry
   45.63  	unsigned long insn, fixup;
   45.64  };
   45.65  
   45.66 -/* Returns 0 if exception not found and fixup otherwise.  */
   45.67 -extern unsigned long search_exception_table(unsigned long);
   45.68 -
   45.69  
   45.70  /*
   45.71   * These are the main single-value transfer routines.  They automatically
   45.72 @@ -84,7 +79,7 @@ extern unsigned long search_exception_ta
   45.73   * This gets kind of ugly. We want to return _two_ values in "get_user()"
   45.74   * and yet we don't want to do any pointers, because that is too much
   45.75   * of a performance impact. Thus we have a few rather ugly macros here,
   45.76 - * and hide all the uglyness from the user.
   45.77 + * and hide all the ugliness from the user.
   45.78   *
   45.79   * The "__xxx" versions of the user access functions are versions that
   45.80   * do not verify the address space, that must have been done previously
   45.81 @@ -95,24 +90,29 @@ extern unsigned long search_exception_ta
   45.82  extern void __get_user_1(void);
   45.83  extern void __get_user_2(void);
   45.84  extern void __get_user_4(void);
   45.85 +extern void __get_user_8(void);
   45.86  
   45.87  #define __get_user_x(size,ret,x,ptr) \
   45.88  	__asm__ __volatile__("call __get_user_" #size \
   45.89  		:"=a" (ret),"=d" (x) \
   45.90 -		:"0" (ptr))
   45.91 +		:"0" (ptr) \
   45.92 +		:"rbx")
   45.93  
   45.94  /* Careful: we have to cast the result to the type of the pointer for sign reasons */
   45.95  #define get_user(x,ptr)							\
   45.96 -({	int __ret_gu=1,__val_gu;						\
   45.97 +({	long __val_gu;							\
   45.98 +	int __ret_gu=1;							\
   45.99  	switch(sizeof (*(ptr))) {					\
  45.100 -	case 1: __ret_gu=copy_from_user(&__val_gu,ptr,1); break;			\
  45.101 -	case 2: __ret_gu=copy_from_user(&__val_gu,ptr,2); break;                 \
  45.102 -	case 4: __ret_gu=copy_from_user(&__val_gu,ptr,4); break;                 \
  45.103 -	default: __ret_gu=copy_from_user(&__val_gu,ptr,8); break;                 \
  45.104 -	/*case 1:  __get_user_x(1,__ret_gu,__val_gu,ptr); break;*/		\
  45.105 -	/*case 2:  __get_user_x(2,__ret_gu,__val_gu,ptr); break;*/		\
  45.106 -	/*case 4:  __get_user_x(4,__ret_gu,__val_gu,ptr); break;*/		\
  45.107 -	/*default: __get_user_x(X,__ret_gu,__val_gu,ptr); break;*/		\
  45.108 +	case 1:  _ret_gu=copy_from_user(&__val_gu,ptr,1);break;		\
  45.109 +	case 2:  _ret_gu=copy_from_user(&__val_gu,ptr,2);break;		\
  45.110 +	case 4:  _ret_gu=copy_from_user(&__val_gu,ptr,4);break;		\
  45.111 +	case 8:  _ret_gu=copy_from_user(&__val_gu,ptr,8);break;		\
  45.112 +	default: _ret_gu=copy_from_user(&__val_gu,ptr,sizeof(*(ptr)));break;\
  45.113 +	/*case 1:  __get_user_x(1,__ret_gu,__val_gu,ptr); break;*/	\
  45.114 +	/*case 2:  __get_user_x(2,__ret_gu,__val_gu,ptr); break;*/	\
  45.115 +	/*case 4:  __get_user_x(4,__ret_gu,__val_gu,ptr); break;*/	\
  45.116 +	/*case 8:  __get_user_x(8,__ret_gu,__val_gu,ptr); break;*/	\
  45.117 +	/*default: __get_user_bad(); break;*/				\
  45.118  	}								\
  45.119  	(x) = (__typeof__(*(ptr)))__val_gu;				\
  45.120  	__ret_gu;							\
  45.121 @@ -125,6 +125,12 @@ extern void __put_user_8(void);
  45.122  
  45.123  extern void __put_user_bad(void);
  45.124  
  45.125 +#define __put_user_x(size,ret,x,ptr)					\
  45.126 +	__asm__ __volatile__("call __put_user_" #size			\
  45.127 +		:"=a" (ret)						\
  45.128 +		:"0" (ptr),"d" (x)					\
  45.129 +		:"rbx")
  45.130 +
  45.131  #define put_user(x,ptr)							\
  45.132    __put_user_check((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr)))
  45.133  
  45.134 @@ -135,7 +141,7 @@ extern void __put_user_bad(void);
  45.135  
  45.136  #define __put_user_nocheck(x,ptr,size)			\
  45.137  ({							\
  45.138 -	long __pu_err;					\
  45.139 +	int __pu_err;					\
  45.140  	__put_user_size((x),(ptr),(size),__pu_err);	\
  45.141  	__pu_err;					\
  45.142  })
  45.143 @@ -143,42 +149,26 @@ extern void __put_user_bad(void);
  45.144  
  45.145  #define __put_user_check(x,ptr,size)			\
  45.146  ({							\
  45.147 -	long __pu_err = -EFAULT;					\
  45.148 +	int __pu_err = -EFAULT;				\
  45.149  	__typeof__(*(ptr)) *__pu_addr = (ptr);		\
  45.150  	if (access_ok(VERIFY_WRITE,__pu_addr,size))	\
  45.151  		__put_user_size((x),__pu_addr,(size),__pu_err);	\
  45.152  	__pu_err;					\
  45.153 -})							
  45.154 -
  45.155 -#define __put_user_u64(x, addr, err)				\
  45.156 -	__asm__ __volatile__(					\
  45.157 -		"1:	movl %%eax,0(%2)\n"			\
  45.158 -		"2:	movl %%edx,4(%2)\n"			\
  45.159 -		"3:\n"						\
  45.160 -		".section .fixup,\"ax\"\n"			\
  45.161 -		"4:	movl %3,%0\n"				\
  45.162 -		"	jmp 3b\n"				\
  45.163 -		".previous\n"					\
  45.164 -		".section __ex_table,\"a\"\n"			\
  45.165 -		"	.align 4\n"				\
  45.166 -		"	.long 1b,4b\n"				\
  45.167 -		"	.long 2b,4b\n"				\
  45.168 -		".previous"					\
  45.169 -		: "=r"(err)					\
  45.170 -		: "A" (x), "r" (addr), "i"(-EFAULT), "0"(err))
  45.171 +})
  45.172  
  45.173  #define __put_user_size(x,ptr,size,retval)				\
  45.174  do {									\
  45.175  	retval = 0;							\
  45.176  	switch (size) {							\
  45.177 -	  case 1: __put_user_asm(x,ptr,retval,"b","b","iq"); break;	\
  45.178 -	  case 2: __put_user_asm(x,ptr,retval,"w","w","ir"); break;	\
  45.179 -	  case 4: __put_user_asm(x,ptr,retval,"l","","ir"); break;	\
  45.180 -	  case 8: __put_user_u64(x,ptr,retval); break;			\
  45.181 +	  case 1: __put_user_asm(x,ptr,retval,"b","b","iq",-EFAULT); break;\
  45.182 +	  case 2: __put_user_asm(x,ptr,retval,"w","w","ir",-EFAULT); break;\
  45.183 +	  case 4: __put_user_asm(x,ptr,retval,"l","k","ir",-EFAULT); break;\
  45.184 +	  case 8: __put_user_asm(x,ptr,retval,"q","","ir",-EFAULT); break;\
  45.185  	  default: __put_user_bad();					\
  45.186  	}								\
  45.187  } while (0)
  45.188  
  45.189 +/* FIXME: this hack is definitely wrong -AK */
  45.190  struct __large_struct { unsigned long buf[100]; };
  45.191  #define __m(x) (*(struct __large_struct *)(x))
  45.192  
  45.193 @@ -187,414 +177,138 @@ struct __large_struct { unsigned long bu
  45.194   * we do not write to any memory gcc knows about, so there are no
  45.195   * aliasing issues.
  45.196   */
  45.197 -#define __put_user_asm(x, addr, err, itype, rtype, ltype)	\
  45.198 -	__asm__ __volatile__(					\
  45.199 -		"1:	mov"itype" %"rtype"1,%2\n"		\
  45.200 -		"2:\n"						\
  45.201 -		".section .fixup,\"ax\"\n"			\
  45.202 -		"3:	movl %3,%0\n"				\
  45.203 -		"	jmp 2b\n"				\
  45.204 +#define __put_user_asm(x, addr, err, itype, rtype, ltype, errno)	\
  45.205 +	__asm__ __volatile__(				\
  45.206 +		"1:	mov"itype" %"rtype"1,%2\n"	\
  45.207 +		"2:\n"							\
  45.208 +		".section .fixup,\"ax\"\n"		\
  45.209 +		"3:	mov %3,%0\n"				\
  45.210 +		"	jmp 2b\n"					\
  45.211  		".previous\n"					\
  45.212 -		".section __ex_table,\"a\"\n"			\
  45.213 -		"	.align 4\n"				\
  45.214 -		"	.long 1b,3b\n"				\
  45.215 -		".previous"					\
  45.216 -		: "=r"(err)					\
  45.217 -		: ltype (x), "m"(__m(addr)), "i"(-EFAULT), "0"(err))
  45.218 +		".section __ex_table,\"a\"\n"	\
  45.219 +		"	.align 8\n"					\
  45.220 +		"	.quad 1b,3b\n"				\
  45.221 +		".previous"						\
  45.222 +		: "=r"(err)						\
  45.223 +		: ltype (x), "m"(__m(addr)), "i"(errno), "0"(err))
  45.224  
  45.225  
  45.226  #define __get_user_nocheck(x,ptr,size)				\
  45.227  ({								\
  45.228 -	long __gu_err, __gu_val;				\
  45.229 +	int __gu_err;						\
  45.230 +	long __gu_val;						\
  45.231  	__get_user_size(__gu_val,(ptr),(size),__gu_err);	\
  45.232  	(x) = (__typeof__(*(ptr)))__gu_val;			\
  45.233  	__gu_err;						\
  45.234  })
  45.235  
  45.236 -extern long __get_user_bad(void);
  45.237 +extern int __get_user_bad(void);
  45.238  
  45.239  #define __get_user_size(x,ptr,size,retval)				\
  45.240  do {									\
  45.241  	retval = 0;							\
  45.242  	switch (size) {							\
  45.243 -	  case 1: __get_user_asm(x,ptr,retval,"b","b","=q"); break;	\
  45.244 -	  case 2: __get_user_asm(x,ptr,retval,"w","w","=r"); break;	\
  45.245 -	  case 4: __get_user_asm(x,ptr,retval,"l","","=r"); break;	\
  45.246 +	  case 1: __get_user_asm(x,ptr,retval,"b","b","=q",-EFAULT); break;\
  45.247 +	  case 2: __get_user_asm(x,ptr,retval,"w","w","=r",-EFAULT); break;\
  45.248 +	  case 4: __get_user_asm(x,ptr,retval,"l","k","=r",-EFAULT); break;\
  45.249 +	  case 8: __get_user_asm(x,ptr,retval,"q","","=r",-EFAULT); break;\
  45.250  	  default: (x) = __get_user_bad();				\
  45.251  	}								\
  45.252  } while (0)
  45.253  
  45.254 -#define __get_user_asm(x, addr, err, itype, rtype, ltype)	\
  45.255 +#define __get_user_asm(x, addr, err, itype, rtype, ltype, errno)	\
  45.256  	__asm__ __volatile__(					\
  45.257  		"1:	mov"itype" %2,%"rtype"1\n"		\
  45.258  		"2:\n"						\
  45.259  		".section .fixup,\"ax\"\n"			\
  45.260 -		"3:	movl %3,%0\n"				\
  45.261 +		"3:	mov %3,%0\n"				\
  45.262  		"	xor"itype" %"rtype"1,%"rtype"1\n"	\
  45.263  		"	jmp 2b\n"				\
  45.264  		".previous\n"					\
  45.265  		".section __ex_table,\"a\"\n"			\
  45.266 -		"	.align 4\n"				\
  45.267 -		"	.long 1b,3b\n"				\
  45.268 +		"	.align 8\n"				\
  45.269 +		"	.quad 1b,3b\n"				\
  45.270  		".previous"					\
  45.271  		: "=r"(err), ltype (x)				\
  45.272 -		: "m"(__m(addr)), "i"(-EFAULT), "0"(err))
  45.273 -
  45.274 +		: "m"(__m(addr)), "i"(errno), "0"(err))
  45.275  
  45.276  /*
  45.277   * Copy To/From Userspace
  45.278   */
  45.279  
  45.280 -/* Generic arbitrary sized copy.  */
  45.281 -#define __copy_user(to,from,size)					\
  45.282 -do {									\
  45.283 -	int __d0, __d1;							\
  45.284 -	__asm__ __volatile__(						\
  45.285 -		"0:	rep; movsl\n"					\
  45.286 -		"	movl %3,%0\n"					\
  45.287 -		"1:	rep; movsb\n"					\
  45.288 -		"2:\n"							\
  45.289 -		".section .fixup,\"ax\"\n"				\
  45.290 -		"3:	lea 0(%3,%0,4),%0\n"				\
  45.291 -		"	jmp 2b\n"					\
  45.292 -		".previous\n"						\
  45.293 -		".section __ex_table,\"a\"\n"				\
  45.294 -		"	.align 4\n"					\
  45.295 -		"	.long 0b,3b\n"					\
  45.296 -		"	.long 1b,2b\n"					\
  45.297 -		".previous"						\
  45.298 -		: "=&c"(size), "=&D" (__d0), "=&S" (__d1)		\
  45.299 -		: "r"(size & 3), "0"(size / 4), "1"(to), "2"(from)	\
  45.300 -		: "memory");						\
  45.301 -} while (0)
  45.302 -
  45.303 -#define __copy_user_zeroing(to,from,size)				\
  45.304 -do {									\
  45.305 -	int __d0, __d1;							\
  45.306 -	__asm__ __volatile__(						\
  45.307 -		"0:	rep; movsl\n"					\
  45.308 -		"	movl %3,%0\n"					\
  45.309 -		"1:	rep; movsb\n"					\
  45.310 -		"2:\n"							\
  45.311 -		".section .fixup,\"ax\"\n"				\
  45.312 -		"3:	lea 0(%3,%0,4),%0\n"				\
  45.313 -		"4:	pushl %0\n"					\
  45.314 -		"	pushl %%eax\n"					\
  45.315 -		"	xorl %%eax,%%eax\n"				\
  45.316 -		"	rep; stosb\n"					\
  45.317 -		"	popl %%eax\n"					\
  45.318 -		"	popl %0\n"					\
  45.319 -		"	jmp 2b\n"					\
  45.320 -		".previous\n"						\
  45.321 -		".section __ex_table,\"a\"\n"				\
  45.322 -		"	.align 4\n"					\
  45.323 -		"	.long 0b,3b\n"					\
  45.324 -		"	.long 1b,4b\n"					\
  45.325 -		".previous"						\
  45.326 -		: "=&c"(size), "=&D" (__d0), "=&S" (__d1)		\
  45.327 -		: "r"(size & 3), "0"(size / 4), "1"(to), "2"(from)	\
  45.328 -		: "memory");						\
  45.329 -} while (0)
  45.330 -
  45.331 -/* We let the __ versions of copy_from/to_user inline, because they're often
  45.332 - * used in fast paths and have only a small space overhead.
  45.333 - */
  45.334 -static inline unsigned long
  45.335 -__generic_copy_from_user_nocheck(void *to, const void *from, unsigned long n)
  45.336 -{
  45.337 -	__copy_user_zeroing(to,from,n);
  45.338 -	return n;
  45.339 -}
  45.340 -
  45.341 -static inline unsigned long
  45.342 -__generic_copy_to_user_nocheck(void *to, const void *from, unsigned long n)
  45.343 -{
  45.344 -	__copy_user(to,from,n);
  45.345 -	return n;
  45.346 -}
  45.347 -
  45.348 +/* Handles exceptions in both to and from, but doesn't do access_ok */
  45.349 +extern unsigned long copy_user_generic(void *to, const void *from, unsigned len); 
  45.350  
  45.351 -/* Optimize just a little bit when we know the size of the move. */
  45.352 -#define __constant_copy_user(to, from, size)			\
  45.353 -do {								\
  45.354 -	int __d0, __d1;						\
  45.355 -	switch (size & 3) {					\
  45.356 -	default:						\
  45.357 -		__asm__ __volatile__(				\
  45.358 -			"0:	rep; movsl\n"			\
  45.359 -			"1:\n"					\
  45.360 -			".section .fixup,\"ax\"\n"		\
  45.361 -			"2:	shl $2,%0\n"			\
  45.362 -			"	jmp 1b\n"			\
  45.363 -			".previous\n"				\
  45.364 -			".section __ex_table,\"a\"\n"		\
  45.365 -			"	.align 4\n"			\
  45.366 -			"	.long 0b,2b\n"			\
  45.367 -			".previous"				\
  45.368 -			: "=c"(size), "=&S" (__d0), "=&D" (__d1)\
  45.369 -			: "1"(from), "2"(to), "0"(size/4)	\
  45.370 -			: "memory");				\
  45.371 -		break;						\
  45.372 -	case 1:							\
  45.373 -		__asm__ __volatile__(				\
  45.374 -			"0:	rep; movsl\n"			\
  45.375 -			"1:	movsb\n"			\
  45.376 -			"2:\n"					\
  45.377 -			".section .fixup,\"ax\"\n"		\
  45.378 -			"3:	shl $2,%0\n"			\
  45.379 -			"4:	incl %0\n"			\
  45.380 -			"	jmp 2b\n"			\
  45.381 -			".previous\n"				\
  45.382 -			".section __ex_table,\"a\"\n"		\
  45.383 -			"	.align 4\n"			\
  45.384 -			"	.long 0b,3b\n"			\
  45.385 -			"	.long 1b,4b\n"			\
  45.386 -			".previous"				\
  45.387 -			: "=c"(size), "=&S" (__d0), "=&D" (__d1)\
  45.388 -			: "1"(from), "2"(to), "0"(size/4)	\
  45.389 -			: "memory");				\
  45.390 -		break;						\
  45.391 -	case 2:							\
  45.392 -		__asm__ __volatile__(				\
  45.393 -			"0:	rep; movsl\n"			\
  45.394 -			"1:	movsw\n"			\
  45.395 -			"2:\n"					\
  45.396 -			".section .fixup,\"ax\"\n"		\
  45.397 -			"3:	shl $2,%0\n"			\
  45.398 -			"4:	addl $2,%0\n"			\
  45.399 -			"	jmp 2b\n"			\
  45.400 -			".previous\n"				\
  45.401 -			".section __ex_table,\"a\"\n"		\
  45.402 -			"	.align 4\n"			\
  45.403 -			"	.long 0b,3b\n"			\
  45.404 -			"	.long 1b,4b\n"			\
  45.405 -			".previous"				\
  45.406 -			: "=c"(size), "=&S" (__d0), "=&D" (__d1)\
  45.407 -			: "1"(from), "2"(to), "0"(size/4)	\
  45.408 -			: "memory");				\
  45.409 -		break;						\
  45.410 -	case 3:							\
  45.411 -		__asm__ __volatile__(				\
  45.412 -			"0:	rep; movsl\n"			\
  45.413 -			"1:	movsw\n"			\
  45.414 -			"2:	movsb\n"			\
  45.415 -			"3:\n"					\
  45.416 -			".section .fixup,\"ax\"\n"		\
  45.417 -			"4:	shl $2,%0\n"			\
  45.418 -			"5:	addl $2,%0\n"			\
  45.419 -			"6:	incl %0\n"			\
  45.420 -			"	jmp 3b\n"			\
  45.421 -			".previous\n"				\
  45.422 -			".section __ex_table,\"a\"\n"		\
  45.423 -			"	.align 4\n"			\
  45.424 -			"	.long 0b,4b\n"			\
  45.425 -			"	.long 1b,5b\n"			\
  45.426 -			"	.long 2b,6b\n"			\
  45.427 -			".previous"				\
  45.428 -			: "=c"(size), "=&S" (__d0), "=&D" (__d1)\
  45.429 -			: "1"(from), "2"(to), "0"(size/4)	\
  45.430 -			: "memory");				\
  45.431 -		break;						\
  45.432 -	}							\
  45.433 -} while (0)
  45.434 +extern unsigned long copy_to_user(void *to, const void *from, unsigned len); 
  45.435 +extern unsigned long copy_from_user(void *to, const void *from, unsigned len); 
  45.436  
  45.437 -/* Optimize just a little bit when we know the size of the move. */
  45.438 -#define __constant_copy_user_zeroing(to, from, size)		\
  45.439 -do {								\
  45.440 -	int __d0, __d1;						\
  45.441 -	switch (size & 3) {					\
  45.442 -	default:						\
  45.443 -		__asm__ __volatile__(				\
  45.444 -			"0:	rep; movsl\n"			\
  45.445 -			"1:\n"					\
  45.446 -			".section .fixup,\"ax\"\n"		\
  45.447 -			"2:	pushl %0\n"			\
  45.448 -			"	pushl %%eax\n"			\
  45.449 -			"	xorl %%eax,%%eax\n"		\
  45.450 -			"	rep; stosl\n"			\
  45.451 -			"	popl %%eax\n"			\
  45.452 -			"	popl %0\n"			\
  45.453 -			"	shl $2,%0\n"			\
  45.454 -			"	jmp 1b\n"			\
  45.455 -			".previous\n"				\
  45.456 -			".section __ex_table,\"a\"\n"		\
  45.457 -			"	.align 4\n"			\
  45.458 -			"	.long 0b,2b\n"			\
  45.459 -			".previous"				\
  45.460 -			: "=c"(size), "=&S" (__d0), "=&D" (__d1)\
  45.461 -			: "1"(from), "2"(to), "0"(size/4)	\
  45.462 -			: "memory");				\
  45.463 -		break;						\
  45.464 -	case 1:							\
  45.465 -		__asm__ __volatile__(				\
  45.466 -			"0:	rep; movsl\n"			\
  45.467 -			"1:	movsb\n"			\
  45.468 -			"2:\n"					\
  45.469 -			".section .fixup,\"ax\"\n"		\
  45.470 -			"3:	pushl %0\n"			\
  45.471 -			"	pushl %%eax\n"			\
  45.472 -			"	xorl %%eax,%%eax\n"		\
  45.473 -			"	rep; stosl\n"			\
  45.474 -			"	stosb\n"			\
  45.475 -			"	popl %%eax\n"			\
  45.476 -			"	popl %0\n"			\
  45.477 -			"	shl $2,%0\n"			\
  45.478 -			"	incl %0\n"			\
  45.479 -			"	jmp 2b\n"			\
  45.480 -			"4:	pushl %%eax\n"			\
  45.481 -			"	xorl %%eax,%%eax\n"		\
  45.482 -			"	stosb\n"			\
  45.483 -			"	popl %%eax\n"			\
  45.484 -			"	incl %0\n"			\
  45.485 -			"	jmp 2b\n"			\
  45.486 -			".previous\n"				\
  45.487 -			".section __ex_table,\"a\"\n"		\
  45.488 -			"	.align 4\n"			\
  45.489 -			"	.long 0b,3b\n"			\
  45.490 -			"	.long 1b,4b\n"			\
  45.491 -			".previous"				\
  45.492 -			: "=c"(size), "=&S" (__d0), "=&D" (__d1)\
  45.493 -			: "1"(from), "2"(to), "0"(size/4)	\
  45.494 -			: "memory");				\
  45.495 -		break;						\
  45.496 -	case 2:							\
  45.497 -		__asm__ __volatile__(				\
  45.498 -			"0:	rep; movsl\n"			\
  45.499 -			"1:	movsw\n"			\
  45.500 -			"2:\n"					\
  45.501 -			".section .fixup,\"ax\"\n"		\
  45.502 -			"3:	pushl %0\n"			\
  45.503 -			"	pushl %%eax\n"			\
  45.504 -			"	xorl %%eax,%%eax\n"		\
  45.505 -			"	rep; stosl\n"			\
  45.506 -			"	stosw\n"			\
  45.507 -			"	popl %%eax\n"			\
  45.508 -			"	popl %0\n"			\
  45.509 -			"	shl $2,%0\n"			\
  45.510 -			"	addl $2,%0\n"			\
  45.511 -			"	jmp 2b\n"			\
  45.512 -			"4:	pushl %%eax\n"			\
  45.513 -			"	xorl %%eax,%%eax\n"		\
  45.514 -			"	stosw\n"			\
  45.515 -			"	popl %%eax\n"			\
  45.516 -			"	addl $2,%0\n"			\
  45.517 -			"	jmp 2b\n"			\
  45.518 -			".previous\n"				\
  45.519 -			".section __ex_table,\"a\"\n"		\
  45.520 -			"	.align 4\n"			\
  45.521 -			"	.long 0b,3b\n"			\
  45.522 -			"	.long 1b,4b\n"			\
  45.523 -			".previous"				\
  45.524 -			: "=c"(size), "=&S" (__d0), "=&D" (__d1)\
  45.525 -			: "1"(from), "2"(to), "0"(size/4)	\
  45.526 -			: "memory");				\
  45.527 -		break;						\
  45.528 -	case 3:							\
  45.529 -		__asm__ __volatile__(				\
  45.530 -			"0:	rep; movsl\n"			\
  45.531 -			"1:	movsw\n"			\
  45.532 -			"2:	movsb\n"			\
  45.533 -			"3:\n"					\
  45.534 -			".section .fixup,\"ax\"\n"		\
  45.535 -			"4:	pushl %0\n"			\
  45.536 -			"	pushl %%eax\n"			\
  45.537 -			"	xorl %%eax,%%eax\n"		\
  45.538 -			"	rep; stosl\n"			\
  45.539 -			"	stosw\n"			\
  45.540 -			"	stosb\n"			\
  45.541 -			"	popl %%eax\n"			\
  45.542 -			"	popl %0\n"			\
  45.543 -			"	shl $2,%0\n"			\
  45.544 -			"	addl $3,%0\n"			\
  45.545 -			"	jmp 2b\n"			\
  45.546 -			"5:	pushl %%eax\n"			\
  45.547 -			"	xorl %%eax,%%eax\n"		\
  45.548 -			"	stosw\n"			\
  45.549 -			"	stosb\n"			\
  45.550 -			"	popl %%eax\n"			\
  45.551 -			"	addl $3,%0\n"			\
  45.552 -			"	jmp 2b\n"			\
  45.553 -			"6:	pushl %%eax\n"			\
  45.554 -			"	xorl %%eax,%%eax\n"		\
  45.555 -			"	stosb\n"			\
  45.556 -			"	popl %%eax\n"			\
  45.557 -			"	incl %0\n"			\
  45.558 -			"	jmp 3b\n"			\
  45.559 -			".previous\n"				\
  45.560 -			".section __ex_table,\"a\"\n"		\
  45.561 -			"	.align 4\n"			\
  45.562 -			"	.long 0b,4b\n"			\
  45.563 -			"	.long 1b,5b\n"			\
  45.564 -			"	.long 2b,6b\n"			\
  45.565 -			".previous"				\
  45.566 -			: "=c"(size), "=&S" (__d0), "=&D" (__d1)\
  45.567 -			: "1"(from), "2"(to), "0"(size/4)	\
  45.568 -			: "memory");				\
  45.569 -		break;						\
  45.570 -	}							\
  45.571 -} while (0)
  45.572 +static inline int __copy_from_user(void *dst, const void *src, unsigned size) 
  45.573 +{ 
  45.574 +	if (!__builtin_constant_p(size))
  45.575 +		return copy_user_generic(dst,src,size);
  45.576 +	int ret = 0; 
  45.577 +	switch (size) { 
  45.578 +	case 1:__get_user_asm(*(u8*)dst,(u8 *)src,ret,"b","b","=q",1); 
  45.579 +		return ret;
  45.580 +	case 2:__get_user_asm(*(u16*)dst,(u16*)src,ret,"w","w","=r",2);
  45.581 +		return ret;
  45.582 +	case 4:__get_user_asm(*(u32*)dst,(u32*)src,ret,"l","k","=r",4);
  45.583 +		return ret;
  45.584 +	case 8:__get_user_asm(*(u64*)dst,(u64*)src,ret,"q","","=r",8);
  45.585 +		return ret; 
  45.586 +	case 10:
  45.587 +	       	__get_user_asm(*(u64*)dst,(u64*)src,ret,"q","","=r",16);
  45.588 +		if (ret) return ret;
  45.589 +		__get_user_asm(*(u16*)(8+dst),(u16*)(8+src),ret,"w","w","=r",2);
  45.590 +		return ret; 
  45.591 +	case 16:
  45.592 +		__get_user_asm(*(u64*)dst,(u64*)src,ret,"q","","=r",16);
  45.593 +		if (ret) return ret;
  45.594 +		__get_user_asm(*(u64*)(8+dst),(u64*)(8+src),ret,"q","","=r",8);
  45.595 +		return ret; 
  45.596 +	default:
  45.597 +		return copy_user_generic(dst,src,size); 
  45.598 +	}
  45.599 +}	
  45.600  
  45.601 -unsigned long __generic_copy_to_user(void *, const void *, unsigned long);
  45.602 -unsigned long __generic_copy_from_user(void *, const void *, unsigned long);
  45.603 -
  45.604 -static inline unsigned long
  45.605 -__constant_copy_to_user(void *to, const void *from, unsigned long n)
  45.606 -{
  45.607 -	prefetch(from);
  45.608 -	if (access_ok(VERIFY_WRITE, to, n))
  45.609 -		__constant_copy_user(to,from,n);
  45.610 -	return n;
  45.611 -}
  45.612 -
  45.613 -static inline unsigned long
  45.614 -__constant_copy_from_user(void *to, const void *from, unsigned long n)
  45.615 -{
  45.616 -	if (access_ok(VERIFY_READ, from, n))
  45.617 -		__constant_copy_user_zeroing(to,from,n);
  45.618 -	else
  45.619 -		memset(to, 0, n);
  45.620 -	return n;
  45.621 -}
  45.622 -
  45.623 -static inline unsigned long
  45.624 -__constant_copy_to_user_nocheck(void *to, const void *from, unsigned long n)
  45.625 -{
  45.626 -	__constant_copy_user(to,from,n);
  45.627 -	return n;
  45.628 -}
  45.629 -
  45.630 -static inline unsigned long
  45.631 -__constant_copy_from_user_nocheck(void *to, const void *from, unsigned long n)
  45.632 -{
  45.633 -	__constant_copy_user_zeroing(to,from,n);
  45.634 -	return n;
  45.635 -}
  45.636 -
  45.637 -#define copy_to_user(to,from,n)				\
  45.638 -	(__builtin_constant_p(n) ?			\
  45.639 -	 __constant_copy_to_user((to),(from),(n)) :	\
  45.640 -	 __generic_copy_to_user((to),(from),(n)))
  45.641 -
  45.642 -#define copy_from_user(to,from,n)			\
  45.643 -	(__builtin_constant_p(n) ?			\
  45.644 -	 __constant_copy_from_user((to),(from),(n)) :	\
  45.645 -	 __generic_copy_from_user((to),(from),(n)))
  45.646 -
  45.647 -#define __copy_to_user(to,from,n)			\
  45.648 -	(__builtin_constant_p(n) ?			\
  45.649 -	 __constant_copy_to_user_nocheck((to),(from),(n)) :	\
  45.650 -	 __generic_copy_to_user_nocheck((to),(from),(n)))
  45.651 -
  45.652 -#define __copy_from_user(to,from,n)			\
  45.653 -	(__builtin_constant_p(n) ?			\
  45.654 -	 __constant_copy_from_user_nocheck((to),(from),(n)) :	\
  45.655 -	 __generic_copy_from_user_nocheck((to),(from),(n)))
  45.656 +static inline int __copy_to_user(void *dst, const void *src, unsigned size) 
  45.657 +{ 
  45.658 +	if (!__builtin_constant_p(size))
  45.659 +		return copy_user_generic(dst,src,size);
  45.660 +	int ret = 0; 
  45.661 +	switch (size) { 
  45.662 +	case 1:__put_user_asm(*(u8*)src,(u8 *)dst,ret,"b","b","iq",1); 
  45.663 +		return ret;
  45.664 +	case 2:__put_user_asm(*(u16*)src,(u16*)dst,ret,"w","w","ir",2);
  45.665 +		return ret;
  45.666 +	case 4:__put_user_asm(*(u32*)src,(u32*)dst,ret,"l","k","ir",4);
  45.667 +		return ret;
  45.668 +	case 8:__put_user_asm(*(u64*)src,(u64*)dst,ret,"q","","ir",8);
  45.669 +		return ret; 
  45.670 +	case 10:
  45.671 +		__put_user_asm(*(u64*)src,(u64*)dst,ret,"q","","ir",10);
  45.672 +		if (ret) return ret;
  45.673 +		asm("":::"memory");
  45.674 +		__put_user_asm(4[(u16*)src],4+(u16*)dst,ret,"w","w","ir",2);
  45.675 +		return ret; 
  45.676 +	case 16:
  45.677 +		__put_user_asm(*(u64*)src,(u64*)dst,ret,"q","","ir",16);
  45.678 +		if (ret) return ret;
  45.679 +		asm("":::"memory");
  45.680 +		__put_user_asm(1[(u64*)src],1+(u64*)dst,ret,"q","","ir",8);
  45.681 +		return ret; 
  45.682 +	default:
  45.683 +		return copy_user_generic(dst,src,size); 
  45.684 +	}
  45.685 +}	
  45.686  
  45.687  long strncpy_from_user(char *dst, const char *src, long count);
  45.688  long __strncpy_from_user(char *dst, const char *src, long count);
  45.689 -#define strlen_user(str) strnlen_user(str, ~0UL >> 1)
  45.690  long strnlen_user(const char *str, long n);
  45.691 +long strlen_user(const char *str);
  45.692  unsigned long clear_user(void *mem, unsigned long len);
  45.693  unsigned long __clear_user(void *mem, unsigned long len);
  45.694  
  45.695 -#endif /* __i386_UACCESS_H */
  45.696 +extern unsigned long search_exception_table(unsigned long);
  45.697 +
  45.698 +#endif /* __X86_64_UACCESS_H */
    46.1 --- a/xen/include/asm-x86_64/unaligned.h	Wed Mar 10 13:44:42 2004 +0000
    46.2 +++ b/xen/include/asm-x86_64/unaligned.h	Wed Mar 10 13:46:20 2004 +0000
    46.3 @@ -1,8 +1,8 @@
    46.4 -#ifndef __I386_UNALIGNED_H
    46.5 -#define __I386_UNALIGNED_H
    46.6 +#ifndef __X8664_UNALIGNED_H
    46.7 +#define __X8664_UNALIGNED_H
    46.8  
    46.9  /*
   46.10 - * The i386 can do unaligned accesses itself. 
   46.11 + * The x86-64 can do unaligned accesses itself. 
   46.12   *
   46.13   * The strange macros are there to make sure these can't
   46.14   * be misused in a way that makes them not work on other
    47.1 --- a/xen/include/hypervisor-ifs/dom0_ops.h	Wed Mar 10 13:44:42 2004 +0000
    47.2 +++ b/xen/include/hypervisor-ifs/dom0_ops.h	Wed Mar 10 13:46:20 2004 +0000
    47.3 @@ -19,29 +19,6 @@
    47.4   */
    47.5  #define DOM0_INTERFACE_VERSION   0xAAAA0008
    47.6  
    47.7 -/*
    47.8 - * The following is all CPU context. Note that the i387_ctxt block is filled 
    47.9 - * in by FXSAVE if the CPU has feature FXSR; otherwise FSAVE is used.
   47.10 - */
   47.11 -typedef struct full_execution_context_st
   47.12 -{
   47.13 -#define ECF_I387_VALID (1<<0)
   47.14 -    unsigned long flags;
   47.15 -    execution_context_t i386_ctxt;          /* User-level CPU registers     */
   47.16 -    char          i387_ctxt[256];           /* User-level FPU registers     */
   47.17 -    trap_info_t   trap_ctxt[256];           /* Virtual IDT                  */
   47.18 -    unsigned int  fast_trap_idx;            /* "Fast trap" vector offset    */
   47.19 -    unsigned long ldt_base, ldt_ents;       /* LDT (linear address, # ents) */
   47.20 -    unsigned long gdt_frames[16], gdt_ents; /* GDT (machine frames, # ents) */
   47.21 -    unsigned long ring1_ss, ring1_esp;      /* Virtual TSS (only SS1/ESP1)  */
   47.22 -    unsigned long pt_base;                  /* CR3 (pagetable base)         */
   47.23 -    unsigned long debugreg[8];              /* DB0-DB7 (debug registers)    */
   47.24 -    unsigned long event_callback_cs;        /* CS:EIP of event callback     */
   47.25 -    unsigned long event_callback_eip;
   47.26 -    unsigned long failsafe_callback_cs;     /* CS:EIP of failsafe callback  */
   47.27 -    unsigned long failsafe_callback_eip;
   47.28 -} full_execution_context_t;
   47.29 -
   47.30  #define MAX_CMD_LEN       256
   47.31  #define MAX_DOMAIN_NAME    16
   47.32  
    48.1 --- a/xen/include/hypervisor-ifs/hypervisor-if.h	Wed Mar 10 13:44:42 2004 +0000
    48.2 +++ b/xen/include/hypervisor-ifs/hypervisor-if.h	Wed Mar 10 13:46:20 2004 +0000
    48.3 @@ -7,33 +7,7 @@
    48.4  #ifndef __HYPERVISOR_IF_H__
    48.5  #define __HYPERVISOR_IF_H__
    48.6  
    48.7 -/*
    48.8 - * SEGMENT DESCRIPTOR TABLES
    48.9 - */
   48.10 -/*
   48.11 - * A number of GDT entries are reserved by Xen. These are not situated at the
   48.12 - * start of the GDT because some stupid OSes export hard-coded selector values
   48.13 - * in their ABI. These hard-coded values are always near the start of the GDT,
   48.14 - * so Xen places itself out of the way.
   48.15 - * 
   48.16 - * NB. The reserved range is inclusive (that is, both FIRST_RESERVED_GDT_ENTRY
   48.17 - * and LAST_RESERVED_GDT_ENTRY are reserved).
   48.18 - */
   48.19 -#define NR_RESERVED_GDT_ENTRIES    40
   48.20 -#define FIRST_RESERVED_GDT_ENTRY   256
   48.21 -#define LAST_RESERVED_GDT_ENTRY    \
   48.22 -  (FIRST_RESERVED_GDT_ENTRY + NR_RESERVED_GDT_ENTRIES - 1)
   48.23 -
   48.24 -/*
   48.25 - * These flat segments are in the Xen-private section of every GDT. Since these
   48.26 - * are also present in the initial GDT, many OSes will be able to avoid
   48.27 - * installing their own GDT.
   48.28 - */
   48.29 -#define FLAT_RING1_CS 0x0819    /* GDT index 259 */
   48.30 -#define FLAT_RING1_DS 0x0821    /* GDT index 260 */
   48.31 -#define FLAT_RING3_CS 0x082b    /* GDT index 261 */
   48.32 -#define FLAT_RING3_DS 0x0833    /* GDT index 262 */
   48.33 -
   48.34 +#include "if-arch/hypervisor-if-arch.h"
   48.35  
   48.36  /*
   48.37   * HYPERVISOR "SYSTEM CALLS"
   48.38 @@ -65,10 +39,6 @@
   48.39  #define __HYPERVISOR_xen_version          22
   48.40  #define __HYPERVISOR_serial_io            23
   48.41  
   48.42 -/* And the trap vector is... */
   48.43 -#define TRAP_INSTR "int $0x82"
   48.44 -
   48.45 -
   48.46  /*
   48.47   * MULTICALLS
   48.48   * 
   48.49 @@ -76,7 +46,7 @@
   48.50   * (BYTES_PER_MULTICALL_ENTRY). Each is of the form (op, arg1, ..., argN)
   48.51   * where each element of the tuple is a machine word. 
   48.52   */
   48.53 -#define BYTES_PER_MULTICALL_ENTRY 32
   48.54 +#define ARGS_PER_MULTICALL_ENTRY 8
   48.55  
   48.56  
   48.57  /* EVENT MESSAGES
   48.58 @@ -110,15 +80,6 @@
   48.59  #define _EVENT_VBD_UPD  8
   48.60  #define _EVENT_CONSOLE  9 /* This is only for domain-0 initial console. */
   48.61  
   48.62 -/*
   48.63 - * Virtual addresses beyond this are not modifiable by guest OSes. The 
   48.64 - * machine->physical mapping table starts at this address, read-only.
   48.65 - */
   48.66 -#define HYPERVISOR_VIRT_START (0xFC000000UL)
   48.67 -#ifndef machine_to_phys_mapping
   48.68 -#define machine_to_phys_mapping ((unsigned long *)HYPERVISOR_VIRT_START)
   48.69 -#endif
   48.70 -
   48.71  
   48.72  /*
   48.73   * MMU_XXX: specified in least 2 bits of 'ptr' field. These bits are masked
   48.74 @@ -187,21 +148,6 @@ typedef u64 domid_t;
   48.75  #include "block.h"
   48.76  
   48.77  /*
   48.78 - * Send an array of these to HYPERVISOR_set_trap_table()
   48.79 - */
   48.80 -#define TI_GET_DPL(_ti)      ((_ti)->flags & 3)
   48.81 -#define TI_GET_IF(_ti)       ((_ti)->flags & 4)
   48.82 -#define TI_SET_DPL(_ti,_dpl) ((_ti)->flags |= (_dpl))
   48.83 -#define TI_SET_IF(_ti,_if)   ((_ti)->flags |= ((!!(_if))<<2))
   48.84 -typedef struct trap_info_st
   48.85 -{
   48.86 -    unsigned char  vector;  /* exception vector                              */
   48.87 -    unsigned char  flags;   /* 0-3: privilege level; 4: clear event enable?  */
   48.88 -    unsigned short cs;	    /* code selector                                 */
   48.89 -    unsigned long  address; /* code address                                  */
   48.90 -} trap_info_t;
   48.91 -
   48.92 -/*
   48.93   * Send an array of these to HYPERVISOR_mmu_update()
   48.94   */
   48.95  typedef struct
   48.96 @@ -218,27 +164,6 @@ typedef struct
   48.97      unsigned long args[7];
   48.98  } multicall_entry_t;
   48.99  
  48.100 -typedef struct
  48.101 -{
  48.102 -    unsigned long ebx;
  48.103 -    unsigned long ecx;
  48.104 -    unsigned long edx;
  48.105 -    unsigned long esi;
  48.106 -    unsigned long edi;
  48.107 -    unsigned long ebp;
  48.108 -    unsigned long eax;
  48.109 -    unsigned long ds;
  48.110 -    unsigned long es;
  48.111 -    unsigned long fs;
  48.112 -    unsigned long gs;
  48.113 -    unsigned long _unused;
  48.114 -    unsigned long eip;
  48.115 -    unsigned long cs;
  48.116 -    unsigned long eflags;
  48.117 -    unsigned long esp;
  48.118 -    unsigned long ss;
  48.119 -} execution_context_t;
  48.120 -
  48.121  /*
  48.122   * Xen/guestos shared data -- pointer provided in start_info.
  48.123   * NB. We expect that this struct is smaller than a page.
  48.124 @@ -285,7 +210,6 @@ typedef struct shared_info_st {
  48.125       * Domain Virtual Time. Domains can access Cycle counter time directly.
  48.126       */
  48.127  
  48.128 -    unsigned int       rdtsc_bitshift;  /* tsc_timestamp uses N:N+31 of TSC. */
  48.129      u64                cpu_freq;        /* CPU frequency (Hz).               */
  48.130  
  48.131      /*
  48.132 @@ -310,6 +234,7 @@ typedef struct shared_info_st {
  48.133       * Allow a domain to specify a timeout value in system time and 
  48.134       * domain virtual time.
  48.135       */
  48.136 +
  48.137      u64                wall_timeout;
  48.138      u64                domain_timeout;
  48.139  
  48.140 @@ -322,6 +247,7 @@ typedef struct shared_info_st {
  48.141      net_idx_t net_idx[MAX_DOMAIN_VIFS];
  48.142  
  48.143      execution_context_t execution_context;
  48.144 +    arch_shared_info_t arch;
  48.145  
  48.146  } shared_info_t;
  48.147  
    49.1 --- a/xen/include/hypervisor-ifs/if-i386/hypervisor-if-arch.h	Wed Mar 10 13:44:42 2004 +0000
    49.2 +++ b/xen/include/hypervisor-ifs/if-i386/hypervisor-if-arch.h	Wed Mar 10 13:46:20 2004 +0000
    49.3 @@ -1,11 +1,11 @@
    49.4  /******************************************************************************
    49.5 - * hypervisor-if.h
    49.6 + * hypervisor-if-i386.h
    49.7   * 
    49.8 - * Interface to Xeno hypervisor.
    49.9 + * i386 32-bit Interface to Xeno hypervisor.
   49.10   */
   49.11  
   49.12 -#ifndef __HYPERVISOR_IF_H__
   49.13 -#define __HYPERVISOR_IF_H__
   49.14 +#ifndef __HYPERVISOR_IF_I386_H__
   49.15 +#define __HYPERVISOR_IF_I386_H__
   49.16  
   49.17  /*
   49.18   * SEGMENT DESCRIPTOR TABLES
   49.19 @@ -24,6 +24,7 @@
   49.20  #define LAST_RESERVED_GDT_ENTRY    \
   49.21    (FIRST_RESERVED_GDT_ENTRY + NR_RESERVED_GDT_ENTRIES - 1)
   49.22  
   49.23 +
   49.24  /*
   49.25   * These flat segments are in the Xen-private section of every GDT. Since these
   49.26   * are also present in the initial GDT, many OSes will be able to avoid
   49.27 @@ -34,83 +35,11 @@
   49.28  #define FLAT_RING3_CS 0x082b    /* GDT index 261 */
   49.29  #define FLAT_RING3_DS 0x0833    /* GDT index 262 */
   49.30  
   49.31 -
   49.32 -/*
   49.33 - * HYPERVISOR "SYSTEM CALLS"
   49.34 - */
   49.35 -
   49.36 -/* EAX = vector; EBX, ECX, EDX, ESI, EDI = args 1, 2, 3, 4, 5. */
   49.37 -#define __HYPERVISOR_set_trap_table        0
   49.38 -#define __HYPERVISOR_mmu_update            1
   49.39 -#define __HYPERVISOR_console_write         2 /* DEPRECATED */
   49.40 -#define __HYPERVISOR_set_gdt               3
   49.41 -#define __HYPERVISOR_stack_switch          4
   49.42 -#define __HYPERVISOR_set_callbacks         5
   49.43 -#define __HYPERVISOR_net_io_op             6
   49.44 -#define __HYPERVISOR_fpu_taskswitch        7
   49.45 -#define __HYPERVISOR_sched_op              8
   49.46 -#define __HYPERVISOR_dom0_op               9
   49.47 -#define __HYPERVISOR_network_op           10
   49.48 -#define __HYPERVISOR_block_io_op          11
   49.49 -#define __HYPERVISOR_set_debugreg         12
   49.50 -#define __HYPERVISOR_get_debugreg         13
   49.51 -#define __HYPERVISOR_update_descriptor    14
   49.52 -#define __HYPERVISOR_set_fast_trap        15
   49.53 -#define __HYPERVISOR_dom_mem_op           16
   49.54 -#define __HYPERVISOR_multicall            17
   49.55 -#define __HYPERVISOR_kbd_op               18
   49.56 -#define __HYPERVISOR_update_va_mapping    19
   49.57 -#define __HYPERVISOR_set_timer_op         20
   49.58 -#define __HYPERVISOR_event_channel_op     21
   49.59 -#define __HYPERVISOR_xen_version          22
   49.60 -#define __HYPERVISOR_serial_io            23
   49.61 -
   49.62  /* And the trap vector is... */
   49.63  #define TRAP_INSTR "int $0x82"
   49.64  
   49.65  
   49.66  /*
   49.67 - * MULTICALLS
   49.68 - * 
   49.69 - * Multicalls are listed in an array, with each element being a fixed size 
   49.70 - * (BYTES_PER_MULTICALL_ENTRY). Each is of the form (op, arg1, ..., argN)
   49.71 - * where each element of the tuple is a machine word. 
   49.72 - */
   49.73 -#define BYTES_PER_MULTICALL_ENTRY 32
   49.74 -
   49.75 -
   49.76 -/* EVENT MESSAGES
   49.77 - *
   49.78 - * Here, as in the interrupts to the guestos, additional network interfaces
   49.79 - * are defined.	 These definitions server as placeholders for the event bits,
   49.80 - * however, in the code these events will allways be referred to as shifted
   49.81 - * offsets from the base NET events.
   49.82 - */
   49.83 -
   49.84 -/* Events that a guest OS may receive from the hypervisor. */
   49.85 -#define EVENT_BLKDEV   0x01 /* A block device response has been queued. */
   49.86 -#define EVENT_TIMER    0x02 /* A timeout has been updated. */
   49.87 -#define EVENT_DIE      0x04 /* OS is about to be killed. Clean up please! */
   49.88 -#define EVENT_DEBUG    0x08 /* Request guest to dump debug info (gross!) */
   49.89 -#define EVENT_NET      0x10 /* There are packets for transmission. */
   49.90 -#define EVENT_PS2      0x20 /* PS/2 keyboard or mouse event(s) */
   49.91 -#define EVENT_STOP     0x40 /* Prepare for stopping and possible pickling */
   49.92 -#define EVENT_EVTCHN   0x80 /* Event pending on an event channel */
   49.93 -#define EVENT_VBD_UPD  0x100 /* Event to signal VBDs should be reprobed */
   49.94 -
   49.95 -/* Bit offsets, as opposed to the above masks. */
   49.96 -#define _EVENT_BLKDEV   0
   49.97 -#define _EVENT_TIMER    1
   49.98 -#define _EVENT_DIE      2
   49.99 -#define _EVENT_DEBUG    3
  49.100 -#define _EVENT_NET      4
  49.101 -#define _EVENT_PS2      5
  49.102 -#define _EVENT_STOP     6
  49.103 -#define _EVENT_EVTCHN   7
  49.104 -#define _EVENT_VBD_UPD  8
  49.105 -#define _EVENT_CONSOLE  9 /* This is only for domain-0 initial console. */
  49.106 -
  49.107 -/*
  49.108   * Virtual addresses beyond this are not modifiable by guest OSes. The 
  49.109   * machine->physical mapping table starts at this address, read-only.
  49.110   */
  49.111 @@ -119,73 +48,8 @@
  49.112  #define machine_to_phys_mapping ((unsigned long *)HYPERVISOR_VIRT_START)
  49.113  #endif
  49.114  
  49.115 -
  49.116 -/*
  49.117 - * MMU_XXX: specified in least 2 bits of 'ptr' field. These bits are masked
  49.118 - *  off to get the real 'ptr' value.
  49.119 - * All requests specify relevent address in 'ptr'. This is either a
  49.120 - * machine/physical address (MA), or linear/virtual address (VA).
  49.121 - * Normal requests specify update value in 'value'.
  49.122 - * Extended requests specify command in least 8 bits of 'value'. These bits
  49.123 - *  are masked off to get the real 'val' value. Except for MMUEXT_SET_LDT 
  49.124 - *  which shifts the least bits out.
  49.125 - */
  49.126 -/* A normal page-table update request. */
  49.127 -#define MMU_NORMAL_PT_UPDATE     0 /* checked '*ptr = val'. ptr is MA.       */
  49.128 -/* Update an entry in the machine->physical mapping table. */
  49.129 -#define MMU_MACHPHYS_UPDATE      2 /* ptr = MA of frame to modify entry for  */
  49.130 -/* An extended command. */
  49.131 -#define MMU_EXTENDED_COMMAND     3 /* least 8 bits of val demux further      */
  49.132 -/* Extended commands: */
  49.133 -#define MMUEXT_PIN_L1_TABLE      0 /* ptr = MA of frame to pin               */
  49.134 -#define MMUEXT_PIN_L2_TABLE      1 /* ptr = MA of frame to pin               */
  49.135 -#define MMUEXT_PIN_L3_TABLE      2 /* ptr = MA of frame to pin               */
  49.136 -#define MMUEXT_PIN_L4_TABLE      3 /* ptr = MA of frame to pin               */
  49.137 -#define MMUEXT_UNPIN_TABLE       4 /* ptr = MA of frame to unpin             */
  49.138 -#define MMUEXT_NEW_BASEPTR       5 /* ptr = MA of new pagetable base         */
  49.139 -#define MMUEXT_TLB_FLUSH         6 /* ptr = NULL                             */
  49.140 -#define MMUEXT_INVLPG            7 /* ptr = NULL ; val = VA to invalidate    */
  49.141 -#define MMUEXT_SET_LDT           8 /* ptr = VA of table; val = # entries     */
  49.142 -/* NB. MMUEXT_SET_SUBJECTDOM must consist of *_L followed immediately by *_H */
  49.143 -#define MMUEXT_SET_SUBJECTDOM_L  9 /* (ptr[31:15],val[31:15]) = dom[31:0]    */
  49.144 -#define MMUEXT_SET_SUBJECTDOM_H 10 /* (ptr[31:15],val[31:15]) = dom[63:32]   */
  49.145 -#define MMUEXT_CMD_MASK        255
  49.146 -#define MMUEXT_CMD_SHIFT         8
  49.147 -
  49.148 -/* These are passed as 'flags' to update_va_mapping. They can be ORed. */
  49.149 -#define UVMF_FLUSH_TLB          1 /* Flush entire TLB. */
  49.150 -#define UVMF_INVLPG             2 /* Flush the VA mapping being updated. */
  49.151 -
  49.152 -/*
  49.153 - * Master "switch" for enabling/disabling event delivery.
  49.154 - */
  49.155 -#define EVENTS_MASTER_ENABLE_MASK 0x80000000UL
  49.156 -#define EVENTS_MASTER_ENABLE_BIT  31
  49.157 -
  49.158 -
  49.159 -/*
  49.160 - * SCHEDOP_* - Scheduler hypercall operations.
  49.161 - */
  49.162 -#define SCHEDOP_yield           0   /* Give up the CPU voluntarily.      */
  49.163 -#define SCHEDOP_block           1   /* Block until an event is received. */
  49.164 -#define SCHEDOP_exit            3   /* Exit and kill this domain.        */
  49.165 -#define SCHEDOP_stop            4   /* Stop executing this domain.       */
  49.166 -
  49.167 -/*
  49.168 - * Commands to HYPERVISOR_serial_io().
  49.169 - */
  49.170 -#define SERIALIO_write          0
  49.171 -#define SERIALIO_read           1
  49.172 -
  49.173  #ifndef __ASSEMBLY__
  49.174  
  49.175 -typedef u64 domid_t;
  49.176 -/* DOMID_SELF is used in certain contexts to refer to oneself. */
  49.177 -#define DOMID_SELF (~1ULL)
  49.178 -
  49.179 -#include "network.h"
  49.180 -#include "block.h"
  49.181 -
  49.182  /*
  49.183   * Send an array of these to HYPERVISOR_set_trap_table()
  49.184   */
  49.185 @@ -201,23 +65,6 @@ typedef struct trap_info_st
  49.186      unsigned long  address; /* code address                                  */
  49.187  } trap_info_t;
  49.188  
  49.189 -/*
  49.190 - * Send an array of these to HYPERVISOR_mmu_update()
  49.191 - */
  49.192 -typedef struct
  49.193 -{
  49.194 -    unsigned long ptr, val; /* *ptr = val */
  49.195 -} mmu_update_t;
  49.196 -
  49.197 -/*
  49.198 - * Send an array of these to HYPERVISOR_multicall()
  49.199 - */
  49.200 -typedef struct
  49.201 -{
  49.202 -    unsigned long op;
  49.203 -    unsigned long args[7];
  49.204 -} multicall_entry_t;
  49.205 -
  49.206  typedef struct
  49.207  {
  49.208      unsigned long ebx;
  49.209 @@ -240,113 +87,36 @@ typedef struct
  49.210  } execution_context_t;
  49.211  
  49.212  /*
  49.213 - * Xen/guestos shared data -- pointer provided in start_info.
  49.214 - * NB. We expect that this struct is smaller than a page.
  49.215 + * Shared info specific to the architecture in question
  49.216   */
  49.217 -typedef struct shared_info_st {
  49.218 -
  49.219 -    /* Bitmask of outstanding event notifications hypervisor -> guest OS. */
  49.220 -    unsigned long events;
  49.221 -    /*
  49.222 -     * Hypervisor will only signal event delivery via the "callback exception"
  49.223 -     * when a pending event is not masked. The mask also contains a "master
  49.224 -     * enable" which prevents any event delivery. This mask can be used to
  49.225 -     * prevent unbounded reentrancy and stack overflow (in this way, acts as a
  49.226 -     * kind of interrupt-enable flag).
  49.227 -     */
  49.228 -    unsigned long events_mask;
  49.229 -
  49.230 -    /*
  49.231 -     * A domain can have up to 1024 bidirectional event channels to/from other
  49.232 -     * domains. Domains must agree out-of-band to set up a connection, and then
  49.233 -     * each must explicitly request a connection to the other. When both have
  49.234 -     * made the request the channel is fully allocated and set up.
  49.235 -     * 
  49.236 -     * An event channel is a single sticky 'bit' of information. Setting the
  49.237 -     * sticky bit also causes an upcall into the target domain. In this way
  49.238 -     * events can be seen as an IPI [Inter-Process(or) Interrupt].
  49.239 -     * 
  49.240 -     * A guest can see which of its event channels are pending by reading the
  49.241 -     * 'event_channel_pend' bitfield. To avoid a linear scan of the entire
  49.242 -     * bitfield there is a 'selector' which indicates which words in the
  49.243 -     * bitfield contain at least one set bit.
  49.244 -     * 
  49.245 -     * There is a similar bitfield to indicate which event channels have been
  49.246 -     * disconnected by the remote end. There is also a 'selector' for this
  49.247 -     * field.
  49.248 -     */
  49.249 -    u32 event_channel_pend[32];
  49.250 -    u32 event_channel_pend_sel;
  49.251 -    u32 event_channel_disc[32];
  49.252 -    u32 event_channel_disc_sel;
  49.253 +typedef struct arch_shared_info_st {
  49.254 +    unsigned int       rdtsc_bitshift;  /* tsc_timestamp uses N:N+31 of TSC. */
  49.255 +} arch_shared_info_t;
  49.256  
  49.257 -    /*
  49.258 -     * Time: The following abstractions are exposed: System Time, Clock Time,
  49.259 -     * Domain Virtual Time. Domains can access Cycle counter time directly.
  49.260 -     */
  49.261 -
  49.262 -    unsigned int       rdtsc_bitshift;  /* tsc_timestamp uses N:N+31 of TSC. */
  49.263 -    u64                cpu_freq;        /* CPU frequency (Hz).               */
  49.264 -
  49.265 -    /*
  49.266 -     * The following values are updated periodically (and not necessarily
  49.267 -     * atomically!). The guest OS detects this because 'time_version1' is
  49.268 -     * incremented just before updating these values, and 'time_version2' is
  49.269 -     * incremented immediately after. See Xenolinux code for an example of how 
  49.270 -     * to read these values safely (arch/xeno/kernel/time.c).
  49.271 -     */
  49.272 -    unsigned long      time_version1;   /* A version number for info below.  */
  49.273 -    unsigned long      time_version2;   /* A version number for info below.  */
  49.274 -    unsigned long      tsc_timestamp;   /* TSC at last update of time vals.  */
  49.275 -    u64                system_time;     /* Time, in nanosecs, since boot.    */
  49.276 -    unsigned long      wc_sec;          /* Secs  00:00:00 UTC, Jan 1, 1970.  */
  49.277 -    unsigned long      wc_usec;         /* Usecs 00:00:00 UTC, Jan 1, 1970.  */
  49.278 -    
  49.279 -    /* Domain Virtual Time */
  49.280 -    u64                domain_time;
  49.281 -	
  49.282 -    /*
  49.283 -     * Timeout values:
  49.284 -     * Allow a domain to specify a timeout value in system time and 
  49.285 -     * domain virtual time.
  49.286 -     */
  49.287 -    u64                wall_timeout;
  49.288 -    u64                domain_timeout;
  49.289 -
  49.290 -    /*
  49.291 -     * The index structures are all stored here for convenience. The rings 
  49.292 -     * themselves are allocated by Xen but the guestos must create its own 
  49.293 -     * mapping -- the machine address is given in the startinfo structure to 
  49.294 -     * allow this to happen.
  49.295 -     */
  49.296 -    net_idx_t net_idx[MAX_DOMAIN_VIFS];
  49.297 -
  49.298 -    execution_context_t execution_context;
  49.299 -
  49.300 -} shared_info_t;
  49.301  
  49.302  /*
  49.303 - * NB. We expect that this struct is smaller than a page.
  49.304 + * The following is all CPU context. Note that the i387_ctxt block is filled 
  49.305 + * in by FXSAVE if the CPU has feature FXSR; otherwise FSAVE is used.
  49.306   */
  49.307 -typedef struct start_info_st {
  49.308 -    /* THE FOLLOWING ARE FILLED IN BOTH ON INITIAL BOOT AND ON RESUME.     */
  49.309 -    unsigned long nr_pages;	  /* total pages allocated to this domain. */
  49.310 -    unsigned long shared_info;	  /* MACHINE address of shared info struct.*/
  49.311 -    unsigned long flags;          /* SIF_xxx flags.                        */
  49.312 -    /* THE FOLLOWING ARE ONLY FILLED IN ON INITIAL BOOT (NOT RESUME).      */
  49.313 -    unsigned long pt_base;	  /* VIRTUAL address of page directory.    */
  49.314 -    unsigned long mod_start;	  /* VIRTUAL address of pre-loaded module. */
  49.315 -    unsigned long mod_len;	  /* Size (bytes) of pre-loaded module.    */
  49.316 -    unsigned char cmd_line[1];	  /* Variable-length options.              */
  49.317 -} start_info_t;
  49.318 +typedef struct full_execution_context_st
  49.319 +{
  49.320 +#define ECF_I387_VALID (1<<0)
  49.321 +    unsigned long flags;
  49.322 +    execution_context_t i386_ctxt;          /* User-level CPU registers     */
  49.323 +    char          i387_ctxt[256];           /* User-level FPU registers     */
  49.324 +    trap_info_t   trap_ctxt[256];           /* Virtual IDT                  */
  49.325 +    unsigned int  fast_trap_idx;            /* "Fast trap" vector offset    */
  49.326 +    unsigned long ldt_base, ldt_ents;       /* LDT (linear address, # ents) */
  49.327 +    unsigned long gdt_frames[16], gdt_ents; /* GDT (machine frames, # ents) */
  49.328 +    unsigned long ring1_ss, ring1_esp;      /* Virtual TSS (only SS1/ESP1)  */
  49.329 +    unsigned long pt_base;                  /* CR3 (pagetable base)         */
  49.330 +    unsigned long debugreg[8];              /* DB0-DB7 (debug registers)    */
  49.331 +    unsigned long event_callback_cs;        /* CS:EIP of event callback     */
  49.332 +    unsigned long event_callback_eip;
  49.333 +    unsigned long failsafe_callback_cs;     /* CS:EIP of failsafe callback  */
  49.334 +    unsigned long failsafe_callback_eip;
  49.335 +} full_execution_context_t;
  49.336  
  49.337 -/* These flags are passed in the 'flags' field of start_info_t. */
  49.338 -#define SIF_PRIVILEGED 1          /* Is the domain privileged? */
  49.339 -#define SIF_INITDOMAIN 2          /* Is thsi the initial control domain? */
  49.340 +#endif
  49.341  
  49.342 -/* For use in guest OSes. */
  49.343 -extern shared_info_t *HYPERVISOR_shared_info;
  49.344 -
  49.345 -#endif /* !__ASSEMBLY__ */
  49.346 -
  49.347 -#endif /* __HYPERVISOR_IF_H__ */
  49.348 +#endif
    50.1 --- a/xen/include/hypervisor-ifs/if-x86_64/hypervisor-if-arch.h	Wed Mar 10 13:44:42 2004 +0000
    50.2 +++ b/xen/include/hypervisor-ifs/if-x86_64/hypervisor-if-arch.h	Wed Mar 10 13:46:20 2004 +0000
    50.3 @@ -1,11 +1,11 @@
    50.4  /******************************************************************************
    50.5   * hypervisor-if.h
    50.6   * 
    50.7 - * Interface to Xeno hypervisor.
    50.8 + * Interface to AMD x86-64 bit Xeno hypervisor.
    50.9   */
   50.10  
   50.11 -#ifndef __HYPERVISOR_IF_H__
   50.12 -#define __HYPERVISOR_IF_H__
   50.13 +#ifndef __HYPERVISOR_IF_X86_64_H__
   50.14 +#define __HYPERVISOR_IF_X86_64_H__
   50.15  
   50.16  /*
   50.17   * SEGMENT DESCRIPTOR TABLES
   50.18 @@ -19,173 +19,33 @@
   50.19   * NB. The reserved range is inclusive (that is, both FIRST_RESERVED_GDT_ENTRY
   50.20   * and LAST_RESERVED_GDT_ENTRY are reserved).
   50.21   */
   50.22 -#define NR_RESERVED_GDT_ENTRIES    40
   50.23 +#define NR_RESERVED_GDT_ENTRIES    40 
   50.24  #define FIRST_RESERVED_GDT_ENTRY   256
   50.25  #define LAST_RESERVED_GDT_ENTRY    \
   50.26    (FIRST_RESERVED_GDT_ENTRY + NR_RESERVED_GDT_ENTRIES - 1)
   50.27  
   50.28  /*
   50.29 + * 64-bit segment selectors
   50.30   * These flat segments are in the Xen-private section of every GDT. Since these
   50.31   * are also present in the initial GDT, many OSes will be able to avoid
   50.32   * installing their own GDT.
   50.33   */
   50.34 -#define FLAT_RING1_CS 0x0819    /* GDT index 259 */
   50.35 -#define FLAT_RING1_DS 0x0821    /* GDT index 260 */
   50.36 -#define FLAT_RING3_CS 0x082b    /* GDT index 261 */
   50.37 -#define FLAT_RING3_DS 0x0833    /* GDT index 262 */
   50.38  
   50.39 -
   50.40 -/*
   50.41 - * HYPERVISOR "SYSTEM CALLS"
   50.42 - */
   50.43 -
   50.44 -/* EAX = vector; EBX, ECX, EDX, ESI, EDI = args 1, 2, 3, 4, 5. */
   50.45 -#define __HYPERVISOR_set_trap_table        0
   50.46 -#define __HYPERVISOR_mmu_update            1
   50.47 -#define __HYPERVISOR_console_write         2 /* DEPRECATED */
   50.48 -#define __HYPERVISOR_set_gdt               3
   50.49 -#define __HYPERVISOR_stack_switch          4
   50.50 -#define __HYPERVISOR_set_callbacks         5
   50.51 -#define __HYPERVISOR_net_io_op             6
   50.52 -#define __HYPERVISOR_fpu_taskswitch        7
   50.53 -#define __HYPERVISOR_sched_op              8
   50.54 -#define __HYPERVISOR_dom0_op               9
   50.55 -#define __HYPERVISOR_network_op           10
   50.56 -#define __HYPERVISOR_block_io_op          11
   50.57 -#define __HYPERVISOR_set_debugreg         12
   50.58 -#define __HYPERVISOR_get_debugreg         13
   50.59 -#define __HYPERVISOR_update_descriptor    14
   50.60 -#define __HYPERVISOR_set_fast_trap        15
   50.61 -#define __HYPERVISOR_dom_mem_op           16
   50.62 -#define __HYPERVISOR_multicall            17
   50.63 -#define __HYPERVISOR_kbd_op               18
   50.64 -#define __HYPERVISOR_update_va_mapping    19
   50.65 -#define __HYPERVISOR_set_timer_op         20
   50.66 -#define __HYPERVISOR_event_channel_op     21
   50.67 -#define __HYPERVISOR_xen_version          22
   50.68 -#define __HYPERVISOR_serial_io            23
   50.69 -
   50.70 -/* And the trap vector is... */
   50.71 -#define TRAP_INSTR "int $0x82"
   50.72 +#define FLAT_RING3_CS32 0x0823	/* GDT index 260 */
   50.73 +#define FLAT_RING3_CS64 0x082b	/* GDT index 261 */
   50.74 +#define FLAT_RING3_DS 0x0833	/* GDT index 262 */
   50.75  
   50.76  
   50.77 -/*
   50.78 - * MULTICALLS
   50.79 - * 
   50.80 - * Multicalls are listed in an array, with each element being a fixed size 
   50.81 - * (BYTES_PER_MULTICALL_ENTRY). Each is of the form (op, arg1, ..., argN)
   50.82 - * where each element of the tuple is a machine word. 
   50.83 - */
   50.84 -#define BYTES_PER_MULTICALL_ENTRY 32
   50.85 +/* And the trap vector is... */
   50.86 +#define TRAP_INSTR "syscall"
   50.87  
   50.88  
   50.89 -/* EVENT MESSAGES
   50.90 - *
   50.91 - * Here, as in the interrupts to the guestos, additional network interfaces
   50.92 - * are defined.	 These definitions server as placeholders for the event bits,
   50.93 - * however, in the code these events will allways be referred to as shifted
   50.94 - * offsets from the base NET events.
   50.95 - */
   50.96 -
   50.97 -/* Events that a guest OS may receive from the hypervisor. */
   50.98 -#define EVENT_BLKDEV   0x01 /* A block device response has been queued. */
   50.99 -#define EVENT_TIMER    0x02 /* A timeout has been updated. */
  50.100 -#define EVENT_DIE      0x04 /* OS is about to be killed. Clean up please! */
  50.101 -#define EVENT_DEBUG    0x08 /* Request guest to dump debug info (gross!) */
  50.102 -#define EVENT_NET      0x10 /* There are packets for transmission. */
  50.103 -#define EVENT_PS2      0x20 /* PS/2 keyboard or mouse event(s) */
  50.104 -#define EVENT_STOP     0x40 /* Prepare for stopping and possible pickling */
  50.105 -#define EVENT_EVTCHN   0x80 /* Event pending on an event channel */
  50.106 -#define EVENT_VBD_UPD  0x100 /* Event to signal VBDs should be reprobed */
  50.107 -
  50.108 -/* Bit offsets, as opposed to the above masks. */
  50.109 -#define _EVENT_BLKDEV   0
  50.110 -#define _EVENT_TIMER    1
  50.111 -#define _EVENT_DIE      2
  50.112 -#define _EVENT_DEBUG    3
  50.113 -#define _EVENT_NET      4
  50.114 -#define _EVENT_PS2      5
  50.115 -#define _EVENT_STOP     6
  50.116 -#define _EVENT_EVTCHN   7
  50.117 -#define _EVENT_VBD_UPD  8
  50.118 -#define _EVENT_CONSOLE  9 /* This is only for domain-0 initial console. */
  50.119 -
  50.120 -/*
  50.121 - * Virtual addresses beyond this are not modifiable by guest OSes. The 
  50.122 - * machine->physical mapping table starts at this address, read-only.
  50.123 - */
  50.124 -#define HYPERVISOR_VIRT_START (0xFC000000UL)
  50.125  #ifndef machine_to_phys_mapping
  50.126  #define machine_to_phys_mapping ((unsigned long *)HYPERVISOR_VIRT_START)
  50.127  #endif
  50.128  
  50.129 -
  50.130 -/*
  50.131 - * MMU_XXX: specified in least 2 bits of 'ptr' field. These bits are masked
  50.132 - *  off to get the real 'ptr' value.
  50.133 - * All requests specify relevent address in 'ptr'. This is either a
  50.134 - * machine/physical address (MA), or linear/virtual address (VA).
  50.135 - * Normal requests specify update value in 'value'.
  50.136 - * Extended requests specify command in least 8 bits of 'value'. These bits
  50.137 - *  are masked off to get the real 'val' value. Except for MMUEXT_SET_LDT 
  50.138 - *  which shifts the least bits out.
  50.139 - */
  50.140 -/* A normal page-table update request. */
  50.141 -#define MMU_NORMAL_PT_UPDATE     0 /* checked '*ptr = val'. ptr is MA.       */
  50.142 -/* Update an entry in the machine->physical mapping table. */
  50.143 -#define MMU_MACHPHYS_UPDATE      2 /* ptr = MA of frame to modify entry for  */
  50.144 -/* An extended command. */
  50.145 -#define MMU_EXTENDED_COMMAND     3 /* least 8 bits of val demux further      */
  50.146 -/* Extended commands: */
  50.147 -#define MMUEXT_PIN_L1_TABLE      0 /* ptr = MA of frame to pin               */
  50.148 -#define MMUEXT_PIN_L2_TABLE      1 /* ptr = MA of frame to pin               */
  50.149 -#define MMUEXT_PIN_L3_TABLE      2 /* ptr = MA of frame to pin               */
  50.150 -#define MMUEXT_PIN_L4_TABLE      3 /* ptr = MA of frame to pin               */
  50.151 -#define MMUEXT_UNPIN_TABLE       4 /* ptr = MA of frame to unpin             */
  50.152 -#define MMUEXT_NEW_BASEPTR       5 /* ptr = MA of new pagetable base         */
  50.153 -#define MMUEXT_TLB_FLUSH         6 /* ptr = NULL                             */
  50.154 -#define MMUEXT_INVLPG            7 /* ptr = NULL ; val = VA to invalidate    */
  50.155 -#define MMUEXT_SET_LDT           8 /* ptr = VA of table; val = # entries     */
  50.156 -/* NB. MMUEXT_SET_SUBJECTDOM must consist of *_L followed immediately by *_H */
  50.157 -#define MMUEXT_SET_SUBJECTDOM_L  9 /* (ptr[31:15],val[31:15]) = dom[31:0]    */
  50.158 -#define MMUEXT_SET_SUBJECTDOM_H 10 /* (ptr[31:15],val[31:15]) = dom[63:32]   */
  50.159 -#define MMUEXT_CMD_MASK        255
  50.160 -#define MMUEXT_CMD_SHIFT         8
  50.161 -
  50.162 -/* These are passed as 'flags' to update_va_mapping. They can be ORed. */
  50.163 -#define UVMF_FLUSH_TLB          1 /* Flush entire TLB. */
  50.164 -#define UVMF_INVLPG             2 /* Flush the VA mapping being updated. */
  50.165 -
  50.166 -/*
  50.167 - * Master "switch" for enabling/disabling event delivery.
  50.168 - */
  50.169 -#define EVENTS_MASTER_ENABLE_MASK 0x80000000UL
  50.170 -#define EVENTS_MASTER_ENABLE_BIT  31
  50.171 -
  50.172 -
  50.173 -/*
  50.174 - * SCHEDOP_* - Scheduler hypercall operations.
  50.175 - */
  50.176 -#define SCHEDOP_yield           0   /* Give up the CPU voluntarily.      */
  50.177 -#define SCHEDOP_block           1   /* Block until an event is received. */
  50.178 -#define SCHEDOP_exit            3   /* Exit and kill this domain.        */
  50.179 -#define SCHEDOP_stop            4   /* Stop executing this domain.       */
  50.180 -
  50.181 -/*
  50.182 - * Commands to HYPERVISOR_serial_io().
  50.183 - */
  50.184 -#define SERIALIO_write          0
  50.185 -#define SERIALIO_read           1
  50.186 -
  50.187  #ifndef __ASSEMBLY__
  50.188  
  50.189 -typedef u64 domid_t;
  50.190 -/* DOMID_SELF is used in certain contexts to refer to oneself. */
  50.191 -#define DOMID_SELF (~1ULL)
  50.192 -
  50.193 -#include "network.h"
  50.194 -#include "block.h"
  50.195 -
  50.196  /*
  50.197   * Send an array of these to HYPERVISOR_set_trap_table()
  50.198   */
  50.199 @@ -201,41 +61,27 @@ typedef struct trap_info_st
  50.200      unsigned long  address; /* code address                                  */
  50.201  } trap_info_t;
  50.202  
  50.203 -/*
  50.204 - * Send an array of these to HYPERVISOR_mmu_update()
  50.205 - */
  50.206 -typedef struct
  50.207 -{
  50.208 -    unsigned long ptr, val; /* *ptr = val */
  50.209 -} mmu_update_t;
  50.210 -
  50.211 -/*
  50.212 - * Send an array of these to HYPERVISOR_multicall()
  50.213 - */
  50.214  typedef struct
  50.215  {
  50.216 -    unsigned long op;
  50.217 -    unsigned long args[7];
  50.218 -} multicall_entry_t;
  50.219 -
  50.220 -typedef struct
  50.221 -{
  50.222 -    unsigned long ebx;
  50.223 -    unsigned long ecx;
  50.224 -    unsigned long edx;
  50.225 -    unsigned long esi;
  50.226 -    unsigned long edi;
  50.227 -    unsigned long ebp;
  50.228 -    unsigned long eax;
  50.229 -    unsigned long ds;
  50.230 -    unsigned long es;
  50.231 -    unsigned long fs;
  50.232 -    unsigned long gs;
  50.233 -    unsigned long _unused;
  50.234 -    unsigned long eip;
  50.235 +    unsigned long r15;
  50.236 +    unsigned long r14;
  50.237 +    unsigned long r13;
  50.238 +    unsigned long r12;
  50.239 +    unsigned long rbp;
  50.240 +    unsigned long rbx;
  50.241 +    unsigned long r11;
  50.242 +    unsigned long r10;
  50.243 +    unsigned long r9;
  50.244 +    unsigned long r8;
  50.245 +    unsigned long rax;
  50.246 +    unsigned long rcx;
  50.247 +    unsigned long rdx;
  50.248 +    unsigned long rsi;
  50.249 +    unsigned long rdi;
  50.250 +    unsigned long rip;
  50.251      unsigned long cs;
  50.252      unsigned long eflags;
  50.253 -    unsigned long esp;
  50.254 +    unsigned long rsp;
  50.255      unsigned long ss;
  50.256  } execution_context_t;
  50.257  
  50.258 @@ -243,109 +89,33 @@ typedef struct
  50.259   * Xen/guestos shared data -- pointer provided in start_info.
  50.260   * NB. We expect that this struct is smaller than a page.
  50.261   */
  50.262 -typedef struct shared_info_st {
  50.263 -
  50.264 -    /* Bitmask of outstanding event notifications hypervisor -> guest OS. */
  50.265 -    unsigned long events;
  50.266 -    /*
  50.267 -     * Hypervisor will only signal event delivery via the "callback exception"
  50.268 -     * when a pending event is not masked. The mask also contains a "master
  50.269 -     * enable" which prevents any event delivery. This mask can be used to
  50.270 -     * prevent unbounded reentrancy and stack overflow (in this way, acts as a
  50.271 -     * kind of interrupt-enable flag).
  50.272 -     */
  50.273 -    unsigned long events_mask;
  50.274 -
  50.275 -    /*
  50.276 -     * A domain can have up to 1024 bidirectional event channels to/from other
  50.277 -     * domains. Domains must agree out-of-band to set up a connection, and then
  50.278 -     * each must explicitly request a connection to the other. When both have
  50.279 -     * made the request the channel is fully allocated and set up.
  50.280 -     * 
  50.281 -     * An event channel is a single sticky 'bit' of information. Setting the
  50.282 -     * sticky bit also causes an upcall into the target domain. In this way
  50.283 -     * events can be seen as an IPI [Inter-Process(or) Interrupt].
  50.284 -     * 
  50.285 -     * A guest can see which of its event channels are pending by reading the
  50.286 -     * 'event_channel_pend' bitfield. To avoid a linear scan of the entire
  50.287 -     * bitfield there is a 'selector' which indicates which words in the
  50.288 -     * bitfield contain at least one set bit.
  50.289 -     * 
  50.290 -     * There is a similar bitfield to indicate which event channels have been
  50.291 -     * disconnected by the remote end. There is also a 'selector' for this
  50.292 -     * field.
  50.293 -     */
  50.294 -    u32 event_channel_pend[32];
  50.295 -    u32 event_channel_pend_sel;
  50.296 -    u32 event_channel_disc[32];
  50.297 -    u32 event_channel_disc_sel;
  50.298 +typedef struct arch_shared_info_st {
  50.299 +    unsigned int       rdtsc_bitshift;  /* tsc_timestamp uses N:N+31 of TSC. */
  50.300 +} arch_shared_info_t;
  50.301  
  50.302 -    /*
  50.303 -     * Time: The following abstractions are exposed: System Time, Clock Time,
  50.304 -     * Domain Virtual Time. Domains can access Cycle counter time directly.
  50.305 -     */
  50.306 -
  50.307 -    unsigned int       rdtsc_bitshift;  /* tsc_timestamp uses N:N+31 of TSC. */
  50.308 -    u64                cpu_freq;        /* CPU frequency (Hz).               */
  50.309 -
  50.310 -    /*
  50.311 -     * The following values are updated periodically (and not necessarily
  50.312 -     * atomically!). The guest OS detects this because 'time_version1' is
  50.313 -     * incremented just before updating these values, and 'time_version2' is
  50.314 -     * incremented immediately after. See Xenolinux code for an example of how 
  50.315 -     * to read these values safely (arch/xeno/kernel/time.c).
  50.316 -     */
  50.317 -    unsigned long      time_version1;   /* A version number for info below.  */
  50.318 -    unsigned long      time_version2;   /* A version number for info below.  */
  50.319 -    unsigned long      tsc_timestamp;   /* TSC at last update of time vals.  */
  50.320 -    u64                system_time;     /* Time, in nanosecs, since boot.    */
  50.321 -    unsigned long      wc_sec;          /* Secs  00:00:00 UTC, Jan 1, 1970.  */
  50.322 -    unsigned long      wc_usec;         /* Usecs 00:00:00 UTC, Jan 1, 1970.  */
  50.323 -    
  50.324 -    /* Domain Virtual Time */
  50.325 -    u64                domain_time;
  50.326 -	
  50.327 -    /*
  50.328 -     * Timeout values:
  50.329 -     * Allow a domain to specify a timeout value in system time and 
  50.330 -     * domain virtual time.
  50.331 -     */
  50.332 -    u64                wall_timeout;
  50.333 -    u64                domain_timeout;
  50.334 -
  50.335 -    /*
  50.336 -     * The index structures are all stored here for convenience. The rings 
  50.337 -     * themselves are allocated by Xen but the guestos must create its own 
  50.338 -     * mapping -- the machine address is given in the startinfo structure to 
  50.339 -     * allow this to happen.
  50.340 -     */
  50.341 -    net_idx_t net_idx[MAX_DOMAIN_VIFS];
  50.342 -
  50.343 -    execution_context_t execution_context;
  50.344 -
  50.345 -} shared_info_t;
  50.346  
  50.347  /*
  50.348 - * NB. We expect that this struct is smaller than a page.
  50.349 + * The following is all CPU context. Note that the i387_ctxt block is filled 
  50.350 + * in by FXSAVE if the CPU has feature FXSR; otherwise FSAVE is used.
  50.351   */
  50.352 -typedef struct start_info_st {
  50.353 -    /* THE FOLLOWING ARE FILLED IN BOTH ON INITIAL BOOT AND ON RESUME.     */
  50.354 -    unsigned long nr_pages;	  /* total pages allocated to this domain. */
  50.355 -    unsigned long shared_info;	  /* MACHINE address of shared info struct.*/
  50.356 -    unsigned long flags;          /* SIF_xxx flags.                        */
  50.357 -    /* THE FOLLOWING ARE ONLY FILLED IN ON INITIAL BOOT (NOT RESUME).      */
  50.358 -    unsigned long pt_base;	  /* VIRTUAL address of page directory.    */
  50.359 -    unsigned long mod_start;	  /* VIRTUAL address of pre-loaded module. */
  50.360 -    unsigned long mod_len;	  /* Size (bytes) of pre-loaded module.    */
  50.361 -    unsigned char cmd_line[1];	  /* Variable-length options.              */
  50.362 -} start_info_t;
  50.363 -
  50.364 -/* These flags are passed in the 'flags' field of start_info_t. */
  50.365 -#define SIF_PRIVILEGED 1          /* Is the domain privileged? */
  50.366 -#define SIF_INITDOMAIN 2          /* Is thsi the initial control domain? */
  50.367 -
  50.368 -/* For use in guest OSes. */
  50.369 -extern shared_info_t *HYPERVISOR_shared_info;
  50.370 +typedef struct full_execution_context_st
  50.371 +{
  50.372 +#define ECF_I387_VALID (1<<0)
  50.373 +    unsigned long flags;
  50.374 +    execution_context_t x86_64_ctxt;          /* User-level CPU registers     */
  50.375 +    char          i387_ctxt[512];           /* User-level FPU registers     */
  50.376 +    trap_info_t   trap_ctxt[256];           /* Virtual IDT                  */
  50.377 +    unsigned int  fast_trap_idx;            /* "Fast trap" vector offset    */
  50.378 +    unsigned long ldt_base, ldt_ents;       /* LDT (linear address, # ents) */
  50.379 +    unsigned long gdt_frames[16], gdt_ents; /* GDT (machine frames, # ents) */
  50.380 +    unsigned long ring1_ss, ring1_esp;      /* Virtual TSS (only SS1/ESP1)  */
  50.381 +    unsigned long pt_base;                  /* CR3 (pagetable base)         */
  50.382 +    unsigned long debugreg[8];              /* DB0-DB7 (debug registers)    */
  50.383 +    unsigned long event_callback_cs;        /* CS:EIP of event callback     */
  50.384 +    unsigned long event_callback_eip;
  50.385 +    unsigned long failsafe_callback_cs;     /* CS:EIP of failsafe callback  */
  50.386 +    unsigned long failsafe_callback_eip;
  50.387 +} full_execution_context_t;
  50.388  
  50.389  #endif /* !__ASSEMBLY__ */
  50.390  
    51.1 --- a/xen/include/xeno/sched.h	Wed Mar 10 13:44:42 2004 +0000
    51.2 +++ b/xen/include/xeno/sched.h	Wed Mar 10 13:46:20 2004 +0000
    51.3 @@ -6,6 +6,7 @@
    51.4  #include <xeno/spinlock.h>
    51.5  #include <asm/ptrace.h>
    51.6  #include <xeno/smp.h>
    51.7 +#include <asm/page.h>
    51.8  #include <asm/processor.h>
    51.9  #include <hypervisor-ifs/hypervisor-if.h>
   51.10  #include <hypervisor-ifs/dom0_ops.h>
   51.11 @@ -297,26 +298,4 @@ extern struct task_struct *task_list;
   51.12  
   51.13  extern void update_process_times(int user);
   51.14  
   51.15 -#include <asm/desc.h>
   51.16 -static inline void load_LDT(struct task_struct *p)
   51.17 -{
   51.18 -    unsigned int cpu;
   51.19 -    struct desc_struct *desc;
   51.20 -    unsigned long ents;
   51.21 -
   51.22 -    if ( (ents = p->mm.ldt_ents) == 0 )
   51.23 -    {
   51.24 -        __asm__ __volatile__ ( "lldt %%ax" : : "a" (0) );
   51.25 -    }
   51.26 -    else
   51.27 -    {
   51.28 -        cpu = smp_processor_id();
   51.29 -        desc = (struct desc_struct *)GET_GDT_ADDRESS(p) + __LDT(cpu);
   51.30 -        desc->a = ((LDT_VIRT_START&0xffff)<<16) | (ents*8-1);
   51.31 -        desc->b = (LDT_VIRT_START&(0xff<<24)) | 0x8200 | 
   51.32 -            ((LDT_VIRT_START&0xff0000)>>16);
   51.33 -        __asm__ __volatile__ ( "lldt %%ax" : : "a" (__LDT(cpu)<<3) );
   51.34 -    }
   51.35 -}
   51.36 -
   51.37  #endif