1.1 --- a/tools/libxc/xc_cpuid_x86.c	Mon Sep 29 15:45:38 2008 +0100
     1.2 +++ b/tools/libxc/xc_cpuid_x86.c	Tue Sep 30 10:14:54 2008 +0100
     1.3 @@ -92,6 +92,7 @@ static void amd_xc_cpuid_policy(
     1.4  
     1.5          /* Filter all other features according to a whitelist. */
     1.6          regs[2] &= ((is_64bit ? bitmaskof(X86_FEATURE_LAHF_LM) : 0) |
     1.7 +                    bitmaskof(X86_FEATURE_CMP_LEGACY) |
     1.8                      bitmaskof(X86_FEATURE_ALTMOVCR) |
     1.9                      bitmaskof(X86_FEATURE_ABM) |
    1.10                      bitmaskof(X86_FEATURE_SSE4A) |
    1.11 @@ -108,6 +109,14 @@ static void amd_xc_cpuid_policy(
    1.12                      bitmaskof(X86_FEATURE_3DNOWEXT));
    1.13          break;
    1.14      }
    1.15 +
    1.16 +    case 0x80000008:
    1.17 +        /*
    1.18 +         * ECX[15:12] is ApicIdCoreSize: ECX[7:0] is NumberOfCores (minus one).
    1.19 +         * Update to reflect vLAPIC_ID = vCPU_ID * 2.
    1.20 +         */
    1.21 +        regs[2] = ((regs[2] & 0xf000u) + 1) | ((regs[2] & 0xffu) << 1) | 1u;
    1.22 +        break;
    1.23      }
    1.24  }
    1.25  
    1.26 @@ -123,8 +132,13 @@ static void intel_xc_cpuid_policy(
    1.27          break;
    1.28  
    1.29      case 0x00000004:
    1.30 -        regs[0] &= 0x3FF;
    1.31 -        regs[3] &= 0x3FF;
    1.32 +        /*
    1.33 +         * EAX[31:26] is Maximum Cores Per Package (minus one).
    1.34 +         * Update to reflect vLAPIC_ID = vCPU_ID * 2.
    1.35 +         */
    1.36 +        regs[0] = (((regs[0] & 0x7c000000u) << 1) | 0x04000000u |
    1.37 +                   (regs[0] & 0x3ffu));
    1.38 +        regs[3] &= 0x3ffu;
    1.39          break;
    1.40  
    1.41      case 0x80000001: {
    1.42 @@ -141,6 +155,11 @@ static void intel_xc_cpuid_policy(
    1.43      case 0x80000005:
    1.44          regs[0] = regs[1] = regs[2] = 0;
    1.45          break;
    1.46 +
    1.47 +    case 0x80000008:
    1.48 +        /* Mask AMD Number of Cores information. */
    1.49 +        regs[2] = 0;
    1.50 +        break;
    1.51      }
    1.52  }
    1.53  
    1.54 @@ -162,6 +181,12 @@ static void xc_cpuid_hvm_policy(
    1.55          break;
    1.56  
    1.57      case 0x00000001:
    1.58 +        /*
    1.59 +         * EBX[23:16] is Maximum Logical Processors Per Package.
    1.60 +         * Update to reflect vLAPIC_ID = vCPU_ID * 2.
    1.61 +         */
    1.62 +        regs[1] = (regs[1] & 0x0000ffffu) | ((regs[1] & 0x007f0000u) << 1);
    1.63 +
    1.64          regs[2] &= (bitmaskof(X86_FEATURE_XMM3) |
    1.65                      bitmaskof(X86_FEATURE_SSSE3) |
    1.66                      bitmaskof(X86_FEATURE_CX16) |
    1.67 @@ -189,7 +214,8 @@ static void xc_cpuid_hvm_policy(
    1.68                      bitmaskof(X86_FEATURE_MMX) |
    1.69                      bitmaskof(X86_FEATURE_FXSR) |
    1.70                      bitmaskof(X86_FEATURE_XMM) |
    1.71 -                    bitmaskof(X86_FEATURE_XMM2));
    1.72 +                    bitmaskof(X86_FEATURE_XMM2) |
    1.73 +                    bitmaskof(X86_FEATURE_HT));
    1.74              
    1.75          /* We always support MTRR MSRs. */
    1.76          regs[3] |= bitmaskof(X86_FEATURE_MTRR);
    1.77 @@ -211,7 +237,7 @@ static void xc_cpuid_hvm_policy(
    1.78  
    1.79      case 0x80000008:
    1.80          regs[0] &= 0x0000ffffu;
    1.81 -        regs[1] = regs[2] = regs[3] = 0;
    1.82 +        regs[1] = regs[3] = 0;
    1.83          break;
    1.84  
    1.85      case 0x00000002: /* Intel cache info (dumped by AMD policy) */