1.1 --- a/xen/arch/x86/idle0_task.c	Sat Nov 20 00:32:32 2004 +0000
     1.2 +++ b/xen/arch/x86/idle0_task.c	Mon Nov 22 10:47:20 2004 +0000
     1.3 @@ -21,11 +21,4 @@ struct domain idle0_domain = IDLE0_DOMAI
     1.4  struct exec_domain idle0_exec_domain = IDLE0_EXEC_DOMAIN(idle0_exec_domain,
     1.5                                                           &idle0_domain);
     1.6  
     1.7 -/*
     1.8 - * per-CPU TSS segments. Threads are completely 'soft' on Linux,
     1.9 - * no more per-task TSS's. The TSS size is kept cacheline-aligned
    1.10 - * so they are allowed to end up in the .data.cacheline_aligned
    1.11 - * section. Since TSS's are completely CPU-local, we want them
    1.12 - * on exact cacheline boundaries, to eliminate cacheline ping-pong.
    1.13 - */ 
    1.14 -struct tss_struct init_tss[NR_CPUS] __cacheline_aligned;
    1.15 +struct tss_struct init_tss[NR_CPUS];

     2.1 --- a/xen/arch/x86/irq.c	Sat Nov 20 00:32:32 2004 +0000
     2.2 +++ b/xen/arch/x86/irq.c	Mon Nov 22 10:47:20 2004 +0000
     2.3 @@ -13,7 +13,7 @@
     2.4  #include <xen/sched.h>
     2.5  #include <asm/smpboot.h>
     2.6  
     2.7 -irq_desc_t irq_desc[NR_IRQS] __cacheline_aligned;
     2.8 +irq_desc_t irq_desc[NR_IRQS];
     2.9  
    2.10  static void __do_IRQ_guest(int irq);
    2.11  

     3.1 --- a/xen/arch/x86/memory.c	Sat Nov 20 00:32:32 2004 +0000
     3.2 +++ b/xen/arch/x86/memory.c	Mon Nov 22 10:47:20 2004 +0000
     3.3 @@ -130,7 +130,7 @@ static struct {
     3.4      unsigned long       cr0;
     3.5      /* If non-NULL, specifies a foreign subject domain for some operations. */
     3.6      struct domain      *foreign;
     3.7 -} percpu_info[NR_CPUS] __cacheline_aligned;
     3.8 +} __cacheline_aligned percpu_info[NR_CPUS];
     3.9  
    3.10  /*
    3.11   * Returns the current foreign domain; defaults to the currently-executing

     4.1 --- a/xen/arch/x86/smpboot.c	Sat Nov 20 00:32:32 2004 +0000
     4.2 +++ b/xen/arch/x86/smpboot.c	Mon Nov 22 10:47:20 2004 +0000
     4.3 @@ -67,7 +67,7 @@ static volatile unsigned long cpu_callin
     4.4  static volatile unsigned long cpu_callout_map;
     4.5  
     4.6  /* Per CPU bogomips and other parameters */
     4.7 -struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
     4.8 +struct cpuinfo_x86 cpu_data[NR_CPUS];
     4.9  
    4.10  /* Set when the idlers are all forked */
    4.11  int smp_threads_ready;

     5.1 --- a/xen/arch/x86/traps.c	Sat Nov 20 00:32:32 2004 +0000
     5.2 +++ b/xen/arch/x86/traps.c	Mon Nov 22 10:47:20 2004 +0000
     5.3 @@ -721,7 +721,11 @@ static void set_task_gate(unsigned int n
     5.4  
     5.5  void set_tss_desc(unsigned int n, void *addr)
     5.6  {
     5.7 -    _set_tssldt_desc(gdt_table+__TSS(n), (int)addr, 8299, 0x89);
     5.8 +    _set_tssldt_desc(
     5.9 +        gdt_table + __TSS(n),
    5.10 +        (int)addr,
    5.11 +        offsetof(struct tss_struct, __cacheline_filler) - 1,
    5.12 +        0x89);
    5.13  }
    5.14  
    5.15  void __init trap_init(void)

     6.1 --- a/xen/arch/x86/x86_32/xen.lds	Sat Nov 20 00:32:32 2004 +0000
     6.2 +++ b/xen/arch/x86/x86_32/xen.lds	Mon Nov 22 10:47:20 2004 +0000
     6.3 @@ -65,9 +65,6 @@ SECTIONS
     6.4    . = ALIGN(4096);
     6.5    .data.page_aligned : { *(.data.idt) } :text
     6.6  
     6.7 -  . = ALIGN(32);
     6.8 -  .data.cacheline_aligned : { *(.data.cacheline_aligned) } :text
     6.9 -
    6.10    __bss_start = .;		/* BSS */
    6.11    .bss : {
    6.12  	*(.bss)

     7.1 --- a/xen/arch/x86/x86_64/xen.lds	Sat Nov 20 00:32:32 2004 +0000
     7.2 +++ b/xen/arch/x86/x86_64/xen.lds	Mon Nov 22 10:47:20 2004 +0000
     7.3 @@ -63,9 +63,6 @@ SECTIONS
     7.4    . = ALIGN(4096);
     7.5    .data.page_aligned : { *(.data.idt) } :text
     7.6  
     7.7 -  . = ALIGN(32);
     7.8 -  .data.cacheline_aligned : { *(.data.cacheline_aligned) } :text
     7.9 -
    7.10    __bss_start = .;		/* BSS */
    7.11    .bss : {
    7.12  	*(.bss)

     8.1 --- a/xen/common/domain.c	Sat Nov 20 00:32:32 2004 +0000
     8.2 +++ b/xen/common/domain.c	Mon Nov 22 10:47:20 2004 +0000
     8.3 @@ -19,7 +19,7 @@
     8.4  #include <asm/domain_page.h>
     8.5  
     8.6  /* Both these structures are protected by the domlist_lock. */
     8.7 -rwlock_t domlist_lock __cacheline_aligned = RW_LOCK_UNLOCKED;
     8.8 +rwlock_t domlist_lock = RW_LOCK_UNLOCKED;
     8.9  struct domain *domain_hash[DOMAIN_HASH_SIZE];
    8.10  struct domain *domain_list;
    8.11  

     9.1 --- a/xen/common/softirq.c	Sat Nov 20 00:32:32 2004 +0000
     9.2 +++ b/xen/common/softirq.c	Mon Nov 22 10:47:20 2004 +0000
     9.3 @@ -17,7 +17,7 @@
     9.4  
     9.5  irq_cpustat_t irq_stat[NR_CPUS];
     9.6  
     9.7 -static softirq_handler softirq_handlers[NR_SOFTIRQS] __cacheline_aligned;
     9.8 +static softirq_handler softirq_handlers[NR_SOFTIRQS];
     9.9  
    9.10  asmlinkage void do_softirq()
    9.11  {

    10.1 --- a/xen/include/asm-x86/config.h	Sat Nov 20 00:32:32 2004 +0000
    10.2 +++ b/xen/include/asm-x86/config.h	Mon Nov 22 10:47:20 2004 +0000
    10.3 @@ -55,8 +55,6 @@
    10.4   */
    10.5  #define SMP_CACHE_BYTES 64
    10.6  #define NR_CPUS 16
    10.7 -#define __cacheline_aligned __attribute__((__aligned__(SMP_CACHE_BYTES)))
    10.8 -#define ____cacheline_aligned __cacheline_aligned
    10.9  
   10.10  /* Linkage for x86 */
   10.11  #define asmlinkage        __attribute__((regparm(0)))

    11.1 --- a/xen/include/asm-x86/hardirq.h	Sat Nov 20 00:32:32 2004 +0000
    11.2 +++ b/xen/include/asm-x86/hardirq.h	Mon Nov 22 10:47:20 2004 +0000
    11.3 @@ -4,13 +4,12 @@
    11.4  #include <xen/config.h>
    11.5  #include <xen/cache.h>
    11.6  
    11.7 -/* assembly code in softirq.h is sensitive to the offsets of these fields */
    11.8  typedef struct {
    11.9  	unsigned int __softirq_pending;
   11.10  	unsigned int __local_irq_count;
   11.11  	unsigned int __nmi_count;
   11.12  	unsigned long idle_timestamp;
   11.13 -} ____cacheline_aligned irq_cpustat_t;
   11.14 +} __cacheline_aligned irq_cpustat_t;
   11.15  
   11.16  #include <xen/irq_cpustat.h>	/* Standard mappings for irq_cpustat_t above */
   11.17  

    12.1 --- a/xen/include/asm-x86/pda.h	Sat Nov 20 00:32:32 2004 +0000
    12.2 +++ b/xen/include/asm-x86/pda.h	Mon Nov 22 10:47:20 2004 +0000
    12.3 @@ -14,7 +14,7 @@ struct x8664_pda {
    12.4  	int cpunumber;		    /* Logical CPU number */
    12.5  	char *irqstackptr;	/* top of irqstack */
    12.6  	unsigned long volatile *level4_pgt; 
    12.7 -} ____cacheline_aligned;
    12.8 +} __cacheline_aligned;
    12.9  
   12.10  #define PDA_STACKOFFSET (5*8)
   12.11  

    13.1 --- a/xen/include/asm-x86/processor.h	Sat Nov 20 00:32:32 2004 +0000
    13.2 +++ b/xen/include/asm-x86/processor.h	Mon Nov 22 10:47:20 2004 +0000
    13.3 @@ -281,7 +281,7 @@ static inline void clear_in_cr4 (unsigne
    13.4  #define IOBMP_BYTES             8192
    13.5  #define IOBMP_BYTES_PER_SELBIT  (IOBMP_BYTES / 64)
    13.6  #define IOBMP_BITS_PER_SELBIT   (IOBMP_BYTES_PER_SELBIT * 8)
    13.7 -#define IOBMP_OFFSET            offsetof(struct tss_struct,io_bitmap)
    13.8 +#define IOBMP_OFFSET            offsetof(struct tss_struct, io_bitmap)
    13.9  #define IOBMP_INVALID_OFFSET    0x8000
   13.10  
   13.11  struct i387_state {
   13.12 @@ -323,9 +323,9 @@ struct tss_struct {
   13.13      u16 trace;
   13.14  #endif
   13.15      u16 bitmap;
   13.16 -    u8  io_bitmap[IOBMP_BYTES];
   13.17 +    u8  io_bitmap[IOBMP_BYTES+1];
   13.18      /* Pads the TSS to be cacheline-aligned (total size is 0x2080). */
   13.19 -    u32 __cacheline_filler[6];
   13.20 +    u8 __cacheline_filler[23];
   13.21  };
   13.22  
   13.23  struct trap_bounce {

    14.1 --- a/xen/include/asm-x86/x86_32/uaccess.h	Sat Nov 20 00:32:32 2004 +0000
    14.2 +++ b/xen/include/asm-x86/x86_32/uaccess.h	Mon Nov 22 10:47:20 2004 +0000
    14.3 @@ -23,7 +23,7 @@
    14.4  #ifdef CONFIG_X86_INTEL_USERCOPY
    14.5  extern struct movsl_mask {
    14.6  	int mask;
    14.7 -} ____cacheline_aligned_in_smp movsl_mask;
    14.8 +} __cacheline_aligned movsl_mask;
    14.9  #endif
   14.10  
   14.11  #define __addr_ok(addr) ((unsigned long)(addr) < HYPERVISOR_VIRT_START)

    15.1 --- a/xen/include/asm-x86/x86_64/desc.h	Sat Nov 20 00:32:32 2004 +0000
    15.2 +++ b/xen/include/asm-x86/x86_64/desc.h	Mon Nov 22 10:47:20 2004 +0000
    15.3 @@ -82,7 +82,7 @@ union desc_union {
    15.4  struct per_cpu_gdt {
    15.5  	struct ldttss_desc tss;
    15.6  	struct ldttss_desc ldt; 
    15.7 -} ____cacheline_aligned; 
    15.8 +} __cacheline_aligned; 
    15.9  
   15.10  
   15.11  struct Xgt_desc_struct {

    16.1 --- a/xen/include/xen/cache.h	Sat Nov 20 00:32:32 2004 +0000
    16.2 +++ b/xen/include/xen/cache.h	Mon Nov 22 10:47:20 2004 +0000
    16.3 @@ -12,26 +12,8 @@
    16.4  #define SMP_CACHE_BYTES L1_CACHE_BYTES
    16.5  #endif
    16.6  
    16.7 -#ifndef ____cacheline_aligned
    16.8 -#define ____cacheline_aligned __attribute__((__aligned__(SMP_CACHE_BYTES)))
    16.9 -#endif
   16.10 -
   16.11 -#ifndef ____cacheline_aligned_in_smp
   16.12 -#ifdef CONFIG_SMP
   16.13 -#define ____cacheline_aligned_in_smp ____cacheline_aligned
   16.14 -#else
   16.15 -#define ____cacheline_aligned_in_smp
   16.16 -#endif /* CONFIG_SMP */
   16.17 +#ifndef __cacheline_aligned
   16.18 +#define __cacheline_aligned __attribute__((__aligned__(SMP_CACHE_BYTES)))
   16.19  #endif
   16.20  
   16.21 -#ifndef __cacheline_aligned
   16.22 -#ifdef MODULE
   16.23 -#define __cacheline_aligned ____cacheline_aligned
   16.24 -#else
   16.25 -#define __cacheline_aligned					\
   16.26 -  __attribute__((__aligned__(SMP_CACHE_BYTES),			\
   16.27 -		 __section__(".data.cacheline_aligned")))
   16.28 -#endif
   16.29 -#endif /* __cacheline_aligned */
   16.30 -
   16.31  #endif /* __LINUX_CACHE_H */

    17.1 --- a/xen/include/xen/irq.h	Sat Nov 20 00:32:32 2004 +0000
    17.2 +++ b/xen/include/xen/irq.h	Mon Nov 22 10:47:20 2004 +0000
    17.3 @@ -54,7 +54,7 @@ typedef struct {
    17.4      struct irqaction *action;	/* IRQ action list */
    17.5      unsigned int depth;		/* nested irq disables */
    17.6      spinlock_t lock;
    17.7 -} ____cacheline_aligned irq_desc_t;
    17.8 +} __cacheline_aligned irq_desc_t;
    17.9  
   17.10  extern irq_desc_t irq_desc[NR_IRQS];
   17.11  

    18.1 --- a/xen/include/xen/sched.h	Sat Nov 20 00:32:32 2004 +0000
    18.2 +++ b/xen/include/xen/sched.h	Mon Nov 22 10:47:20 2004 +0000
    18.3 @@ -6,6 +6,7 @@
    18.4  #include <xen/config.h>
    18.5  #include <xen/types.h>
    18.6  #include <xen/spinlock.h>
    18.7 +#include <xen/cache.h>
    18.8  #include <asm/regs.h>
    18.9  #include <xen/smp.h>
   18.10  #include <asm/page.h>