ia64/xen-unstable

changeset 11643:5ab400346b13

[HVM] Fix MSR read/write and add extra info when
write to MSR_EFER fails.
Signed-off-by: Keir Fraser <keir@xensource.com>
author kfraser@localhost.localdomain
date Wed Sep 27 10:17:03 2006 +0100 (2006-09-27)
parents 8905ffc1a3c8
children 7c5ea4f50bd9
files xen/arch/x86/hvm/svm/svm.c xen/arch/x86/hvm/vmx/vmx.c
line diff
     1.1 --- a/xen/arch/x86/hvm/svm/svm.c	Wed Sep 27 09:29:46 2006 +0100
     1.2 +++ b/xen/arch/x86/hvm/svm/svm.c	Wed Sep 27 10:17:03 2006 +0100
     1.3 @@ -282,7 +282,7 @@ static inline int long_mode_do_msr_read(
     1.4      switch (regs->ecx)
     1.5      {
     1.6      case MSR_EFER:
     1.7 -        msr_content = vmcb->efer;      
     1.8 +        msr_content = vmcb->efer;
     1.9          msr_content &= ~EFER_SVME;
    1.10          break;
    1.11  
    1.12 @@ -320,14 +320,14 @@ static inline int long_mode_do_msr_read(
    1.13      HVM_DBG_LOG(DBG_LEVEL_2, "mode_do_msr_read: msr_content: %"PRIx64"\n", 
    1.14                  msr_content);
    1.15  
    1.16 -    regs->eax = msr_content & 0xffffffff;
    1.17 -    regs->edx = msr_content >> 32;
    1.18 +    regs->eax = (u32)(msr_content >>  0);
    1.19 +    regs->edx = (u32)(msr_content >> 32);
    1.20      return 1;
    1.21  }
    1.22  
    1.23  static inline int long_mode_do_msr_write(struct cpu_user_regs *regs)
    1.24  {
    1.25 -    u64 msr_content = regs->eax | ((u64)regs->edx << 32);
    1.26 +    u64 msr_content = (u32)regs->eax | ((u64)regs->edx << 32);
    1.27      struct vcpu *vc = current;
    1.28      struct vmcb_struct *vmcb = vc->arch.hvm_svm.vmcb;
    1.29  
    1.30 @@ -342,7 +342,8 @@ static inline int long_mode_do_msr_write
    1.31          /* offending reserved bit will cause #GP */
    1.32          if ( msr_content & ~(EFER_LME | EFER_LMA | EFER_NX | EFER_SCE) )
    1.33          {
    1.34 -            printk("trying to set reserved bit in EFER\n");
    1.35 +            printk("Trying to set reserved bit in EFER: %016llx\n",
    1.36 +                   msr_content);
    1.37              svm_inject_exception(vc, TRAP_gp_fault, 1, 0);
    1.38              return 0;
    1.39          }
    1.40 @@ -355,7 +356,7 @@ static inline int long_mode_do_msr_write
    1.41                   !test_bit(SVM_CPU_STATE_PAE_ENABLED,
    1.42                             &vc->arch.hvm_svm.cpu_state) )
    1.43              {
    1.44 -                printk("trying to set LME bit when "
    1.45 +                printk("Trying to set LME bit when "
    1.46                         "in paging mode or PAE bit is not set\n");
    1.47                  svm_inject_exception(vc, TRAP_gp_fault, 1, 0);
    1.48                  return 0;
    1.49 @@ -1997,7 +1998,7 @@ static inline void svm_do_msr_access(
    1.50      else
    1.51      {
    1.52          inst_len = __get_instruction_length(vmcb, INSTR_WRMSR, NULL);
    1.53 -        msr_content = (regs->eax & 0xFFFFFFFF) | ((u64)regs->edx << 32);
    1.54 +        msr_content = (u32)regs->eax | ((u64)regs->edx << 32);
    1.55  
    1.56          switch (regs->ecx)
    1.57          {
     2.1 --- a/xen/arch/x86/hvm/vmx/vmx.c	Wed Sep 27 09:29:46 2006 +0100
     2.2 +++ b/xen/arch/x86/hvm/vmx/vmx.c	Wed Sep 27 10:17:03 2006 +0100
     2.3 @@ -269,15 +269,15 @@ static inline int long_mode_do_msr_read(
     2.4  
     2.5      HVM_DBG_LOG(DBG_LEVEL_2, "msr_content: 0x%"PRIx64, msr_content);
     2.6  
     2.7 -    regs->eax = msr_content & 0xffffffff;
     2.8 -    regs->edx = msr_content >> 32;
     2.9 +    regs->eax = (u32)(msr_content >>  0);
    2.10 +    regs->edx = (u32)(msr_content >> 32);
    2.11  
    2.12      return 1;
    2.13  }
    2.14  
    2.15  static inline int long_mode_do_msr_write(struct cpu_user_regs *regs)
    2.16  {
    2.17 -    u64 msr_content = regs->eax | ((u64)regs->edx << 32);
    2.18 +    u64 msr_content = (u32)regs->eax | ((u64)regs->edx << 32);
    2.19      struct vcpu *v = current;
    2.20      struct vmx_msr_state *msr = &v->arch.hvm_vmx.msr_content;
    2.21      struct vmx_msr_state *host_state = &this_cpu(percpu_msr);
    2.22 @@ -290,7 +290,8 @@ static inline int long_mode_do_msr_write
    2.23          /* offending reserved bit will cause #GP */
    2.24          if ( msr_content & ~(EFER_LME | EFER_LMA | EFER_NX | EFER_SCE) )
    2.25          {
    2.26 -            printk("trying to set reserved bit in EFER\n");
    2.27 +            printk("Trying to set reserved bit in EFER: %016llx\n",
    2.28 +                   msr_content);
    2.29              vmx_inject_hw_exception(v, TRAP_gp_fault, 0);
    2.30              return 0;
    2.31          }
    2.32 @@ -303,7 +304,7 @@ static inline int long_mode_do_msr_write
    2.33                   !test_bit(VMX_CPU_STATE_PAE_ENABLED,
    2.34                             &v->arch.hvm_vmx.cpu_state) )
    2.35              {
    2.36 -                printk("trying to set LME bit when "
    2.37 +                printk("Trying to set LME bit when "
    2.38                         "in paging mode or PAE bit is not set\n");
    2.39                  vmx_inject_hw_exception(v, TRAP_gp_fault, 0);
    2.40                  return 0;
    2.41 @@ -1924,7 +1925,7 @@ static inline void vmx_do_msr_write(stru
    2.42                  (unsigned long)regs->ecx, (unsigned long)regs->eax,
    2.43                  (unsigned long)regs->edx);
    2.44  
    2.45 -    msr_content = (regs->eax & 0xFFFFFFFF) | ((u64)regs->edx << 32);
    2.46 +    msr_content = (u32)regs->eax | ((u64)regs->edx << 32);
    2.47  
    2.48      switch (regs->ecx) {
    2.49      case MSR_IA32_TIME_STAMP_COUNTER: