1.1 --- a/xen/arch/ia64/xen/hyperprivop.S	Sun Aug 12 12:06:43 2007 -0600
     1.2 +++ b/xen/arch/ia64/xen/hyperprivop.S	Sun Aug 12 12:13:22 2007 -0600
     1.3 @@ -844,13 +844,9 @@ fast_tlb_no_tr_match:
     1.4  	
     1.5  1:	// check the guest VHPT
     1.6  	adds r19 = XSI_PTA_OFS-XSI_PSR_IC_OFS, r18;;
     1.7 -	ld8 r19=[r19];;
     1.8 -	tbit.nz p7,p0=r19,IA64_PTA_VF_BIT;;	// long format VHPT
     1.9 -(p7)	br.cond.spnt.few page_fault;;
    1.10 +	ld8 r19=[r19]
    1.11  	// if (!rr.ve || !(pta & IA64_PTA_VE)) take slow way for now
    1.12  	// FIXME: later, we deliver an alt_d/i vector after thash and itir
    1.13 -	tbit.z p7,p0=r19,IA64_PTA_VE_BIT
    1.14 -(p7)	br.cond.spnt.few page_fault;;
    1.15  	extr.u r25=r17,61,3
    1.16  	adds r21=XSI_RR0_OFS-XSI_PSR_IC_OFS,r18 ;;
    1.17  	shl r25=r25,3;;
    1.18 @@ -858,6 +854,10 @@ 1:	// check the guest VHPT
    1.19  	ld8 r22=[r21];;
    1.20  	tbit.z p7,p0=r22,0
    1.21  (p7)	br.cond.spnt.few page_fault;;
    1.22 +	tbit.z p7,p0=r19,IA64_PTA_VE_BIT
    1.23 +(p7)	br.cond.spnt.few page_fault;;
    1.24 +	tbit.nz p7,p0=r19,IA64_PTA_VF_BIT	// long format VHPT
    1.25 +(p7)	br.cond.spnt.few page_fault;;
    1.26  
    1.27  	// compute and save away itir (r22 & RR_PS_MASK)
    1.28  	movl r21=IA64_ITIR_PS_MASK;;

     2.1 --- a/xen/arch/ia64/xen/vcpu.c	Sun Aug 12 12:06:43 2007 -0600
     2.2 +++ b/xen/arch/ia64/xen/vcpu.c	Sun Aug 12 12:13:22 2007 -0600
     2.3 @@ -49,7 +49,6 @@ typedef union {
     2.4  #define	IA64_PTA_SZ_BIT		2
     2.5  #define	IA64_PTA_VF_BIT		8
     2.6  #define	IA64_PTA_BASE_BIT	15
     2.7 -#define	IA64_PTA_LFMT		(1UL << IA64_PTA_VF_BIT)
     2.8  #define	IA64_PTA_SZ(x)		(x##UL << IA64_PTA_SZ_BIT)
     2.9  
    2.10  #define IA64_PSR_NON_VIRT_BITS				\
    2.11 @@ -755,10 +754,6 @@ IA64FAULT vcpu_set_iva(VCPU * vcpu, u64 
    2.12  
    2.13  IA64FAULT vcpu_set_pta(VCPU * vcpu, u64 val)
    2.14  {
    2.15 -	if (val & IA64_PTA_LFMT) {
    2.16 -		printk("*** No support for VHPT long format yet!!\n");
    2.17 -		return IA64_ILLOP_FAULT;
    2.18 -	}
    2.19  	if (val & (0x3f << 9))	/* reserved fields */
    2.20  		return IA64_RSVDREG_FAULT;
    2.21  	if (val & 2)		/* reserved fields */
    2.22 @@ -1753,10 +1748,6 @@ IA64FAULT vcpu_translate(VCPU * vcpu, u6
    2.23  
    2.24  	/* check guest VHPT */
    2.25  	pta = PSCB(vcpu, pta);
    2.26 -	if (pta & IA64_PTA_VF) { /* long format VHPT - not implemented */
    2.27 -		panic_domain(vcpu_regs(vcpu), "can't do long format VHPT\n");
    2.28 -		//return is_data ? IA64_DATA_TLB_VECTOR:IA64_INST_TLB_VECTOR;
    2.29 -	}
    2.30  
    2.31  	*itir = rr & (RR_RID_MASK | RR_PS_MASK);
    2.32  	// note: architecturally, iha is optionally set for alt faults but
    2.33 @@ -1778,6 +1769,13 @@ IA64FAULT vcpu_translate(VCPU * vcpu, u6
    2.34  			IA64_ALT_INST_TLB_VECTOR;
    2.35  	}
    2.36  
    2.37 +	if (pta & IA64_PTA_VF) { /* long format VHPT - not implemented */
    2.38 +		/*
    2.39 +		 * minimal support: vhpt walker is really dumb and won't find
    2.40 +		 * anything
    2.41 +		 */
    2.42 +		return is_data ? IA64_DATA_TLB_VECTOR : IA64_INST_TLB_VECTOR;
    2.43 +	}
    2.44  	/* avoid recursively walking (short format) VHPT */
    2.45  	if (((address ^ pta) & ((itir_mask(pta) << 3) >> 3)) == 0)
    2.46  		return is_data ? IA64_DATA_TLB_VECTOR : IA64_INST_TLB_VECTOR;