1.1 --- a/.rootkeys	Tue Dec 02 16:30:20 2003 +0000
     1.2 +++ b/.rootkeys	Wed Dec 10 18:35:31 2003 +0000
     1.3 @@ -194,6 +194,8 @@ 3e4540cczrrQVyyj-s1-viyX1kMUlA xen/drive
     1.4  3e4540ccvQ9Dtoh9tV-L3ULUwN9X7g xen/drivers/net/e1000/e1000_main.c
     1.5  3e4540cc3t7_y-YLeyMG2pX9xtdXPA xen/drivers/net/e1000/e1000_osdep.h
     1.6  3e4540cct_8Ig-Y1W_vM2gS_u7mC0A xen/drivers/net/e1000/e1000_param.c
     1.7 +3fd76772aP8tdbOsmFpbsSr90TP0YA xen/drivers/net/e1000/kcompat.c
     1.8 +3fd76773I15-QqRK-uQAdEd-cBFVZw xen/drivers/net/e1000/kcompat.h
     1.9  3ddb79bfKvn9mt0kofpkw0QaWjxO6A xen/drivers/net/net_init.c
    1.10  3f0c428exbF4as5zi8GyGyDSUITmxg xen/drivers/net/pcnet32.c
    1.11  3ddb79bf_CBcu3QWYwq4bNAOnM2RqQ xen/drivers/net/setup.c

     2.1 --- a/xen/drivers/net/e1000/e1000.h	Tue Dec 02 16:30:20 2003 +0000
     2.2 +++ b/xen/drivers/net/e1000/e1000.h	Wed Dec 10 18:35:31 2003 +0000
     2.3 @@ -1,7 +1,7 @@
     2.4  /*******************************************************************************
     2.5  
     2.6    
     2.7 -  Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
     2.8 +  Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
     2.9    
    2.10    This program is free software; you can redistribute it and/or modify it 
    2.11    under the terms of the GNU General Public License as published by the Free 
    2.12 @@ -50,7 +50,7 @@
    2.13  #include <linux/timer.h>
    2.14  #include <linux/slab.h>
    2.15  #include <linux/interrupt.h>
    2.16 -//#include <linux/string.h>
    2.17 +#include <linux/string.h>
    2.18  //#include <linux/pagemap.h>
    2.19  #include <asm/bitops.h>
    2.20  #include <asm/io.h>
    2.21 @@ -63,9 +63,18 @@
    2.22  //#include <net/pkt_sched.h>
    2.23  #include <linux/list.h>
    2.24  #include <linux/reboot.h>
    2.25 -#include <linux/tqueue.h>
    2.26 +#ifdef NETIF_F_TSO
    2.27 +#include <net/checksum.h>
    2.28 +#endif
    2.29 +#ifdef SIOCGMIIPHY
    2.30 +#include <linux/mii.h>
    2.31 +#endif
    2.32 +#ifdef SIOCETHTOOL
    2.33  #include <linux/ethtool.h>
    2.34 +#endif
    2.35 +#ifdef NETIF_F_HW_VLAN_TX
    2.36  #include <linux/if_vlan.h>
    2.37 +#endif
    2.38  
    2.39  #define BAR_0		0
    2.40  #define BAR_1		1
    2.41 @@ -73,12 +82,10 @@
    2.42  #define PCI_DMA_64BIT	0xffffffffffffffffULL
    2.43  #define PCI_DMA_32BIT	0x00000000ffffffffULL
    2.44  
    2.45 +#include "kcompat.h"
    2.46  
    2.47  struct e1000_adapter;
    2.48  
    2.49 -// XEN XXX
    2.50 -// #define DBG 1
    2.51 -
    2.52  #include "e1000_hw.h"
    2.53  
    2.54  #if DBG
    2.55 @@ -97,6 +104,15 @@ struct e1000_adapter;
    2.56  #define E1000_RXBUFFER_8192  8192
    2.57  #define E1000_RXBUFFER_16384 16384
    2.58  
    2.59 +/* SmartSpeed delimiters */
    2.60 +#define E1000_SMARTSPEED_DOWNSHIFT 3
    2.61 +#define E1000_SMARTSPEED_MAX       15
    2.62 +
    2.63 +/* Packet Buffer allocations */
    2.64 +#define E1000_TX_FIFO_SIZE_SHIFT 0xA
    2.65 +#define E1000_TX_HEAD_ADDR_SHIFT 7
    2.66 +#define E1000_PBA_TX_MASK 0xFFFF0000
    2.67 +
    2.68  /* Flow Control High-Watermark: 43464 bytes */
    2.69  #define E1000_FC_HIGH_THRESH 0xA9C8
    2.70  
    2.71 @@ -109,13 +125,15 @@ struct e1000_adapter;
    2.72  /* How many Tx Descriptors do we need to call netif_wake_queue ? */
    2.73  #define E1000_TX_QUEUE_WAKE	16
    2.74  /* How many Rx Buffers do we bundle into one write to the hardware ? */
    2.75 -#define E1000_RX_BUFFER_WRITE	16
    2.76 -
    2.77 -#define E1000_JUMBO_PBA      0x00000028
    2.78 -#define E1000_DEFAULT_PBA    0x00000030
    2.79 +#define E1000_RX_BUFFER_WRITE	16	/* Must be power of 2 */
    2.80  
    2.81  #define AUTO_ALL_MODES       0
    2.82 -#define E1000_EEPROM_APME    4
    2.83 +#define E1000_EEPROM_APME    0x0400
    2.84 +
    2.85 +#ifndef E1000_MASTER_SLAVE
    2.86 +/* Switch to override PHY master/slave setting */
    2.87 +#define E1000_MASTER_SLAVE	e1000_ms_hw_default
    2.88 +#endif
    2.89  
    2.90  /* only works for sizes that are powers of 2 */
    2.91  #define E1000_ROUNDUP(i, size) ((i) = (((i) + (size) - 1) & ~((size) - 1)))
    2.92 @@ -127,6 +145,7 @@ struct e1000_buffer {
    2.93  	uint64_t dma;
    2.94  	unsigned long length;
    2.95  	unsigned long time_stamp;
    2.96 +	unsigned int next_to_watch;
    2.97  };
    2.98  
    2.99  struct e1000_desc_ring {
   2.100 @@ -147,7 +166,8 @@ struct e1000_desc_ring {
   2.101  };
   2.102  
   2.103  #define E1000_DESC_UNUSED(R) \
   2.104 -((((R)->next_to_clean + (R)->count) - ((R)->next_to_use + 1)) % ((R)->count))
   2.105 +	((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
   2.106 +	(R)->next_to_clean - (R)->next_to_use - 1)
   2.107  
   2.108  #define E1000_GET_DESC(R, i, type)	(&(((struct type *)((R).desc))[i]))
   2.109  #define E1000_RX_DESC(R, i)		E1000_GET_DESC(R, i, e1000_rx_desc)
   2.110 @@ -157,29 +177,40 @@ struct e1000_desc_ring {
   2.111  /* board specific private data structure */
   2.112  
   2.113  struct e1000_adapter {
   2.114 +	struct timer_list tx_fifo_stall_timer;
   2.115  	struct timer_list watchdog_timer;
   2.116  	struct timer_list phy_info_timer;
   2.117 +#ifdef NETIF_F_HW_VLAN_TX
   2.118  	struct vlan_group *vlgrp;
   2.119 -	char *id_string;
   2.120 +#endif
   2.121  	uint32_t bd_number;
   2.122  	uint32_t rx_buffer_len;
   2.123  	uint32_t part_num;
   2.124  	uint32_t wol;
   2.125 +	uint32_t smartspeed;
   2.126  	uint16_t link_speed;
   2.127  	uint16_t link_duplex;
   2.128  	spinlock_t stats_lock;
   2.129  	atomic_t irq_sem;
   2.130 -	struct tq_struct tx_timeout_task;
   2.131 +	struct work_struct tx_timeout_task;
   2.132 +    	uint8_t fc_autoneg;
   2.133  
   2.134 +#ifdef ETHTOOL_PHYS_ID
   2.135  	struct timer_list blink_timer;
   2.136  	unsigned long led_status;
   2.137 +#endif
   2.138  
   2.139  	/* TX */
   2.140  	struct e1000_desc_ring tx_ring;
   2.141  	uint32_t txd_cmd;
   2.142  	uint32_t tx_int_delay;
   2.143  	uint32_t tx_abs_int_delay;
   2.144 -	int max_data_per_txd;
   2.145 +	uint32_t gotcl;
   2.146 +	uint32_t tx_fifo_head;
   2.147 +	uint32_t tx_head_addr;
   2.148 +	uint32_t tx_fifo_size;
   2.149 +	atomic_t tx_fifo_stall;
   2.150 +	boolean_t pcix_82544;
   2.151  
   2.152  	/* RX */
   2.153  	struct e1000_desc_ring rx_ring;
   2.154 @@ -188,6 +219,10 @@ struct e1000_adapter {
   2.155  	uint32_t rx_int_delay;
   2.156  	uint32_t rx_abs_int_delay;
   2.157  	boolean_t rx_csum;
   2.158 +	uint32_t gorcl;
   2.159 +
   2.160 +	/* Interrupt Throttle Rate */
   2.161 +	uint32_t itr;
   2.162  
   2.163  	/* OS defined structs */
   2.164  	struct net_device *netdev;
   2.165 @@ -200,10 +235,25 @@ struct e1000_adapter {
   2.166  	struct e1000_phy_info phy_info;
   2.167  	struct e1000_phy_stats phy_stats;
   2.168  
   2.169 -	uint32_t pci_state[16];
   2.170 -	char ifname[IFNAMSIZ];
   2.171 +#ifdef ETHTOOL_TEST
   2.172 +	uint32_t test_icr;
   2.173 +	struct e1000_desc_ring test_tx_ring;
   2.174 +	struct e1000_desc_ring test_rx_ring;
   2.175 +#endif
   2.176  
   2.177 -	/* All new definitions should go below this point! */
   2.178 -	spinlock_t tx_lock;
   2.179 +#ifdef E1000_COUNT_ICR
   2.180 +	uint64_t icr_txdw;
   2.181 +	uint64_t icr_txqe;
   2.182 +	uint64_t icr_lsc;
   2.183 +	uint64_t icr_rxseq;
   2.184 +	uint64_t icr_rxdmt;
   2.185 +	uint64_t icr_rxo;
   2.186 +	uint64_t icr_rxt;
   2.187 +	uint64_t icr_mdac;
   2.188 +	uint64_t icr_rxcfg;
   2.189 +	uint64_t icr_gpi;
   2.190 +#endif
   2.191 +
   2.192 +	uint32_t pci_state[16];
   2.193  };
   2.194  #endif /* _E1000_H_ */

     3.1 --- a/xen/drivers/net/e1000/e1000_ethtool.c	Tue Dec 02 16:30:20 2003 +0000
     3.2 +++ b/xen/drivers/net/e1000/e1000_ethtool.c	Wed Dec 10 18:35:31 2003 +0000
     3.3 @@ -1,7 +1,7 @@
     3.4  /*******************************************************************************
     3.5  
     3.6    
     3.7 -  Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
     3.8 +  Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
     3.9    
    3.10    This program is free software; you can redistribute it and/or modify it 
    3.11    under the terms of the GNU General Public License as published by the Free 
    3.12 @@ -30,6 +30,7 @@
    3.13  
    3.14  #include "e1000.h"
    3.15  
    3.16 +#ifdef	SIOCETHTOOL
    3.17  #include <asm/uaccess.h>
    3.18  
    3.19  extern char e1000_driver_name[];
    3.20 @@ -38,16 +39,69 @@ extern char e1000_driver_version[];
    3.21  extern int e1000_up(struct e1000_adapter *adapter);
    3.22  extern void e1000_down(struct e1000_adapter *adapter);
    3.23  extern void e1000_reset(struct e1000_adapter *adapter);
    3.24 +extern int e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx);
    3.25  
    3.26 -static char e1000_gstrings_stats[][ETH_GSTRING_LEN] = {
    3.27 -	"rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
    3.28 -	"tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
    3.29 -	"rx_length_errors", "rx_over_errors", "rx_crc_errors",
    3.30 -	"rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
    3.31 -	"tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
    3.32 -	"tx_heartbeat_errors", "tx_window_errors",
    3.33 +#ifndef ETH_GSTRING_LEN
    3.34 +#define ETH_GSTRING_LEN 32
    3.35 +#endif
    3.36 +#ifdef	ETHTOOL_GSTATS
    3.37 +struct e1000_stats {
    3.38 +	char stat_string[ETH_GSTRING_LEN];
    3.39 +	int sizeof_stat;
    3.40 +	int stat_offset;
    3.41  };
    3.42 -#define E1000_STATS_LEN	sizeof(e1000_gstrings_stats) / ETH_GSTRING_LEN
    3.43 +
    3.44 +#define E1000_STAT(m) sizeof(((struct e1000_adapter *)0)->m), \
    3.45 +		      offsetof(struct e1000_adapter, m)
    3.46 +static struct e1000_stats e1000_gstrings_stats[] = {
    3.47 +	{ "rx_packets", E1000_STAT(net_stats.rx_packets) },
    3.48 +	{ "tx_packets", E1000_STAT(net_stats.tx_packets) },
    3.49 +	{ "rx_bytes", E1000_STAT(net_stats.rx_bytes) },
    3.50 +	{ "tx_bytes", E1000_STAT(net_stats.tx_bytes) },
    3.51 +	{ "rx_errors", E1000_STAT(net_stats.rx_errors) },
    3.52 +	{ "tx_errors", E1000_STAT(net_stats.tx_errors) },
    3.53 +	{ "rx_dropped", E1000_STAT(net_stats.rx_dropped) },
    3.54 +	{ "tx_dropped", E1000_STAT(net_stats.tx_dropped) },
    3.55 +	{ "multicast", E1000_STAT(net_stats.multicast) },
    3.56 +	{ "collisions", E1000_STAT(net_stats.collisions) },
    3.57 +	{ "rx_length_errors", E1000_STAT(net_stats.rx_length_errors) },
    3.58 +	{ "rx_over_errors", E1000_STAT(net_stats.rx_over_errors) },
    3.59 +	{ "rx_crc_errors", E1000_STAT(net_stats.rx_crc_errors) },
    3.60 +	{ "rx_frame_errors", E1000_STAT(net_stats.rx_frame_errors) },
    3.61 +	{ "rx_fifo_errors", E1000_STAT(net_stats.rx_fifo_errors) },
    3.62 +	{ "rx_missed_errors", E1000_STAT(net_stats.rx_missed_errors) },
    3.63 +	{ "tx_aborted_errors", E1000_STAT(net_stats.tx_aborted_errors) },
    3.64 +	{ "tx_carrier_errors", E1000_STAT(net_stats.tx_carrier_errors) },
    3.65 +	{ "tx_fifo_errors", E1000_STAT(net_stats.tx_fifo_errors) },
    3.66 +	{ "tx_heartbeat_errors", E1000_STAT(net_stats.tx_heartbeat_errors) },
    3.67 +	{ "tx_window_errors", E1000_STAT(net_stats.tx_window_errors) },
    3.68 +	{ "tx_abort_late_coll", E1000_STAT(stats.latecol) },
    3.69 +	{ "tx_deferred_ok", E1000_STAT(stats.dc) },
    3.70 +	{ "tx_single_coll_ok", E1000_STAT(stats.scc) },
    3.71 +	{ "tx_multi_coll_ok", E1000_STAT(stats.mcc) },
    3.72 +	{ "rx_long_length_errors", E1000_STAT(stats.roc) },
    3.73 +	{ "rx_short_length_errors", E1000_STAT(stats.ruc) },
    3.74 +	{ "rx_align_errors", E1000_STAT(stats.algnerrc) },
    3.75 +	{ "tx_tcp_seg_good", E1000_STAT(stats.tsctc) },
    3.76 +	{ "tx_tcp_seg_failed", E1000_STAT(stats.tsctfc) },
    3.77 +	{ "rx_flow_control_xon", E1000_STAT(stats.xonrxc) },
    3.78 +	{ "rx_flow_control_xoff", E1000_STAT(stats.xoffrxc) },
    3.79 +	{ "tx_flow_control_xon", E1000_STAT(stats.xontxc) },
    3.80 +	{ "tx_flow_control_xoff", E1000_STAT(stats.xofftxc) },
    3.81 +	{ "rx_csum_offload_good", E1000_STAT(hw_csum_good) },
    3.82 +	{ "rx_csum_offload_errors", E1000_STAT(hw_csum_err) }
    3.83 +};
    3.84 +#define E1000_STATS_LEN	\
    3.85 +	sizeof(e1000_gstrings_stats) / sizeof(struct e1000_stats)
    3.86 +#endif	/* ETHTOOL_GSTATS */
    3.87 +#ifdef	ETHTOOL_TEST
    3.88 +static char e1000_gstrings_test[][ETH_GSTRING_LEN] = {
    3.89 +	"Register test  (offline)", "Eeprom test    (offline)",
    3.90 +	"Interrupt test (offline)", "Loopback test  (offline)",
    3.91 +	"Link test   (on/offline)"
    3.92 +};
    3.93 +#define E1000_TEST_LEN sizeof(e1000_gstrings_test) / ETH_GSTRING_LEN
    3.94 +#endif	/* ETHTOOL_TEST */
    3.95  
    3.96  static void
    3.97  e1000_ethtool_gset(struct e1000_adapter *adapter, struct ethtool_cmd *ecmd)
    3.98 @@ -129,30 +183,9 @@ e1000_ethtool_sset(struct e1000_adapter 
    3.99  		hw->autoneg = 1;
   3.100  		hw->autoneg_advertised = 0x002F;
   3.101  		ecmd->advertising = 0x002F;
   3.102 -	} else {
   3.103 -		hw->autoneg = 0;
   3.104 -		switch(ecmd->speed + ecmd->duplex) {
   3.105 -		case SPEED_10 + DUPLEX_HALF:
   3.106 -			hw->forced_speed_duplex = e1000_10_half;
   3.107 -			break;
   3.108 -		case SPEED_10 + DUPLEX_FULL:
   3.109 -			hw->forced_speed_duplex = e1000_10_full;
   3.110 -			break;
   3.111 -		case SPEED_100 + DUPLEX_HALF:
   3.112 -			hw->forced_speed_duplex = e1000_100_half;
   3.113 -			break;
   3.114 -		case SPEED_100 + DUPLEX_FULL:
   3.115 -			hw->forced_speed_duplex = e1000_100_full;
   3.116 -			break;
   3.117 -		case SPEED_1000 + DUPLEX_FULL:
   3.118 -			hw->autoneg = 1;
   3.119 -			hw->autoneg_advertised = ADVERTISE_1000_FULL;
   3.120 -			break;
   3.121 -		case SPEED_1000 + DUPLEX_HALF: /* not supported */
   3.122 -		default:
   3.123 +	} else
   3.124 +		if(e1000_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex))
   3.125  			return -EINVAL;
   3.126 -		}
   3.127 -	}
   3.128  
   3.129  	/* reset the link */
   3.130  
   3.131 @@ -165,16 +198,60 @@ e1000_ethtool_sset(struct e1000_adapter 
   3.132  	return 0;
   3.133  }
   3.134  
   3.135 -static inline int
   3.136 -e1000_eeprom_size(struct e1000_hw *hw)
   3.137 +#ifdef	ETHTOOL_GPAUSEPARAM
   3.138 +static int
   3.139 +e1000_ethtool_gpause(struct e1000_adapter *adapter,
   3.140 +                     struct ethtool_pauseparam *epause)
   3.141  {
   3.142 -	if((hw->mac_type > e1000_82544) &&
   3.143 -	   (E1000_READ_REG(hw, EECD) & E1000_EECD_SIZE))
   3.144 -		return 512;
   3.145 -	else
   3.146 -		return 128;
   3.147 +	struct e1000_hw *hw = &adapter->hw;
   3.148 +	
   3.149 +	epause->autoneg = 
   3.150 +		(adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
   3.151 +	
   3.152 +	if(hw->fc == e1000_fc_rx_pause)
   3.153 +		epause->rx_pause = 1;
   3.154 +	else if(hw->fc == e1000_fc_tx_pause)
   3.155 +		epause->tx_pause = 1;
   3.156 +	else if(hw->fc == e1000_fc_full) {
   3.157 +		epause->rx_pause = 1;
   3.158 +		epause->tx_pause = 1;
   3.159 +	}
   3.160 +	
   3.161 +	return 0;
   3.162  }
   3.163 +#endif /* ETHTOOL_GPAUSEPARAM */
   3.164  
   3.165 +#ifdef	ETHTOOL_SPAUSEPARAM
   3.166 +static int
   3.167 +e1000_ethtool_spause(struct e1000_adapter *adapter,
   3.168 +                     struct ethtool_pauseparam *epause)
   3.169 +{
   3.170 +	struct e1000_hw *hw = &adapter->hw;
   3.171 +	
   3.172 +	adapter->fc_autoneg = epause->autoneg;
   3.173 +
   3.174 +	if(epause->rx_pause && epause->tx_pause)
   3.175 +		hw->fc = e1000_fc_full;
   3.176 +	else if(epause->rx_pause && !epause->tx_pause)
   3.177 +		hw->fc = e1000_fc_rx_pause;
   3.178 +	else if(!epause->rx_pause && epause->tx_pause)
   3.179 +		hw->fc = e1000_fc_tx_pause;
   3.180 +	else if(!epause->rx_pause && !epause->tx_pause)
   3.181 +		hw->fc = e1000_fc_none;
   3.182 +
   3.183 +	hw->original_fc = hw->fc;
   3.184 +
   3.185 +	if(netif_running(adapter->netdev)) {
   3.186 +		e1000_down(adapter);
   3.187 +		e1000_up(adapter);
   3.188 +	} else
   3.189 +		e1000_reset(adapter);
   3.190 +	
   3.191 +	return 0;
   3.192 +}
   3.193 +#endif /* ETHTOOL_SPAUSEPARAM */
   3.194 +
   3.195 +#ifdef	ETHTOOL_GDRVINFO
   3.196  static void
   3.197  e1000_ethtool_gdrvinfo(struct e1000_adapter *adapter,
   3.198                         struct ethtool_drvinfo *drvinfo)
   3.199 @@ -183,17 +260,32 @@ e1000_ethtool_gdrvinfo(struct e1000_adap
   3.200  	strncpy(drvinfo->version, e1000_driver_version, 32);
   3.201  	strncpy(drvinfo->fw_version, "N/A", 32);
   3.202  	strncpy(drvinfo->bus_info, adapter->pdev->slot_name, 32);
   3.203 +#ifdef	ETHTOOL_GSTATS
   3.204  	drvinfo->n_stats = E1000_STATS_LEN;
   3.205 +#endif	/* ETHTOOL_GSTATS */
   3.206 +#ifdef	ETHTOOL_TEST
   3.207 +	drvinfo->testinfo_len = E1000_TEST_LEN;
   3.208 +#endif	/* ETHTOOL_TEST */
   3.209 +#ifdef	ETHTOOL_GEEPROM  /* GREGS broken in earlier ethtool.h */
   3.210 +#ifdef	ETHTOOL_GREGS
   3.211  #define E1000_REGS_LEN 32
   3.212  	drvinfo->regdump_len  = E1000_REGS_LEN * sizeof(uint32_t);
   3.213 -	drvinfo->eedump_len  = e1000_eeprom_size(&adapter->hw);
   3.214 +#endif	/* ETHTOOL_GREGS */
   3.215 +#endif	/* ETHTOOL_GEEPROM */
   3.216 +#ifdef	ETHTOOL_GEEPROM
   3.217 +	drvinfo->eedump_len = adapter->hw.eeprom.word_size * 2;
   3.218 +#endif	/* ETHTOOL_GEEPROM */
   3.219  }
   3.220 +#endif	/* ETHTOOL_GDRVINFO */
   3.221  
   3.222 +#ifdef	ETHTOOL_GEEPROM  /* GREGS broken in earlier ethtool.h */
   3.223 +#ifdef  ETHTOOL_GREGS
   3.224  static void
   3.225  e1000_ethtool_gregs(struct e1000_adapter *adapter,
   3.226                      struct ethtool_regs *regs, uint32_t *regs_buff)
   3.227  {
   3.228  	struct e1000_hw *hw = &adapter->hw;
   3.229 +	uint16_t phy_data;
   3.230  
   3.231  	regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
   3.232  
   3.233 @@ -212,17 +304,75 @@ e1000_ethtool_gregs(struct e1000_adapter
   3.234  	regs_buff[10] = E1000_READ_REG(hw, TDT);
   3.235  	regs_buff[11] = E1000_READ_REG(hw, TIDV);
   3.236  
   3.237 +	regs_buff[12] = adapter->hw.phy_type;  /* PHY type (IGP=1, M88=0) */
   3.238 +	if(hw->phy_type == e1000_phy_igp) {
   3.239 +		e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT,
   3.240 +				    IGP01E1000_PHY_AGC_A);
   3.241 +		e1000_read_phy_reg(hw, IGP01E1000_PHY_AGC_A &
   3.242 +				   IGP01E1000_PHY_PAGE_SELECT, &phy_data);
   3.243 +		regs_buff[13] = (uint32_t)phy_data; /* cable length */
   3.244 +		e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT,
   3.245 +				    IGP01E1000_PHY_AGC_B);
   3.246 +		e1000_read_phy_reg(hw, IGP01E1000_PHY_AGC_B &
   3.247 +				   IGP01E1000_PHY_PAGE_SELECT, &phy_data);
   3.248 +		regs_buff[14] = (uint32_t)phy_data; /* cable length */
   3.249 +		e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT,
   3.250 +				    IGP01E1000_PHY_AGC_C);
   3.251 +		e1000_read_phy_reg(hw, IGP01E1000_PHY_AGC_C &
   3.252 +				   IGP01E1000_PHY_PAGE_SELECT, &phy_data);
   3.253 +		regs_buff[15] = (uint32_t)phy_data; /* cable length */
   3.254 +		e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT,
   3.255 +				    IGP01E1000_PHY_AGC_D);
   3.256 +		e1000_read_phy_reg(hw, IGP01E1000_PHY_AGC_D &
   3.257 +				   IGP01E1000_PHY_PAGE_SELECT, &phy_data);
   3.258 +		regs_buff[16] = (uint32_t)phy_data; /* cable length */
   3.259 +		regs_buff[17] = 0; /* extended 10bt distance (not needed) */
   3.260 +		e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0);
   3.261 +		e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS &
   3.262 +				   IGP01E1000_PHY_PAGE_SELECT, &phy_data);
   3.263 +		regs_buff[18] = (uint32_t)phy_data; /* cable polarity */
   3.264 +		e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT,
   3.265 +				    IGP01E1000_PHY_PCS_INIT_REG);
   3.266 +		e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG &
   3.267 +				   IGP01E1000_PHY_PAGE_SELECT, &phy_data);
   3.268 +		regs_buff[19] = (uint32_t)phy_data; /* cable polarity */
   3.269 +		regs_buff[20] = 0; /* polarity correction enabled (always) */
   3.270 +		regs_buff[22] = 0; /* phy receive errors (unavailable) */
   3.271 +		regs_buff[23] = regs_buff[18]; /* mdix mode */
   3.272 +		e1000_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT, 0x0);
   3.273 +	} else {
   3.274 +        	e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
   3.275 +		regs_buff[13] = (uint32_t)phy_data; /* cable length */
   3.276 +		regs_buff[14] = 0;  /* Dummy (to align w/ IGP phy reg dump) */
   3.277 +		regs_buff[15] = 0;  /* Dummy (to align w/ IGP phy reg dump) */
   3.278 +		regs_buff[16] = 0;  /* Dummy (to align w/ IGP phy reg dump) */
   3.279 +        	e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
   3.280 +		regs_buff[17] = (uint32_t)phy_data; /* extended 10bt distance */
   3.281 +		regs_buff[18] = regs_buff[13]; /* cable polarity */
   3.282 +		regs_buff[19] = 0;  /* Dummy (to align w/ IGP phy reg dump) */
   3.283 +		regs_buff[20] = regs_buff[17]; /* polarity correction */
   3.284 +		/* phy receive errors */
   3.285 +		regs_buff[22] = adapter->phy_stats.receive_errors;
   3.286 +		regs_buff[23] = regs_buff[13]; /* mdix mode */
   3.287 +	}
   3.288 +	regs_buff[21] = adapter->phy_stats.idle_errors;  /* phy idle errors */
   3.289 +	e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
   3.290 +	regs_buff[24] = (uint32_t)phy_data;  /* phy local receiver status */
   3.291 +	regs_buff[25] = regs_buff[24];  /* phy remote receiver status */
   3.292 +
   3.293  	return;
   3.294  }
   3.295 +#endif  /* ETHTOOL_GREGS */
   3.296 +#endif	/* ETHTOOL_GEEPROM */
   3.297  
   3.298 +#ifdef	ETHTOOL_GEEPROM
   3.299  static int
   3.300  e1000_ethtool_geeprom(struct e1000_adapter *adapter,
   3.301                        struct ethtool_eeprom *eeprom, uint16_t *eeprom_buff)
   3.302  {
   3.303  	struct e1000_hw *hw = &adapter->hw;
   3.304 -	int max_len, first_word, last_word;
   3.305 +	int first_word, last_word;
   3.306  	int ret_val = 0;
   3.307 -	int i;
   3.308  
   3.309  	if(eeprom->len == 0) {
   3.310  		ret_val = -EINVAL;
   3.311 @@ -231,35 +381,42 @@ e1000_ethtool_geeprom(struct e1000_adapt
   3.312  
   3.313  	eeprom->magic = hw->vendor_id | (hw->device_id << 16);
   3.314  
   3.315 -	max_len = e1000_eeprom_size(hw);
   3.316 -
   3.317  	if(eeprom->offset > eeprom->offset + eeprom->len) {
   3.318  		ret_val = -EINVAL;
   3.319  		goto geeprom_error;
   3.320  	}
   3.321  
   3.322 -	if((eeprom->offset + eeprom->len) > max_len)
   3.323 -		eeprom->len = (max_len - eeprom->offset);
   3.324 +	if((eeprom->offset + eeprom->len) > (hw->eeprom.word_size * 2))
   3.325 +		eeprom->len = ((hw->eeprom.word_size * 2) - eeprom->offset);
   3.326  
   3.327  	first_word = eeprom->offset >> 1;
   3.328  	last_word = (eeprom->offset + eeprom->len - 1) >> 1;
   3.329  
   3.330 -	for(i = 0; i <= (last_word - first_word); i++)
   3.331 -		e1000_read_eeprom(hw, first_word + i, &eeprom_buff[i]);
   3.332 -
   3.333 +	if(hw->eeprom.type == e1000_eeprom_spi)
   3.334 +		ret_val = e1000_read_eeprom(hw, first_word,
   3.335 +					    last_word - first_word + 1,
   3.336 +					    eeprom_buff);
   3.337 +	else {
   3.338 +		uint16_t i;
   3.339 +		for (i = 0; i < last_word - first_word + 1; i++)
   3.340 +			if((ret_val = e1000_read_eeprom(hw, first_word + i, 1,
   3.341 +							&eeprom_buff[i])))
   3.342 +				break;
   3.343 +	}
   3.344  geeprom_error:
   3.345  	return ret_val;
   3.346  }
   3.347 +#endif	/* ETHTOOL_GEEPROM */
   3.348  
   3.349 +#ifdef	ETHTOOL_SEEPROM
   3.350  static int
   3.351  e1000_ethtool_seeprom(struct e1000_adapter *adapter,
   3.352                        struct ethtool_eeprom *eeprom, void *user_data)
   3.353  {
   3.354  	struct e1000_hw *hw = &adapter->hw;
   3.355  	uint16_t *eeprom_buff;
   3.356 -	int max_len, first_word, last_word;
   3.357  	void *ptr;
   3.358 -	int i;
   3.359 +	int max_len, first_word, last_word, ret_val = 0;
   3.360  
   3.361  	if(eeprom->len == 0)
   3.362  		return -EOPNOTSUPP;
   3.363 @@ -267,7 +424,7 @@ e1000_ethtool_seeprom(struct e1000_adapt
   3.364  	if(eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
   3.365  		return -EFAULT;
   3.366  
   3.367 -	max_len = e1000_eeprom_size(hw);
   3.368 +	max_len = hw->eeprom.word_size * 2;
   3.369  
   3.370  	if((eeprom->offset + eeprom->len) > max_len)
   3.371  		eeprom->len = (max_len - eeprom->offset);
   3.372 @@ -275,7 +432,7 @@ e1000_ethtool_seeprom(struct e1000_adapt
   3.373  	first_word = eeprom->offset >> 1;
   3.374  	last_word = (eeprom->offset + eeprom->len - 1) >> 1;
   3.375  	eeprom_buff = kmalloc(max_len, GFP_KERNEL);
   3.376 -	if(eeprom_buff == NULL)
   3.377 +	if(!eeprom_buff)
   3.378  		return -ENOMEM;
   3.379  
   3.380  	ptr = (void *)eeprom_buff;
   3.381 @@ -283,32 +440,807 @@ e1000_ethtool_seeprom(struct e1000_adapt
   3.382  	if(eeprom->offset & 1) {
   3.383  		/* need read/modify/write of first changed EEPROM word */
   3.384  		/* only the second byte of the word is being modified */
   3.385 -		e1000_read_eeprom(hw, first_word, &eeprom_buff[0]);
   3.386 +		ret_val = e1000_read_eeprom(hw, first_word, 1,
   3.387 +					    &eeprom_buff[0]);
   3.388  		ptr++;
   3.389  	}
   3.390 -	if((eeprom->offset + eeprom->len) & 1) {
   3.391 +	if(((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
   3.392  		/* need read/modify/write of last changed EEPROM word */
   3.393  		/* only the first byte of the word is being modified */
   3.394 -		e1000_read_eeprom(hw, last_word,
   3.395 +		ret_val = e1000_read_eeprom(hw, last_word, 1,
   3.396  		                  &eeprom_buff[last_word - first_word]);
   3.397  	}
   3.398 -	if(copy_from_user(ptr, user_data, eeprom->len)) {
   3.399 -		kfree(eeprom_buff);
   3.400 -		return -EFAULT;
   3.401 +	if((ret_val != 0) || copy_from_user(ptr, user_data, eeprom->len)) {
   3.402 +		ret_val = -EFAULT;
   3.403 +		goto seeprom_error;
   3.404  	}
   3.405  
   3.406 -	for(i = 0; i <= (last_word - first_word); i++)
   3.407 -		e1000_write_eeprom(hw, first_word + i, eeprom_buff[i]);
   3.408 +	ret_val = e1000_write_eeprom(hw, first_word,
   3.409 +				     last_word - first_word + 1, eeprom_buff);
   3.410  
   3.411  	/* Update the checksum over the first part of the EEPROM if needed */
   3.412 -	if(first_word <= EEPROM_CHECKSUM_REG)
   3.413 +	if((ret_val == 0) && first_word <= EEPROM_CHECKSUM_REG)
   3.414  		e1000_update_eeprom_checksum(hw);
   3.415  
   3.416 +seeprom_error:
   3.417  	kfree(eeprom_buff);
   3.418 +	return ret_val;
   3.419 +}
   3.420 +#endif	/* ETHTOOL_SEEPROM */
   3.421 +
   3.422 +#ifdef	ETHTOOL_TEST
   3.423 +#define REG_PATTERN_TEST(R, M, W)                                              \
   3.424 +{                                                                              \
   3.425 +	uint32_t pat, value;                                                   \
   3.426 +	uint32_t test[] =                                                      \
   3.427 +		{0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};              \
   3.428 +	for(pat = 0; pat < sizeof(test)/sizeof(test[0]); pat++) {              \
   3.429 +		E1000_WRITE_REG(&adapter->hw, R, (test[pat] & W));             \
   3.430 +		value = E1000_READ_REG(&adapter->hw, R);                       \
   3.431 +		if(value != (test[pat] & W & M)) {                             \
   3.432 +			*data = (adapter->hw.mac_type < e1000_82543) ?         \
   3.433 +				E1000_82542_##R : E1000_##R;                   \
   3.434 +			return 1;                                              \
   3.435 +		}                                                              \
   3.436 +	}                                                                      \
   3.437 +}
   3.438 +
   3.439 +#define REG_SET_AND_CHECK(R, M, W)                                             \
   3.440 +{                                                                              \
   3.441 +	uint32_t value;                                                        \
   3.442 +	E1000_WRITE_REG(&adapter->hw, R, W & M);                               \
   3.443 +	value = E1000_READ_REG(&adapter->hw, R);                               \
   3.444 +	if ((W & M) != (value & M)) {                                          \
   3.445 +		*data = (adapter->hw.mac_type < e1000_82543) ?                 \
   3.446 +			E1000_82542_##R : E1000_##R;                           \
   3.447 +		return 1;                                                      \
   3.448 +	}                                                                      \
   3.449 +}
   3.450 +
   3.451 +static int
   3.452 +e1000_reg_test(struct e1000_adapter *adapter, uint64_t *data)
   3.453 +{
   3.454 +	uint32_t value;
   3.455 +	uint32_t i;
   3.456 +
   3.457 +	/* The status register is Read Only, so a write should fail.
   3.458 +	 * Some bits that get toggled are ignored.
   3.459 +	 */
   3.460 +	value = (E1000_READ_REG(&adapter->hw, STATUS) & (0xFFFFF833));
   3.461 +	E1000_WRITE_REG(&adapter->hw, STATUS, (0xFFFFFFFF));
   3.462 +	if(value != (E1000_READ_REG(&adapter->hw, STATUS) & (0xFFFFF833))) {
   3.463 +		*data = 1;
   3.464 +		return 1;
   3.465 +	}
   3.466 +
   3.467 +	REG_PATTERN_TEST(FCAL, 0xFFFFFFFF, 0xFFFFFFFF);
   3.468 +	REG_PATTERN_TEST(FCAH, 0x0000FFFF, 0xFFFFFFFF);
   3.469 +	REG_PATTERN_TEST(FCT, 0x0000FFFF, 0xFFFFFFFF);
   3.470 +	REG_PATTERN_TEST(VET, 0x0000FFFF, 0xFFFFFFFF);
   3.471 +	REG_PATTERN_TEST(RDTR, 0x0000FFFF, 0xFFFFFFFF);
   3.472 +	REG_PATTERN_TEST(RDBAH, 0xFFFFFFFF, 0xFFFFFFFF);
   3.473 +	REG_PATTERN_TEST(RDLEN, 0x000FFF80, 0x000FFFFF);
   3.474 +	REG_PATTERN_TEST(RDH, 0x0000FFFF, 0x0000FFFF);
   3.475 +	REG_PATTERN_TEST(RDT, 0x0000FFFF, 0x0000FFFF);
   3.476 +	REG_PATTERN_TEST(FCRTH, 0x0000FFF8, 0x0000FFF8);
   3.477 +	REG_PATTERN_TEST(FCTTV, 0x0000FFFF, 0x0000FFFF);
   3.478 +	REG_PATTERN_TEST(TIPG, 0x3FFFFFFF, 0x3FFFFFFF);
   3.479 +	REG_PATTERN_TEST(TDBAH, 0xFFFFFFFF, 0xFFFFFFFF);
   3.480 +	REG_PATTERN_TEST(TDLEN, 0x000FFF80, 0x000FFFFF);
   3.481 +
   3.482 +	REG_SET_AND_CHECK(RCTL, 0xFFFFFFFF, 0x00000000);
   3.483 +	REG_SET_AND_CHECK(RCTL, 0x06DFB3FE, 0x003FFFFB);
   3.484 +	REG_SET_AND_CHECK(TCTL, 0xFFFFFFFF, 0x00000000);
   3.485 +
   3.486 +	if(adapter->hw.mac_type >= e1000_82543) {
   3.487 +
   3.488 +		REG_SET_AND_CHECK(RCTL, 0x06DFB3FE, 0xFFFFFFFF);
   3.489 +		REG_PATTERN_TEST(RDBAL, 0xFFFFFFF0, 0xFFFFFFFF);
   3.490 +		REG_PATTERN_TEST(TXCW, 0xC000FFFF, 0x0000FFFF);
   3.491 +		REG_PATTERN_TEST(TDBAL, 0xFFFFFFF0, 0xFFFFFFFF);
   3.492 +		REG_PATTERN_TEST(TIDV, 0x0000FFFF, 0x0000FFFF);
   3.493 +
   3.494 +		for(i = 0; i < E1000_RAR_ENTRIES; i++) {
   3.495 +			REG_PATTERN_TEST(RA + ((i << 1) << 2), 0xFFFFFFFF,
   3.496 +					 0xFFFFFFFF);
   3.497 +			REG_PATTERN_TEST(RA + (((i << 1) + 1) << 2), 0x8003FFFF,
   3.498 +					 0xFFFFFFFF);
   3.499 +		}
   3.500 +
   3.501 +	} else {
   3.502 +
   3.503 +		REG_SET_AND_CHECK(RCTL, 0xFFFFFFFF, 0x01FFFFFF);
   3.504 +		REG_PATTERN_TEST(RDBAL, 0xFFFFF000, 0xFFFFFFFF);
   3.505 +		REG_PATTERN_TEST(TXCW, 0x0000FFFF, 0x0000FFFF);
   3.506 +		REG_PATTERN_TEST(TDBAL, 0xFFFFF000, 0xFFFFFFFF);
   3.507 +
   3.508 +	}
   3.509 +
   3.510 +	for(i = 0; i < E1000_MC_TBL_SIZE; i++)
   3.511 +		REG_PATTERN_TEST(MTA + (i << 2), 0xFFFFFFFF, 0xFFFFFFFF);
   3.512  
   3.513  	return 0;
   3.514  }
   3.515  
   3.516 +static int
   3.517 +e1000_eeprom_test(struct e1000_adapter *adapter, uint64_t *data)
   3.518 +{
   3.519 +	uint16_t temp;
   3.520 +	uint16_t checksum = 0;
   3.521 +	uint16_t i;
   3.522 +
   3.523 +	*data = 0;
   3.524 +	/* Read and add up the contents of the EEPROM */
   3.525 +	for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
   3.526 +		if((e1000_read_eeprom(&adapter->hw, i, 1, &temp)) < 0) {
   3.527 +			*data = 1;
   3.528 +			break;
   3.529 +		}
   3.530 +		checksum += temp;
   3.531 +	}
   3.532 +
   3.533 +	/* If Checksum is not Correct return error else test passed */
   3.534 +	if((checksum != (uint16_t) EEPROM_SUM) && !(*data))
   3.535 +		*data = 2;
   3.536 +
   3.537 +	return *data;
   3.538 +}
   3.539 +
   3.540 +static irqreturn_t
   3.541 +e1000_test_intr(int irq,
   3.542 +		void *data,
   3.543 +		struct pt_regs *regs)
   3.544 +{
   3.545 +	struct net_device *netdev = (struct net_device *) data;
   3.546 +	struct e1000_adapter *adapter = netdev->priv;
   3.547 +
   3.548 +	adapter->test_icr |= E1000_READ_REG(&adapter->hw, ICR);
   3.549 +
   3.550 +	return IRQ_HANDLED;
   3.551 +}
   3.552 +
   3.553 +static int
   3.554 +e1000_intr_test(struct e1000_adapter *adapter, uint64_t *data)
   3.555 +{
   3.556 +	struct net_device *netdev = adapter->netdev;
   3.557 +	uint32_t icr, mask, i=0;
   3.558 +
   3.559 +	*data = 0;
   3.560 +
   3.561 +	/* Hook up test interrupt handler just for this test */
   3.562 +	if(request_irq
   3.563 +	   (netdev->irq, &e1000_test_intr, SA_SHIRQ, netdev->name, netdev)) {
   3.564 +		*data = 1;
   3.565 +		return -1;
   3.566 +	}
   3.567 +
   3.568 +	/* Disable all the interrupts */
   3.569 +	E1000_WRITE_REG(&adapter->hw, IMC, 0xFFFFFFFF);
   3.570 +	msec_delay(10);
   3.571 +
   3.572 +	/* Interrupts are disabled, so read interrupt cause
   3.573 +	 * register (icr) twice to verify that there are no interrupts
   3.574 +	 * pending.  icr is clear on read.
   3.575 +	 */
   3.576 +	icr = E1000_READ_REG(&adapter->hw, ICR);
   3.577 +	icr = E1000_READ_REG(&adapter->hw, ICR);
   3.578 +
   3.579 +	if(icr != 0) {
   3.580 +		/* if icr is non-zero, there is no point
   3.581 +		 * running other interrupt tests.
   3.582 +		 */
   3.583 +		*data = 2;
   3.584 +		i = 10;
   3.585 +	}
   3.586 +
   3.587 +	/* Test each interrupt */
   3.588 +	for(; i < 10; i++) {
   3.589 +
   3.590 +		/* Interrupt to test */
   3.591 +		mask = 1 << i;
   3.592 +
   3.593 +		/* Disable the interrupt to be reported in
   3.594 +		 * the cause register and then force the same
   3.595 +		 * interrupt and see if one gets posted.  If
   3.596 +		 * an interrupt was posted to the bus, the
   3.597 +		 * test failed.
   3.598 +		 */
   3.599 +		adapter->test_icr = 0;
   3.600 +		E1000_WRITE_REG(&adapter->hw, IMC, mask);
   3.601 +		E1000_WRITE_REG(&adapter->hw, ICS, mask);
   3.602 +		msec_delay(10);
   3.603 +
   3.604 +		if(adapter->test_icr & mask) {
   3.605 +			*data = 3;
   3.606 +			break;
   3.607 +		}
   3.608 +
   3.609 +		/* Enable the interrupt to be reported in
   3.610 +		 * the cause register and then force the same
   3.611 +		 * interrupt and see if one gets posted.  If
   3.612 +		 * an interrupt was not posted to the bus, the
   3.613 +		 * test failed.
   3.614 +		 */
   3.615 +		adapter->test_icr = 0;
   3.616 +		E1000_WRITE_REG(&adapter->hw, IMS, mask);
   3.617 +		E1000_WRITE_REG(&adapter->hw, ICS, mask);
   3.618 +		msec_delay(10);
   3.619 +
   3.620 +		if(!(adapter->test_icr & mask)) {
   3.621 +			*data = 4;
   3.622 +			break;
   3.623 +		}
   3.624 +
   3.625 +		/* Disable the other interrupts to be reported in
   3.626 +		 * the cause register and then force the other
   3.627 +		 * interrupts and see if any get posted.  If
   3.628 +		 * an interrupt was posted to the bus, the
   3.629 +		 * test failed.
   3.630 +		 */
   3.631 +		adapter->test_icr = 0;
   3.632 +		E1000_WRITE_REG(&adapter->hw, IMC, ~mask);
   3.633 +		E1000_WRITE_REG(&adapter->hw, ICS, ~mask);
   3.634 +		msec_delay(10);
   3.635 +
   3.636 +		if(adapter->test_icr) {
   3.637 +			*data = 5;
   3.638 +			break;
   3.639 +		}
   3.640 +	}
   3.641 +
   3.642 +	/* Disable all the interrupts */
   3.643 +	E1000_WRITE_REG(&adapter->hw, IMC, 0xFFFFFFFF);
   3.644 +	msec_delay(10);
   3.645 +
   3.646 +	/* Unhook test interrupt handler */
   3.647 +	free_irq(netdev->irq, netdev);
   3.648 +
   3.649 +	return *data;
   3.650 +}
   3.651 +
   3.652 +static void
   3.653 +e1000_free_desc_rings(struct e1000_adapter *adapter)
   3.654 +{
   3.655 +	struct e1000_desc_ring *txdr = &adapter->test_tx_ring;
   3.656 +	struct e1000_desc_ring *rxdr = &adapter->test_rx_ring;
   3.657 +	struct pci_dev *pdev = adapter->pdev;
   3.658 +	int i;
   3.659 +
   3.660 +	if(txdr->desc && txdr->buffer_info) {
   3.661 +		for(i = 0; i < txdr->count; i++) {
   3.662 +			if(txdr->buffer_info[i].dma)
   3.663 +				pci_unmap_single(pdev, txdr->buffer_info[i].dma,
   3.664 +						 txdr->buffer_info[i].length,
   3.665 +						 PCI_DMA_TODEVICE);
   3.666 +			if(txdr->buffer_info[i].skb)
   3.667 +				dev_kfree_skb(txdr->buffer_info[i].skb);
   3.668 +		}
   3.669 +	}
   3.670 +
   3.671 +	if(rxdr->desc && rxdr->buffer_info) {
   3.672 +		for(i = 0; i < rxdr->count; i++) {
   3.673 +			if(rxdr->buffer_info[i].dma)
   3.674 +				pci_unmap_single(pdev, rxdr->buffer_info[i].dma,
   3.675 +						 rxdr->buffer_info[i].length,
   3.676 +						 PCI_DMA_FROMDEVICE);
   3.677 +			if(rxdr->buffer_info[i].skb)
   3.678 +				dev_kfree_skb(rxdr->buffer_info[i].skb);
   3.679 +		}
   3.680 +	}
   3.681 +
   3.682 +	if(txdr->desc)
   3.683 +		pci_free_consistent(pdev, txdr->size, txdr->desc, txdr->dma);
   3.684 +	if(rxdr->desc)
   3.685 +		pci_free_consistent(pdev, rxdr->size, rxdr->desc, rxdr->dma);
   3.686 +
   3.687 +	if(txdr->buffer_info)
   3.688 +		kfree(txdr->buffer_info);
   3.689 +	if(rxdr->buffer_info)
   3.690 +		kfree(rxdr->buffer_info);
   3.691 +
   3.692 +	return;
   3.693 +}
   3.694 +
   3.695 +static int
   3.696 +e1000_setup_desc_rings(struct e1000_adapter *adapter)
   3.697 +{
   3.698 +	struct e1000_desc_ring *txdr = &adapter->test_tx_ring;
   3.699 +	struct e1000_desc_ring *rxdr = &adapter->test_rx_ring;
   3.700 +	struct pci_dev *pdev = adapter->pdev;
   3.701 +	uint32_t rctl;
   3.702 +	int size, i, ret_val;
   3.703 +
   3.704 +	/* Setup Tx descriptor ring and Tx buffers */
   3.705 +
   3.706 +	txdr->count = 80;
   3.707 +
   3.708 +	size = txdr->count * sizeof(struct e1000_buffer);
   3.709 +	if(!(txdr->buffer_info = kmalloc(size, GFP_KERNEL))) {
   3.710 +		ret_val = 1;
   3.711 +		goto err_nomem;
   3.712 +	}
   3.713 +	memset(txdr->buffer_info, 0, size);
   3.714 +
   3.715 +	txdr->size = txdr->count * sizeof(struct e1000_tx_desc);
   3.716 +	E1000_ROUNDUP(txdr->size, 4096);
   3.717 +	if(!(txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma))) {
   3.718 +		ret_val = 2;
   3.719 +		goto err_nomem;
   3.720 +	}
   3.721 +	memset(txdr->desc, 0, txdr->size);
   3.722 +	txdr->next_to_use = txdr->next_to_clean = 0;
   3.723 +
   3.724 +	E1000_WRITE_REG(&adapter->hw, TDBAL,
   3.725 +			((uint64_t) txdr->dma & 0x00000000FFFFFFFF));
   3.726 +	E1000_WRITE_REG(&adapter->hw, TDBAH, ((uint64_t) txdr->dma >> 32));
   3.727 +	E1000_WRITE_REG(&adapter->hw, TDLEN,
   3.728 +			txdr->count * sizeof(struct e1000_tx_desc));
   3.729 +	E1000_WRITE_REG(&adapter->hw, TDH, 0);
   3.730 +	E1000_WRITE_REG(&adapter->hw, TDT, 0);
   3.731 +	E1000_WRITE_REG(&adapter->hw, TCTL,
   3.732 +			E1000_TCTL_PSP | E1000_TCTL_EN |
   3.733 +			E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT |
   3.734 +			E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT);
   3.735 +
   3.736 +	for(i = 0; i < txdr->count; i++) {
   3.737 +		struct e1000_tx_desc *tx_desc = E1000_TX_DESC(*txdr, i);
   3.738 +		struct sk_buff *skb;
   3.739 +		unsigned int size = 1024;
   3.740 +
   3.741 +		if(!(skb = alloc_skb(size, GFP_KERNEL))) {
   3.742 +			ret_val = 3;
   3.743 +			goto err_nomem;
   3.744 +		}
   3.745 +		skb_put(skb, size);
   3.746 +		txdr->buffer_info[i].skb = skb;
   3.747 +		txdr->buffer_info[i].length = skb->len;
   3.748 +		txdr->buffer_info[i].dma =
   3.749 +			pci_map_single(pdev, skb->data, skb->len,
   3.750 +				       PCI_DMA_TODEVICE);
   3.751 +		tx_desc->buffer_addr = cpu_to_le64(txdr->buffer_info[i].dma);
   3.752 +		tx_desc->lower.data = cpu_to_le32(skb->len);
   3.753 +		tx_desc->lower.data |= E1000_TXD_CMD_EOP;
   3.754 +		tx_desc->lower.data |= E1000_TXD_CMD_IFCS;
   3.755 +		tx_desc->lower.data |= E1000_TXD_CMD_RPS;
   3.756 +		tx_desc->upper.data = 0;
   3.757 +	}
   3.758 +
   3.759 +	/* Setup Rx descriptor ring and Rx buffers */
   3.760 +
   3.761 +	rxdr->count = 80;
   3.762 +
   3.763 +	size = rxdr->count * sizeof(struct e1000_buffer);
   3.764 +	if(!(rxdr->buffer_info = kmalloc(size, GFP_KERNEL))) {
   3.765 +		ret_val = 4;
   3.766 +		goto err_nomem;
   3.767 +	}
   3.768 +	memset(rxdr->buffer_info, 0, size);
   3.769 +
   3.770 +	rxdr->size = rxdr->count * sizeof(struct e1000_rx_desc);
   3.771 +	if(!(rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma))) {
   3.772 +		ret_val = 5;
   3.773 +		goto err_nomem;
   3.774 +	}
   3.775 +	memset(rxdr->desc, 0, rxdr->size);
   3.776 +	rxdr->next_to_use = rxdr->next_to_clean = 0;
   3.777 +
   3.778 +	rctl = E1000_READ_REG(&adapter->hw, RCTL);
   3.779 +	E1000_WRITE_REG(&adapter->hw, RCTL, rctl & ~E1000_RCTL_EN);
   3.780 +	E1000_WRITE_REG(&adapter->hw, RDBAL,
   3.781 +			((uint64_t) rxdr->dma & 0xFFFFFFFF));
   3.782 +	E1000_WRITE_REG(&adapter->hw, RDBAH, ((uint64_t) rxdr->dma >> 32));
   3.783 +	E1000_WRITE_REG(&adapter->hw, RDLEN, rxdr->size);
   3.784 +	E1000_WRITE_REG(&adapter->hw, RDH, 0);
   3.785 +	E1000_WRITE_REG(&adapter->hw, RDT, 0);
   3.786 +	rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 |
   3.787 +		E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
   3.788 +		(adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
   3.789 +	E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
   3.790 +
   3.791 +	for(i = 0; i < rxdr->count; i++) {
   3.792 +		struct e1000_rx_desc *rx_desc = E1000_RX_DESC(*rxdr, i);
   3.793 +		struct sk_buff *skb;
   3.794 +
   3.795 +		if(!(skb = alloc_skb(E1000_RXBUFFER_2048 + 2, GFP_KERNEL))) {
   3.796 +			ret_val = 6;
   3.797 +			goto err_nomem;
   3.798 +		}
   3.799 +		skb_reserve(skb, 2);
   3.800 +		rxdr->buffer_info[i].skb = skb;
   3.801 +		rxdr->buffer_info[i].length = E1000_RXBUFFER_2048;
   3.802 +		rxdr->buffer_info[i].dma =
   3.803 +			pci_map_single(pdev, skb->data, E1000_RXBUFFER_2048,
   3.804 +				       PCI_DMA_FROMDEVICE);
   3.805 +		rx_desc->buffer_addr = cpu_to_le64(rxdr->buffer_info[i].dma);
   3.806 +		memset(skb->data, 0x00, skb->len);
   3.807 +	}
   3.808 +
   3.809 +	return 0;
   3.810 +
   3.811 +      err_nomem:
   3.812 +	e1000_free_desc_rings(adapter);
   3.813 +	return ret_val;
   3.814 +}
   3.815 +
   3.816 +static void
   3.817 +e1000_phy_disable_receiver(struct e1000_adapter *adapter)
   3.818 +{
   3.819 +	/* Write out to PHY registers 29 and 30 to disable the Receiver. */
   3.820 +	e1000_write_phy_reg(&adapter->hw, 29, 0x001F);
   3.821 +	e1000_write_phy_reg(&adapter->hw, 30, 0x8FFC);
   3.822 +	e1000_write_phy_reg(&adapter->hw, 29, 0x001A);
   3.823 +	e1000_write_phy_reg(&adapter->hw, 30, 0x8FF0);
   3.824 +
   3.825 +	return;
   3.826 +}
   3.827 +
   3.828 +static void
   3.829 +e1000_phy_reset_clk_and_crs(struct e1000_adapter *adapter)
   3.830 +{
   3.831 +	uint16_t phy_reg;
   3.832 +
   3.833 +	/* Because we reset the PHY above, we need to re-force TX_CLK in the
   3.834 +	 * Extended PHY Specific Control Register to 25MHz clock.  This
   3.835 +	 * value defaults back to a 2.5MHz clock when the PHY is reset.
   3.836 +	 */
   3.837 +	e1000_read_phy_reg(&adapter->hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_reg);
   3.838 +	phy_reg |= M88E1000_EPSCR_TX_CLK_25;
   3.839 +	e1000_write_phy_reg(&adapter->hw,
   3.840 +		M88E1000_EXT_PHY_SPEC_CTRL, phy_reg);
   3.841 +
   3.842 +	/* In addition, because of the s/w reset above, we need to enable
   3.843 +	 * CRS on TX.  This must be set for both full and half duplex
   3.844 +	 * operation.
   3.845 +	 */
   3.846 +	e1000_read_phy_reg(&adapter->hw, M88E1000_PHY_SPEC_CTRL, &phy_reg);
   3.847 +	phy_reg |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
   3.848 +	e1000_write_phy_reg(&adapter->hw,
   3.849 +		M88E1000_PHY_SPEC_CTRL, phy_reg);
   3.850 +}
   3.851 +
   3.852 +static int
   3.853 +e1000_nonintegrated_phy_loopback(struct e1000_adapter *adapter)
   3.854 +{
   3.855 +	uint32_t ctrl_reg;
   3.856 +	uint16_t phy_reg;
   3.857 +
   3.858 +	/* Setup the Device Control Register for PHY loopback test. */
   3.859 +
   3.860 +	ctrl_reg = E1000_READ_REG(&adapter->hw, CTRL);
   3.861 +	ctrl_reg |= (E1000_CTRL_ILOS |		/* Invert Loss-Of-Signal */
   3.862 +		     E1000_CTRL_FRCSPD |	/* Set the Force Speed Bit */
   3.863 +		     E1000_CTRL_FRCDPX |	/* Set the Force Duplex Bit */
   3.864 +		     E1000_CTRL_SPD_1000 |	/* Force Speed to 1000 */
   3.865 +		     E1000_CTRL_FD);		/* Force Duplex to FULL */
   3.866 +
   3.867 +	E1000_WRITE_REG(&adapter->hw, CTRL, ctrl_reg);
   3.868 +
   3.869 +	/* Read the PHY Specific Control Register (0x10) */
   3.870 +	e1000_read_phy_reg(&adapter->hw, M88E1000_PHY_SPEC_CTRL, &phy_reg);
   3.871 +
   3.872 +	/* Clear Auto-Crossover bits in PHY Specific Control Register
   3.873 +	 * (bits 6:5).
   3.874 +	 */
   3.875 +	phy_reg &= ~M88E1000_PSCR_AUTO_X_MODE;
   3.876 +	e1000_write_phy_reg(&adapter->hw, M88E1000_PHY_SPEC_CTRL, phy_reg);
   3.877 +
   3.878 +	/* Perform software reset on the PHY */
   3.879 +	e1000_phy_reset(&adapter->hw);
   3.880 +
   3.881 +	/* Have to setup TX_CLK and TX_CRS after software reset */
   3.882 +	e1000_phy_reset_clk_and_crs(adapter);
   3.883 +
   3.884 +	e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x8100);
   3.885 +
   3.886 +	/* Wait for reset to complete. */
   3.887 +	usec_delay(500);
   3.888 +
   3.889 +	/* Have to setup TX_CLK and TX_CRS after software reset */
   3.890 +	e1000_phy_reset_clk_and_crs(adapter);
   3.891 +
   3.892 +	/* Write out to PHY registers 29 and 30 to disable the Receiver. */
   3.893 +	e1000_phy_disable_receiver(adapter);
   3.894 +
   3.895 +	/* Set the loopback bit in the PHY control register. */
   3.896 +	e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_reg);
   3.897 +	phy_reg |= MII_CR_LOOPBACK;
   3.898 +	e1000_write_phy_reg(&adapter->hw, PHY_CTRL, phy_reg);
   3.899 +
   3.900 +	/* Setup TX_CLK and TX_CRS one more time. */
   3.901 +	e1000_phy_reset_clk_and_crs(adapter);
   3.902 +
   3.903 +	/* Check Phy Configuration */
   3.904 +	e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_reg);
   3.905 +	if(phy_reg != 0x4100)
   3.906 +		 return 9;
   3.907 +
   3.908 +	e1000_read_phy_reg(&adapter->hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_reg);
   3.909 +	if(phy_reg != 0x0070)
   3.910 +		return 10;
   3.911 +
   3.912 +	e1000_read_phy_reg(&adapter->hw, 29, &phy_reg);
   3.913 +	if(phy_reg != 0x001A)
   3.914 +		return 11;
   3.915 +
   3.916 +	return 0;
   3.917 +}
   3.918 +
   3.919 +static int
   3.920 +e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
   3.921 +{
   3.922 +	uint32_t ctrl_reg = 0;
   3.923 +	uint32_t stat_reg = 0;
   3.924 +
   3.925 +	adapter->hw.autoneg = FALSE;
   3.926 +
   3.927 +	if(adapter->hw.phy_type == e1000_phy_m88) {
   3.928 +		/* Auto-MDI/MDIX Off */
   3.929 +		e1000_write_phy_reg(&adapter->hw,
   3.930 +				    M88E1000_PHY_SPEC_CTRL, 0x0808);
   3.931 +		/* reset to update Auto-MDI/MDIX */
   3.932 +		e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x9140);
   3.933 +		/* autoneg off */
   3.934 +		e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x8140);
   3.935 +	}
   3.936 +	/* force 1000, set loopback */
   3.937 +	e1000_write_phy_reg(&adapter->hw, PHY_CTRL, 0x4140);
   3.938 +
   3.939 +	/* Now set up the MAC to the same speed/duplex as the PHY. */
   3.940 +	ctrl_reg = E1000_READ_REG(&adapter->hw, CTRL);
   3.941 +	ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
   3.942 +	ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
   3.943 +		     E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
   3.944 +		     E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
   3.945 +		     E1000_CTRL_FD);	 /* Force Duplex to FULL */
   3.946 +
   3.947 +	if(adapter->hw.media_type == e1000_media_type_copper &&
   3.948 +	   adapter->hw.phy_type == e1000_phy_m88) {
   3.949 +		ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
   3.950 +	} else {
   3.951 +		/* Set the ILOS bit on the fiber Nic is half
   3.952 +		 * duplex link is detected. */
   3.953 +		stat_reg = E1000_READ_REG(&adapter->hw, STATUS);
   3.954 +		if((stat_reg & E1000_STATUS_FD) == 0)
   3.955 +			ctrl_reg |= (E1000_CTRL_ILOS | E1000_CTRL_SLU);
   3.956 +	}
   3.957 +
   3.958 +	E1000_WRITE_REG(&adapter->hw, CTRL, ctrl_reg);
   3.959 +
   3.960 +	/* Disable the receiver on the PHY so when a cable is plugged in, the
   3.961 +	 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
   3.962 +	 */
   3.963 +	if(adapter->hw.phy_type == e1000_phy_m88)
   3.964 +		e1000_phy_disable_receiver(adapter);
   3.965 +
   3.966 +	usec_delay(500);
   3.967 +
   3.968 +	return 0;
   3.969 +}
   3.970 +
   3.971 +static int
   3.972 +e1000_set_phy_loopback(struct e1000_adapter *adapter)
   3.973 +{
   3.974 +	uint16_t phy_reg = 0;
   3.975 +	uint16_t count = 0;
   3.976 +
   3.977 +	switch (adapter->hw.mac_type) {
   3.978 +	case e1000_82543:
   3.979 +		if(adapter->hw.media_type == e1000_media_type_copper) {
   3.980 +			/* Attempt to setup Loopback mode on Non-integrated PHY.
   3.981 +			 * Some PHY registers get corrupted at random, so
   3.982 +			 * attempt this 10 times.
   3.983 +			 */
   3.984 +			while(e1000_nonintegrated_phy_loopback(adapter) &&
   3.985 +			      count++ < 10);
   3.986 +			if(count < 11)
   3.987 +				return 0;
   3.988 +		}
   3.989 +		break;
   3.990 +
   3.991 +	case e1000_82544:
   3.992 +	case e1000_82540:
   3.993 +	case e1000_82545:
   3.994 +	case e1000_82545_rev_3:
   3.995 +	case e1000_82546:
   3.996 +	case e1000_82546_rev_3:
   3.997 +	case e1000_82541:
   3.998 +	case e1000_82541_rev_2:
   3.999 +	case e1000_82547:
  3.1000 +	case e1000_82547_rev_2:
  3.1001 +		return e1000_integrated_phy_loopback(adapter);
  3.1002 +		break;
  3.1003 +
  3.1004 +	default:
  3.1005 +		/* Default PHY loopback work is to read the MII
  3.1006 +		 * control register and assert bit 14 (loopback mode).
  3.1007 +		 */
  3.1008 +		e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_reg);
  3.1009 +		phy_reg |= MII_CR_LOOPBACK;
  3.1010 +		e1000_write_phy_reg(&adapter->hw, PHY_CTRL, phy_reg);
  3.1011 +		return 0;
  3.1012 +		break;
  3.1013 +	}
  3.1014 +
  3.1015 +	return 8;
  3.1016 +}
  3.1017 +
  3.1018 +static int
  3.1019 +e1000_setup_loopback_test(struct e1000_adapter *adapter)
  3.1020 +{
  3.1021 +	uint32_t rctl;
  3.1022 +
  3.1023 +	if(adapter->hw.media_type == e1000_media_type_fiber ||
  3.1024 +	   adapter->hw.media_type == e1000_media_type_internal_serdes) {
  3.1025 +		if(adapter->hw.mac_type == e1000_82545 ||
  3.1026 +		   adapter->hw.mac_type == e1000_82546 ||
  3.1027 +		   adapter->hw.mac_type == e1000_82545_rev_3 ||
  3.1028 +		   adapter->hw.mac_type == e1000_82546_rev_3)
  3.1029 +			return e1000_set_phy_loopback(adapter);
  3.1030 +		else {
  3.1031 +			rctl = E1000_READ_REG(&adapter->hw, RCTL);
  3.1032 +			rctl |= E1000_RCTL_LBM_TCVR;
  3.1033 +			E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
  3.1034 +			return 0;
  3.1035 +		}
  3.1036 +	} else if(adapter->hw.media_type == e1000_media_type_copper)
  3.1037 +		return e1000_set_phy_loopback(adapter);
  3.1038 +
  3.1039 +	return 7;
  3.1040 +}
  3.1041 +
  3.1042 +static void
  3.1043 +e1000_loopback_cleanup(struct e1000_adapter *adapter)
  3.1044 +{
  3.1045 +	uint32_t rctl;
  3.1046 +	uint16_t phy_reg;
  3.1047 +
  3.1048 +	rctl = E1000_READ_REG(&adapter->hw, RCTL);
  3.1049 +	rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
  3.1050 +	E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
  3.1051 +
  3.1052 +	if(adapter->hw.media_type == e1000_media_type_copper ||
  3.1053 +	   ((adapter->hw.media_type == e1000_media_type_fiber ||
  3.1054 +	     adapter->hw.media_type == e1000_media_type_internal_serdes) &&
  3.1055 +	    (adapter->hw.mac_type == e1000_82545 ||
  3.1056 +	     adapter->hw.mac_type == e1000_82546 ||
  3.1057 +	     adapter->hw.mac_type == e1000_82545_rev_3 ||
  3.1058 +	     adapter->hw.mac_type == e1000_82546_rev_3))) {
  3.1059 +		adapter->hw.autoneg = TRUE;
  3.1060 +		e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_reg);
  3.1061 +		if(phy_reg & MII_CR_LOOPBACK) {
  3.1062 +			phy_reg &= ~MII_CR_LOOPBACK;
  3.1063 +			e1000_write_phy_reg(&adapter->hw, PHY_CTRL, phy_reg);
  3.1064 +			e1000_phy_reset(&adapter->hw);
  3.1065 +		}
  3.1066 +	}
  3.1067 +}
  3.1068 +
  3.1069 +static void
  3.1070 +e1000_create_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
  3.1071 +{
  3.1072 +	memset(skb->data, 0xFF, frame_size);
  3.1073 +	frame_size = (frame_size % 2) ? (frame_size - 1) : frame_size;
  3.1074 +	memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
  3.1075 +	memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
  3.1076 +	memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
  3.1077 +}
  3.1078 +
  3.1079 +static int
  3.1080 +e1000_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
  3.1081 +{
  3.1082 +	frame_size = (frame_size % 2) ? (frame_size - 1) : frame_size;
  3.1083 +	if(*(skb->data + 3) == 0xFF) {
  3.1084 +		if((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
  3.1085 +		   (*(skb->data + frame_size / 2 + 12) == 0xAF)) {
  3.1086 +			return 0;
  3.1087 +		}
  3.1088 +	}
  3.1089 +	return 13;
  3.1090 +}
  3.1091 +
  3.1092 +static int
  3.1093 +e1000_run_loopback_test(struct e1000_adapter *adapter)
  3.1094 +{
  3.1095 +	struct e1000_desc_ring *txdr = &adapter->test_tx_ring;
  3.1096 +	struct e1000_desc_ring *rxdr = &adapter->test_rx_ring;
  3.1097 +	struct pci_dev *pdev = adapter->pdev;
  3.1098 +	int i;
  3.1099 +
  3.1100 +	E1000_WRITE_REG(&adapter->hw, RDT, rxdr->count - 1);
  3.1101 +
  3.1102 +	for(i = 0; i < 64; i++) {
  3.1103 +		e1000_create_lbtest_frame(txdr->buffer_info[i].skb, 1024);
  3.1104 +		pci_dma_sync_single(pdev, txdr->buffer_info[i].dma,
  3.1105 +				    txdr->buffer_info[i].length,
  3.1106 +				    PCI_DMA_TODEVICE);
  3.1107 +	}
  3.1108 +	E1000_WRITE_REG(&adapter->hw, TDT, i);
  3.1109 +
  3.1110 +	msec_delay(200);
  3.1111 +
  3.1112 +	pci_dma_sync_single(pdev, rxdr->buffer_info[0].dma,
  3.1113 +			    rxdr->buffer_info[0].length, PCI_DMA_FROMDEVICE);
  3.1114 +
  3.1115 +	return e1000_check_lbtest_frame(rxdr->buffer_info[0].skb, 1024);
  3.1116 +}
  3.1117 +
  3.1118 +static int
  3.1119 +e1000_loopback_test(struct e1000_adapter *adapter, uint64_t *data)
  3.1120 +{
  3.1121 +	if((*data = e1000_setup_desc_rings(adapter))) goto err_loopback;
  3.1122 +	if((*data = e1000_setup_loopback_test(adapter))) goto err_loopback;
  3.1123 +	*data = e1000_run_loopback_test(adapter);
  3.1124 +	e1000_loopback_cleanup(adapter);
  3.1125 +	e1000_free_desc_rings(adapter);
  3.1126 +err_loopback:
  3.1127 +	return *data;
  3.1128 +}
  3.1129 +
  3.1130 +static int
  3.1131 +e1000_link_test(struct e1000_adapter *adapter, uint64_t *data)
  3.1132 +{
  3.1133 +	*data = 0;
  3.1134 +	e1000_check_for_link(&adapter->hw);
  3.1135 +
  3.1136 +	if(!(E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU)) {
  3.1137 +		*data = 1;
  3.1138 +	}
  3.1139 +	return *data;
  3.1140 +}
  3.1141 +
  3.1142 +static int
  3.1143 +e1000_ethtool_test(struct e1000_adapter *adapter,
  3.1144 +		   struct ethtool_test *eth_test, uint64_t *data)
  3.1145 +{
  3.1146 +	boolean_t if_running = netif_running(adapter->netdev);
  3.1147 +
  3.1148 +	if(eth_test->flags == ETH_TEST_FL_OFFLINE) {
  3.1149 +		/* Offline tests */
  3.1150 +
  3.1151 +		/* Link test performed before hardware reset so autoneg doesn't
  3.1152 +		 * interfere with test result */
  3.1153 +		if(e1000_link_test(adapter, &data[4]))
  3.1154 +			eth_test->flags |= ETH_TEST_FL_FAILED;
  3.1155 +
  3.1156 +		if(if_running)
  3.1157 +			e1000_down(adapter);
  3.1158 +		else
  3.1159 +			e1000_reset(adapter);
  3.1160 +
  3.1161 +		if(e1000_reg_test(adapter, &data[0]))
  3.1162 +			eth_test->flags |= ETH_TEST_FL_FAILED;
  3.1163 +
  3.1164 +		e1000_reset(adapter);
  3.1165 +		if(e1000_eeprom_test(adapter, &data[1]))
  3.1166 +			eth_test->flags |= ETH_TEST_FL_FAILED;
  3.1167 +
  3.1168 +		e1000_reset(adapter);
  3.1169 +		if(e1000_intr_test(adapter, &data[2]))
  3.1170 +			eth_test->flags |= ETH_TEST_FL_FAILED;
  3.1171 +
  3.1172 +		e1000_reset(adapter);
  3.1173 +		if(e1000_loopback_test(adapter, &data[3]))
  3.1174 +			eth_test->flags |= ETH_TEST_FL_FAILED;
  3.1175 +
  3.1176 +		e1000_reset(adapter);
  3.1177 +		if(if_running)
  3.1178 +			e1000_up(adapter);
  3.1179 +	} else {
  3.1180 +		/* Online tests */
  3.1181 +		if(e1000_link_test(adapter, &data[4]))
  3.1182 +			eth_test->flags |= ETH_TEST_FL_FAILED;
  3.1183 +
  3.1184 +		/* Offline tests aren't run; pass by default */
  3.1185 +		data[0] = 0;
  3.1186 +		data[1] = 0;
  3.1187 +		data[2] = 0;
  3.1188 +		data[3] = 0;
  3.1189 +	}
  3.1190 +	return 0;
  3.1191 +}
  3.1192 +#endif	/* ETHTOOL_TEST */
  3.1193 +
  3.1194 +#ifdef	ETHTOOL_GWOL
  3.1195  static void
  3.1196  e1000_ethtool_gwol(struct e1000_adapter *adapter, struct ethtool_wolinfo *wol)
  3.1197  {
  3.1198 @@ -324,6 +1256,7 @@ e1000_ethtool_gwol(struct e1000_adapter 
  3.1199  		return;
  3.1200  
  3.1201  	case E1000_DEV_ID_82546EB_FIBER:
  3.1202 +	case E1000_DEV_ID_82546GB_FIBER:
  3.1203  		/* Wake events only supported on port A for dual fiber */
  3.1204  		if(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) {
  3.1205  			wol->supported = 0;
  3.1206 @@ -333,8 +1266,8 @@ e1000_ethtool_gwol(struct e1000_adapter 
  3.1207  		/* Fall Through */
  3.1208  
  3.1209  	default:
  3.1210 -		wol->supported = WAKE_UCAST | WAKE_MCAST
  3.1211 -			         | WAKE_BCAST | WAKE_MAGIC;
  3.1212 +		wol->supported = WAKE_UCAST | WAKE_MCAST |
  3.1213 +				 WAKE_BCAST | WAKE_MAGIC;
  3.1214  
  3.1215  		wol->wolopts = 0;
  3.1216  		if(adapter->wol & E1000_WUFC_EX)
  3.1217 @@ -348,7 +1281,9 @@ e1000_ethtool_gwol(struct e1000_adapter 
  3.1218  		return;
  3.1219  	}
  3.1220  }
  3.1221 +#endif	/* ETHTOOL_GWOL */
  3.1222  
  3.1223 +#ifdef	ETHTOOL_SWOL
  3.1224  static int
  3.1225  e1000_ethtool_swol(struct e1000_adapter *adapter, struct ethtool_wolinfo *wol)
  3.1226  {
  3.1227 @@ -362,13 +1297,14 @@ e1000_ethtool_swol(struct e1000_adapter 
  3.1228  		return wol->wolopts ? -EOPNOTSUPP : 0;
  3.1229  
  3.1230  	case E1000_DEV_ID_82546EB_FIBER:
  3.1231 +	case E1000_DEV_ID_82546GB_FIBER:
  3.1232  		/* Wake events only supported on port A for dual fiber */
  3.1233  		if(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
  3.1234  			return wol->wolopts ? -EOPNOTSUPP : 0;
  3.1235  		/* Fall Through */
  3.1236  
  3.1237  	default:
  3.1238 -		if(wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE | WAKE_PHY))
  3.1239 +		if(wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
  3.1240  			return -EOPNOTSUPP;
  3.1241  
  3.1242  		adapter->wol = 0;
  3.1243 @@ -385,7 +1321,9 @@ e1000_ethtool_swol(struct e1000_adapter 
  3.1244  
  3.1245  	return 0;
  3.1246  }
  3.1247 +#endif	/* ETHTOOL_SWOL */
  3.1248  
  3.1249 +#ifdef	ETHTOOL_PHYS_ID
  3.1250  
  3.1251  /* toggle LED 4 times per second = 2 "blinks" per second */
  3.1252  #define E1000_ID_INTERVAL	(HZ/4)
  3.1253 @@ -431,6 +1369,7 @@ e1000_ethtool_led_blink(struct e1000_ada
  3.1254  
  3.1255  	return 0;
  3.1256  }
  3.1257 +#endif	/* ETHTOOL_PHYS_ID */
  3.1258  
  3.1259  int
  3.1260  e1000_ethtool_ioctl(struct net_device *netdev, struct ifreq *ifr)
  3.1261 @@ -452,12 +1391,11 @@ e1000_ethtool_ioctl(struct net_device *n
  3.1262  	}
  3.1263  	case ETHTOOL_SSET: {
  3.1264  		struct ethtool_cmd ecmd;
  3.1265 -		if(!capable(CAP_NET_ADMIN))
  3.1266 -			return -EPERM;
  3.1267  		if(copy_from_user(&ecmd, addr, sizeof(ecmd)))
  3.1268  			return -EFAULT;
  3.1269  		return e1000_ethtool_sset(adapter, &ecmd);
  3.1270  	}
  3.1271 +#ifdef	ETHTOOL_GDRVINFO
  3.1272  	case ETHTOOL_GDRVINFO: {
  3.1273  		struct ethtool_drvinfo drvinfo = {ETHTOOL_GDRVINFO};
  3.1274  		e1000_ethtool_gdrvinfo(adapter, &drvinfo);
  3.1275 @@ -465,28 +1403,59 @@ e1000_ethtool_ioctl(struct net_device *n
  3.1276  			return -EFAULT;
  3.1277  		return 0;
  3.1278  	}
  3.1279 +#endif	/* ETHTOOL_GDRVINFO */
  3.1280 +#ifdef	ETHTOOL_GSTRINGS
  3.1281  	case ETHTOOL_GSTRINGS: {
  3.1282  		struct ethtool_gstrings gstrings = { ETHTOOL_GSTRINGS };
  3.1283  		char *strings = NULL;
  3.1284 +		int err = 0;
  3.1285  
  3.1286  		if(copy_from_user(&gstrings, addr, sizeof(gstrings)))
  3.1287  			return -EFAULT;
  3.1288  		switch(gstrings.string_set) {
  3.1289 -		case ETH_SS_STATS:
  3.1290 +#ifdef	ETHTOOL_TEST
  3.1291 +		case ETH_SS_TEST:
  3.1292 +			gstrings.len = E1000_TEST_LEN;
  3.1293 +			strings = kmalloc(E1000_TEST_LEN * ETH_GSTRING_LEN,
  3.1294 +					  GFP_KERNEL);
  3.1295 +			if(!strings)
  3.1296 +				return -ENOMEM;
  3.1297 +			memcpy(strings, e1000_gstrings_test, E1000_TEST_LEN *
  3.1298 +			       ETH_GSTRING_LEN);
  3.1299 +			break;
  3.1300 +#endif	/* ETHTOOL_TEST */
  3.1301 +#ifdef	ETHTOOL_GSTATS
  3.1302 +		case ETH_SS_STATS: {
  3.1303 +			int i;
  3.1304  			gstrings.len = E1000_STATS_LEN;
  3.1305 -			strings = *e1000_gstrings_stats;
  3.1306 +			strings = kmalloc(E1000_STATS_LEN * ETH_GSTRING_LEN,
  3.1307 +					  GFP_KERNEL);
  3.1308 +			if(!strings)
  3.1309 +				return -ENOMEM;
  3.1310 +			for(i=0; i < E1000_STATS_LEN; i++) {
  3.1311 +				memcpy(&strings[i * ETH_GSTRING_LEN],
  3.1312 +				       e1000_gstrings_stats[i].stat_string,
  3.1313 +				       ETH_GSTRING_LEN);
  3.1314 +			}
  3.1315  			break;
  3.1316 +		}
  3.1317 +#endif	/* ETHTOOL_GSTATS */
  3.1318  		default:
  3.1319  			return -EOPNOTSUPP;
  3.1320  		}
  3.1321  		if(copy_to_user(addr, &gstrings, sizeof(gstrings)))
  3.1322 -			return -EFAULT;
  3.1323 +			err = -EFAULT;
  3.1324  		addr += offsetof(struct ethtool_gstrings, data);
  3.1325 -		if(copy_to_user(addr, strings,
  3.1326 +		if(!err && copy_to_user(addr, strings,
  3.1327  		   gstrings.len * ETH_GSTRING_LEN))
  3.1328 -			return -EFAULT;
  3.1329 -		return 0;
  3.1330 +			err = -EFAULT;
  3.1331 +
  3.1332 +		kfree(strings);
  3.1333 +		return err;
  3.1334  	}
  3.1335 +#endif	/* ETHTOOL_GSTRINGS */
  3.1336 +#ifdef	ETHTOOL_GEEPROM  /* GREGS broken in earlier ethtool.h */
  3.1337 +#ifdef  ETHTOOL_GREGS
  3.1338  	case ETHTOOL_GREGS: {
  3.1339  		struct ethtool_regs regs = {ETHTOOL_GREGS};
  3.1340  		uint32_t regs_buff[E1000_REGS_LEN];
  3.1341 @@ -503,21 +1472,26 @@ e1000_ethtool_ioctl(struct net_device *n
  3.1342  
  3.1343  		return 0;
  3.1344  	}
  3.1345 +#endif  /* ETHTOOL_GREGS */
  3.1346 +#endif  /* ETHTOOL_GEEPROM */
  3.1347 +#ifdef	ETHTOOL_NWAY_RST
  3.1348  	case ETHTOOL_NWAY_RST: {
  3.1349 -		if(!capable(CAP_NET_ADMIN))
  3.1350 -			return -EPERM;
  3.1351  		if(netif_running(netdev)) {
  3.1352  			e1000_down(adapter);
  3.1353  			e1000_up(adapter);
  3.1354  		}
  3.1355  		return 0;
  3.1356  	}
  3.1357 +#endif	/* ETHTOOL_NWAY_RST */
  3.1358 +#ifdef	ETHTOOL_PHYS_ID
  3.1359  	case ETHTOOL_PHYS_ID: {
  3.1360  		struct ethtool_value id;
  3.1361  		if(copy_from_user(&id, addr, sizeof(id)))
  3.1362  			return -EFAULT;
  3.1363  		return e1000_ethtool_led_blink(adapter, &id);
  3.1364  	}
  3.1365 +#endif	/* ETHTOOL_PHYS_ID */
  3.1366 +#ifdef	ETHTOOL_GLINK
  3.1367  	case ETHTOOL_GLINK: {
  3.1368  		struct ethtool_value link = {ETHTOOL_GLINK};
  3.1369  		link.data = netif_carrier_ok(netdev);
  3.1370 @@ -525,6 +1499,8 @@ e1000_ethtool_ioctl(struct net_device *n
  3.1371  			return -EFAULT;
  3.1372  		return 0;
  3.1373  	}
  3.1374 +#endif	/* ETHTOOL_GLINK */
  3.1375 +#ifdef	ETHTOOL_GWOL
  3.1376  	case ETHTOOL_GWOL: {
  3.1377  		struct ethtool_wolinfo wol = {ETHTOOL_GWOL};
  3.1378  		e1000_ethtool_gwol(adapter, &wol);
  3.1379 @@ -532,31 +1508,30 @@ e1000_ethtool_ioctl(struct net_device *n
  3.1380  			return -EFAULT;
  3.1381  		return 0;
  3.1382  	}
  3.1383 +#endif	/* ETHTOOL_GWOL */
  3.1384 +#ifdef	ETHTOOL_SWOL
  3.1385  	case ETHTOOL_SWOL: {
  3.1386  		struct ethtool_wolinfo wol;
  3.1387 -		if(!capable(CAP_NET_ADMIN))
  3.1388 -			return -EPERM;
  3.1389  		if(copy_from_user(&wol, addr, sizeof(wol)) != 0)
  3.1390  			return -EFAULT;
  3.1391  		return e1000_ethtool_swol(adapter, &wol);
  3.1392  	}
  3.1393 +#endif	/* ETHTOOL_SWOL */
  3.1394 +#ifdef	ETHTOOL_GEEPROM
  3.1395  	case ETHTOOL_GEEPROM: {
  3.1396  		struct ethtool_eeprom eeprom = {ETHTOOL_GEEPROM};
  3.1397 +		struct e1000_hw *hw = &adapter->hw;
  3.1398  		uint16_t *eeprom_buff;
  3.1399  		void *ptr;
  3.1400 -		int max_len, err = 0;
  3.1401 +		int err = 0;
  3.1402  
  3.1403 -		max_len = e1000_eeprom_size(&adapter->hw);
  3.1404 -
  3.1405 -		eeprom_buff = kmalloc(max_len, GFP_KERNEL);
  3.1406 +		if(copy_from_user(&eeprom, addr, sizeof(eeprom)))
  3.1407 +			return -EFAULT;
  3.1408  
  3.1409 -		if(eeprom_buff == NULL)
  3.1410 -			return -ENOMEM;
  3.1411 +		eeprom_buff = kmalloc(hw->eeprom.word_size * 2, GFP_KERNEL);
  3.1412  
  3.1413 -		if(copy_from_user(&eeprom, addr, sizeof(eeprom))) {
  3.1414 -			err = -EFAULT;
  3.1415 -			goto err_geeprom_ioctl;
  3.1416 -		}
  3.1417 +		if(!eeprom_buff)
  3.1418 +			return -ENOMEM;
  3.1419  
  3.1420  		if((err = e1000_ethtool_geeprom(adapter, &eeprom,
  3.1421  						eeprom_buff)))
  3.1422 @@ -577,35 +1552,198 @@ err_geeprom_ioctl:
  3.1423  		kfree(eeprom_buff);
  3.1424  		return err;
  3.1425  	}
  3.1426 +#endif	/* ETHTOOL_GEEPROM */
  3.1427 +#ifdef	ETHTOOL_SEEPROM
  3.1428  	case ETHTOOL_SEEPROM: {
  3.1429  		struct ethtool_eeprom eeprom;
  3.1430  
  3.1431 -		if(!capable(CAP_NET_ADMIN))
  3.1432 -			return -EPERM;
  3.1433 -
  3.1434  		if(copy_from_user(&eeprom, addr, sizeof(eeprom)))
  3.1435  			return -EFAULT;
  3.1436  
  3.1437  		addr += offsetof(struct ethtool_eeprom, data);
  3.1438  		return e1000_ethtool_seeprom(adapter, &eeprom, addr);
  3.1439  	}
  3.1440 +#endif	/* ETHTOOL_SEEPROM */
  3.1441 +#ifdef	ETHTOOL_GPAUSEPARAM
  3.1442 +	case ETHTOOL_GPAUSEPARAM: {
  3.1443 +		struct ethtool_pauseparam epause = {ETHTOOL_GPAUSEPARAM};
  3.1444 +		e1000_ethtool_gpause(adapter, &epause);
  3.1445 +		if(copy_to_user(addr, &epause, sizeof(epause)))
  3.1446 +			return -EFAULT;
  3.1447 +		return 0;
  3.1448 +	}
  3.1449 +#endif	/* ETHTOOL_GPAUSEPARAM */
  3.1450 +#ifdef	ETHTOOL_SPAUSEPARAM
  3.1451 +	case ETHTOOL_SPAUSEPARAM: {
  3.1452 +		struct ethtool_pauseparam epause;
  3.1453 +		if(copy_from_user(&epause, addr, sizeof(epause)))
  3.1454 +			return -EFAULT;
  3.1455 +		return e1000_ethtool_spause(adapter, &epause);
  3.1456 +	}
  3.1457 +#endif	/* ETHTOOL_SPAUSEPARAM */
  3.1458 +#ifdef	ETHTOOL_GSTATS
  3.1459  	case ETHTOOL_GSTATS: {
  3.1460  		struct {
  3.1461 -			struct ethtool_stats cmd;
  3.1462 +			struct ethtool_stats eth_stats;
  3.1463  			uint64_t data[E1000_STATS_LEN];
  3.1464  		} stats = { {ETHTOOL_GSTATS, E1000_STATS_LEN} };
  3.1465  		int i;
  3.1466  
  3.1467  		for(i = 0; i < E1000_STATS_LEN; i++)
  3.1468 -			stats.data[i] =
  3.1469 -				((unsigned long *)&adapter->net_stats)[i];
  3.1470 +			stats.data[i] = (e1000_gstrings_stats[i].sizeof_stat ==
  3.1471 +					sizeof(uint64_t)) ?
  3.1472 +				*(uint64_t *)((char *)adapter +
  3.1473 +					e1000_gstrings_stats[i].stat_offset) :
  3.1474 +				*(uint32_t *)((char *)adapter +
  3.1475 +					e1000_gstrings_stats[i].stat_offset);
  3.1476  		if(copy_to_user(addr, &stats, sizeof(stats)))
  3.1477  			return -EFAULT;
  3.1478  		return 0;
  3.1479  	}
  3.1480 +#endif	/* ETHTOOL_GSTATS */
  3.1481 +#ifdef	ETHTOOL_TEST
  3.1482 +	case ETHTOOL_TEST: {
  3.1483 +		struct {
  3.1484 +			struct ethtool_test eth_test;
  3.1485 +			uint64_t data[E1000_TEST_LEN];
  3.1486 +		} test = { {ETHTOOL_TEST} };
  3.1487 +		int err;
  3.1488 +
  3.1489 +		if(copy_from_user(&test.eth_test, addr, sizeof(test.eth_test)))
  3.1490 +			return -EFAULT;
  3.1491 +
  3.1492 +		test.eth_test.len = E1000_TEST_LEN;
  3.1493 +
  3.1494 +		if((err = e1000_ethtool_test(adapter, &test.eth_test,
  3.1495 +					     test.data)))
  3.1496 +			return err;
  3.1497 +
  3.1498 +		if(copy_to_user(addr, &test, sizeof(test)) != 0)
  3.1499 +			return -EFAULT;
  3.1500 +		return 0;
  3.1501 +	}
  3.1502 +#endif	/* ETHTOOL_TEST */
  3.1503 +#ifdef	ETHTOOL_GRXCSUM
  3.1504 +	case ETHTOOL_GRXCSUM: {
  3.1505 +		struct ethtool_value edata = { ETHTOOL_GRXCSUM };
  3.1506 +
  3.1507 +		edata.data = adapter->rx_csum;
  3.1508 +		if (copy_to_user(addr, &edata, sizeof(edata)))
  3.1509 +			return -EFAULT;
  3.1510 +		return 0;
  3.1511 +	}
  3.1512 +#endif	/* ETHTOOL_GRXCSUM */
  3.1513 +#ifdef	ETHTOOL_SRXCSUM
  3.1514 +	case ETHTOOL_SRXCSUM: {
  3.1515 +		struct ethtool_value edata;
  3.1516 +
  3.1517 +		if (copy_from_user(&edata, addr, sizeof(edata)))
  3.1518 +			return -EFAULT;
  3.1519 +		adapter->rx_csum = edata.data;
  3.1520 +		if(netif_running(netdev)) {
  3.1521 +			e1000_down(adapter);
  3.1522 +			e1000_up(adapter);
  3.1523 +		} else
  3.1524 +			e1000_reset(adapter);
  3.1525 +		return 0;
  3.1526 +	}
  3.1527 +#endif	/* ETHTOOL_SRXCSUM */
  3.1528 +#ifdef	ETHTOOL_GTXCSUM
  3.1529 +	case ETHTOOL_GTXCSUM: {
  3.1530 +		struct ethtool_value edata = { ETHTOOL_GTXCSUM };
  3.1531 +
  3.1532 +		edata.data =
  3.1533 +			(netdev->features & NETIF_F_HW_CSUM) != 0;
  3.1534 +		if (copy_to_user(addr, &edata, sizeof(edata)))
  3.1535 +			return -EFAULT;
  3.1536 +		return 0;
  3.1537 +	}
  3.1538 +#endif	/* ETHTOOL_GTXCSUM */
  3.1539 +#ifdef	ETHTOOL_STXCSUM
  3.1540 +	case ETHTOOL_STXCSUM: {
  3.1541 +		struct ethtool_value edata;
  3.1542 +
  3.1543 +		if (copy_from_user(&edata, addr, sizeof(edata)))
  3.1544 +			return -EFAULT;
  3.1545 +
  3.1546 +		if(adapter->hw.mac_type < e1000_82543) {
  3.1547 +			if (edata.data != 0)
  3.1548 +				return -EINVAL;
  3.1549 +			return 0;
  3.1550 +		}
  3.1551 +
  3.1552 +		if (edata.data)
  3.1553 +			netdev->features |= NETIF_F_HW_CSUM;
  3.1554 +		else
  3.1555 +			netdev->features &= ~NETIF_F_HW_CSUM;
  3.1556 +
  3.1557 +		return 0;
  3.1558 +	}
  3.1559 +#endif	/* ETHTOOL_STXCSUM */
  3.1560 +#ifdef	ETHTOOL_GSG
  3.1561 +	case ETHTOOL_GSG: {
  3.1562 +		struct ethtool_value edata = { ETHTOOL_GSG };
  3.1563 +
  3.1564 +		edata.data =
  3.1565 +			(netdev->features & NETIF_F_SG) != 0;
  3.1566 +		if (copy_to_user(addr, &edata, sizeof(edata)))
  3.1567 +			return -EFAULT;
  3.1568 +		return 0;
  3.1569 +	}
  3.1570 +#endif	/* ETHTOOL_GSG */
  3.1571 +#ifdef	ETHTOOL_SSG
  3.1572 +	case ETHTOOL_SSG: {
  3.1573 +		struct ethtool_value edata;
  3.1574 +
  3.1575 +		if (copy_from_user(&edata, addr, sizeof(edata)))
  3.1576 +			return -EFAULT;
  3.1577 +
  3.1578 +		if (edata.data)
  3.1579 +			netdev->features |= NETIF_F_SG;
  3.1580 +		else
  3.1581 +			netdev->features &= ~NETIF_F_SG;
  3.1582 +
  3.1583 +		return 0;
  3.1584 +	}
  3.1585 +#endif	/* ETHTOOL_SSG */
  3.1586 +#ifdef NETIF_F_TSO
  3.1587 +#ifdef ETHTOOL_GTSO
  3.1588 +	case ETHTOOL_GTSO: {
  3.1589 +		struct ethtool_value edata = { ETHTOOL_GTSO };
  3.1590 +
  3.1591 +		edata.data = (netdev->features & NETIF_F_TSO) != 0;
  3.1592 +		if (copy_to_user(addr, &edata, sizeof(edata)))
  3.1593 +			return -EFAULT;
  3.1594 +		return 0;
  3.1595 +	}
  3.1596 +#endif /* ETHTOOL_GTSO */
  3.1597 +#ifdef ETHTOOL_STSO
  3.1598 +	case ETHTOOL_STSO: {
  3.1599 +		struct ethtool_value edata;
  3.1600 +
  3.1601 +		if (copy_from_user(&edata, addr, sizeof(edata)))
  3.1602 +			return -EFAULT;
  3.1603 +
  3.1604 +		if ((adapter->hw.mac_type < e1000_82544) ||
  3.1605 +		    (adapter->hw.mac_type == e1000_82547)) {
  3.1606 +			if (edata.data != 0)
  3.1607 +				return -EINVAL;
  3.1608 +			return 0;
  3.1609 +		}
  3.1610 +
  3.1611 +		if (edata.data)
  3.1612 +			netdev->features |= NETIF_F_TSO;
  3.1613 +		else
  3.1614 +			netdev->features &= ~NETIF_F_TSO;
  3.1615 +
  3.1616 +		return 0;
  3.1617 +	}
  3.1618 +#endif /* ETHTOOL_STSO */
  3.1619 +#endif
  3.1620  	default:
  3.1621  		return -EOPNOTSUPP;
  3.1622  	}
  3.1623  }
  3.1624  
  3.1625 +#endif	/* SIOCETHTOOL */
  3.1626  

     4.1 --- a/xen/drivers/net/e1000/e1000_hw.c	Tue Dec 02 16:30:20 2003 +0000
     4.2 +++ b/xen/drivers/net/e1000/e1000_hw.c	Wed Dec 10 18:35:31 2003 +0000
     4.3 @@ -1,7 +1,7 @@
     4.4  /*******************************************************************************
     4.5  
     4.6    
     4.7 -  Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
     4.8 +  Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
     4.9    
    4.10    This program is free software; you can redistribute it and/or modify it 
    4.11    under the terms of the GNU General Public License as published by the Free 
    4.12 @@ -32,29 +32,156 @@
    4.13  
    4.14  #include "e1000_hw.h"
    4.15  
    4.16 -static int32_t e1000_setup_fiber_link(struct e1000_hw *hw);
    4.17 +static int32_t e1000_set_phy_type(struct e1000_hw *hw);
    4.18 +static void e1000_phy_init_script(struct e1000_hw *hw);
    4.19  static int32_t e1000_setup_copper_link(struct e1000_hw *hw);
    4.20 +static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
    4.21 +static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
    4.22  static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw);
    4.23  static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw);
    4.24 -static int32_t e1000_force_mac_fc(struct e1000_hw *hw);
    4.25  static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
    4.26  static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
    4.27 -static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count);
    4.28 +static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data,
    4.29 +                                     uint16_t count);
    4.30  static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw);
    4.31  static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw);
    4.32 +static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset,
    4.33 +                                      uint16_t words, uint16_t *data);
    4.34 +static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw,
    4.35 +                                            uint16_t offset, uint16_t words,
    4.36 +                                            uint16_t *data);
    4.37 +static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw);
    4.38  static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
    4.39  static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
    4.40 -static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count);
    4.41 -static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw);
    4.42 -static void e1000_setup_eeprom(struct e1000_hw *hw);
    4.43 -static void e1000_clock_eeprom(struct e1000_hw *hw);
    4.44 -static void e1000_cleanup_eeprom(struct e1000_hw *hw);
    4.45 +static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data,
    4.46 +                                    uint16_t count);
    4.47 +static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
    4.48 +                                      uint16_t phy_data);
    4.49 +static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr,
    4.50 +                                     uint16_t *phy_data);
    4.51 +static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count);
    4.52 +static int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
    4.53 +static void e1000_release_eeprom(struct e1000_hw *hw);
    4.54  static void e1000_standby_eeprom(struct e1000_hw *hw);
    4.55  static int32_t e1000_id_led_init(struct e1000_hw * hw);
    4.56 +static int32_t e1000_set_vco_speed(struct e1000_hw *hw);
    4.57 +
    4.58 +/* IGP cable length table */
    4.59 +static const
    4.60 +uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
    4.61 +    { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
    4.62 +      5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
    4.63 +      25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
    4.64 +      40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
    4.65 +      60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
    4.66 +      90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
    4.67 +      100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
    4.68 +      110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
    4.69 +
    4.70 +
    4.71 +/******************************************************************************
    4.72 + * Set the phy type member in the hw struct.
    4.73 + *
    4.74 + * hw - Struct containing variables accessed by shared code
    4.75 + *****************************************************************************/
    4.76 +int32_t
    4.77 +e1000_set_phy_type(struct e1000_hw *hw)
    4.78 +{
    4.79 +    DEBUGFUNC("e1000_set_phy_type");
    4.80 +
    4.81 +    switch(hw->phy_id) {
    4.82 +    case M88E1000_E_PHY_ID:
    4.83 +    case M88E1000_I_PHY_ID:
    4.84 +    case M88E1011_I_PHY_ID:
    4.85 +        hw->phy_type = e1000_phy_m88;
    4.86 +        break;
    4.87 +    case IGP01E1000_I_PHY_ID:
    4.88 +        hw->phy_type = e1000_phy_igp;
    4.89 +        break;
    4.90 +    default:
    4.91 +        /* Should never have loaded on this device */
    4.92 +        hw->phy_type = e1000_phy_undefined;
    4.93 +        return -E1000_ERR_PHY_TYPE;
    4.94 +    }
    4.95 +
    4.96 +    return E1000_SUCCESS;
    4.97 +}
    4.98 +
    4.99 +/******************************************************************************
   4.100 + * IGP phy init script - initializes the GbE PHY
   4.101 + *
   4.102 + * hw - Struct containing variables accessed by shared code
   4.103 + *****************************************************************************/
   4.104 +static void
   4.105 +e1000_phy_init_script(struct e1000_hw *hw)
   4.106 +{
   4.107 +    DEBUGFUNC("e1000_phy_init_script");
   4.108 +
   4.109 +    if(hw->phy_init_script) {
   4.110 +        msec_delay(20);
   4.111 +
   4.112 +        e1000_write_phy_reg(hw,0x0000,0x0140);
   4.113 +
   4.114 +        msec_delay(5);
   4.115 +
   4.116 +        if(hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547) {
   4.117 +            e1000_write_phy_reg(hw, 0x1F95, 0x0001);
   4.118 +
   4.119 +            e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
   4.120 +
   4.121 +            e1000_write_phy_reg(hw, 0x1F79, 0x0018);
   4.122 +
   4.123 +            e1000_write_phy_reg(hw, 0x1F30, 0x1600);
   4.124 +
   4.125 +            e1000_write_phy_reg(hw, 0x1F31, 0x0014);
   4.126 +
   4.127 +            e1000_write_phy_reg(hw, 0x1F32, 0x161C);
   4.128 +
   4.129 +            e1000_write_phy_reg(hw, 0x1F94, 0x0003);
   4.130 +
   4.131 +            e1000_write_phy_reg(hw, 0x1F96, 0x003F);
   4.132 +
   4.133 +            e1000_write_phy_reg(hw, 0x2010, 0x0008);
   4.134 +        } else {
   4.135 +            e1000_write_phy_reg(hw, 0x1F73, 0x0099);
   4.136 +        }
   4.137 +
   4.138 +        e1000_write_phy_reg(hw, 0x0000, 0x3300);
   4.139 +
   4.140 +
   4.141 +        if(hw->mac_type == e1000_82547) {
   4.142 +            uint16_t fused, fine, coarse;
   4.143 +
   4.144 +            /* Move to analog registers page */
   4.145 +            e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
   4.146 +
   4.147 +            if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
   4.148 +                e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
   4.149 +
   4.150 +                fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
   4.151 +                coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
   4.152 +
   4.153 +                if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
   4.154 +                    coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
   4.155 +                    fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
   4.156 +                } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
   4.157 +                    fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
   4.158 +
   4.159 +                fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
   4.160 +                        (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
   4.161 +                        (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
   4.162 +
   4.163 +                e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
   4.164 +                e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
   4.165 +                                    IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
   4.166 +            }
   4.167 +        }
   4.168 +    }
   4.169 +}
   4.170  
   4.171  /******************************************************************************
   4.172   * Set the mac type member in the hw struct.
   4.173 - * 
   4.174 + *
   4.175   * hw - Struct containing variables accessed by shared code
   4.176   *****************************************************************************/
   4.177  int32_t
   4.178 @@ -97,30 +224,99 @@ e1000_set_mac_type(struct e1000_hw *hw)
   4.179      case E1000_DEV_ID_82545EM_FIBER:
   4.180          hw->mac_type = e1000_82545;
   4.181          break;
   4.182 +    case E1000_DEV_ID_82545GM_COPPER:
   4.183 +    case E1000_DEV_ID_82545GM_FIBER:
   4.184 +    case E1000_DEV_ID_82545GM_SERDES:
   4.185 +        hw->mac_type = e1000_82545_rev_3;
   4.186 +        break;
   4.187      case E1000_DEV_ID_82546EB_COPPER:
   4.188      case E1000_DEV_ID_82546EB_FIBER:
   4.189 +    case E1000_DEV_ID_82546EB_QUAD_COPPER:
   4.190          hw->mac_type = e1000_82546;
   4.191          break;
   4.192 +    case E1000_DEV_ID_82546GB_COPPER:
   4.193 +    case E1000_DEV_ID_82546GB_FIBER:
   4.194 +    case E1000_DEV_ID_82546GB_SERDES:
   4.195 +        hw->mac_type = e1000_82546_rev_3;
   4.196 +        break;
   4.197 +    case E1000_DEV_ID_82541EI:
   4.198 +    case E1000_DEV_ID_82541EI_MOBILE:
   4.199 +        hw->mac_type = e1000_82541;
   4.200 +        break;
   4.201 +    case E1000_DEV_ID_82541ER:
   4.202 +    case E1000_DEV_ID_82541GI:
   4.203 +    case E1000_DEV_ID_82541GI_MOBILE:
   4.204 +        hw->mac_type = e1000_82541_rev_2;
   4.205 +        break;
   4.206 +    case E1000_DEV_ID_82547EI:
   4.207 +        hw->mac_type = e1000_82547;
   4.208 +        break;
   4.209 +    case E1000_DEV_ID_82547GI:
   4.210 +        hw->mac_type = e1000_82547_rev_2;
   4.211 +        break;
   4.212      default:
   4.213          /* Should never have loaded on this device */
   4.214          return -E1000_ERR_MAC_TYPE;
   4.215      }
   4.216 +
   4.217      return E1000_SUCCESS;
   4.218  }
   4.219 +
   4.220 +/*****************************************************************************
   4.221 + * Set media type and TBI compatibility.
   4.222 + *
   4.223 + * hw - Struct containing variables accessed by shared code
   4.224 + * **************************************************************************/
   4.225 +void
   4.226 +e1000_set_media_type(struct e1000_hw *hw)
   4.227 +{
   4.228 +    uint32_t status;
   4.229 +
   4.230 +    DEBUGFUNC("e1000_set_media_type");
   4.231 +
   4.232 +    if(hw->mac_type != e1000_82543) {
   4.233 +        /* tbi_compatibility is only valid on 82543 */
   4.234 +        hw->tbi_compatibility_en = FALSE;
   4.235 +    }
   4.236 +
   4.237 +    switch (hw->device_id) {
   4.238 +    case E1000_DEV_ID_82545GM_SERDES:
   4.239 +    case E1000_DEV_ID_82546GB_SERDES:
   4.240 +        hw->media_type = e1000_media_type_internal_serdes;
   4.241 +        break;
   4.242 +    default:
   4.243 +        if(hw->mac_type >= e1000_82543) {
   4.244 +            status = E1000_READ_REG(hw, STATUS);
   4.245 +            if(status & E1000_STATUS_TBIMODE) {
   4.246 +                hw->media_type = e1000_media_type_fiber;
   4.247 +                /* tbi_compatibility not valid on fiber */
   4.248 +                hw->tbi_compatibility_en = FALSE;
   4.249 +            } else {
   4.250 +                hw->media_type = e1000_media_type_copper;
   4.251 +            }
   4.252 +        } else {
   4.253 +            /* This is an 82542 (fiber only) */
   4.254 +            hw->media_type = e1000_media_type_fiber;
   4.255 +        }
   4.256 +    }
   4.257 +}
   4.258 +
   4.259  /******************************************************************************
   4.260   * Reset the transmit and receive units; mask and clear all interrupts.
   4.261   *
   4.262   * hw - Struct containing variables accessed by shared code
   4.263   *****************************************************************************/
   4.264 -void
   4.265 +int32_t
   4.266  e1000_reset_hw(struct e1000_hw *hw)
   4.267  {
   4.268      uint32_t ctrl;
   4.269      uint32_t ctrl_ext;
   4.270      uint32_t icr;
   4.271      uint32_t manc;
   4.272 +    uint32_t led_ctrl;
   4.273  
   4.274      DEBUGFUNC("e1000_reset_hw");
   4.275 +
   4.276      /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
   4.277      if(hw->mac_type == e1000_82542_rev2_0) {
   4.278          DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
   4.279 @@ -144,42 +340,93 @@ e1000_reset_hw(struct e1000_hw *hw)
   4.280  
   4.281      /* Delay to allow any outstanding PCI transactions to complete before
   4.282       * resetting the device
   4.283 -     */ 
   4.284 -    DEBUGOUT("Before delay\n");
   4.285 +     */
   4.286      msec_delay(10);
   4.287  
   4.288 +    ctrl = E1000_READ_REG(hw, CTRL);
   4.289 +
   4.290 +    /* Must reset the PHY before resetting the MAC */
   4.291 +    if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
   4.292 +        E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
   4.293 +        msec_delay(5);
   4.294 +    }
   4.295 +
   4.296      /* Issue a global reset to the MAC.  This will reset the chip's
   4.297       * transmit, receive, DMA, and link units.  It will not effect
   4.298       * the current PCI configuration.  The global reset bit is self-
   4.299       * clearing, and should clear within a microsecond.
   4.300       */
   4.301      DEBUGOUT("Issuing a global reset to MAC\n");
   4.302 -    ctrl = E1000_READ_REG(hw, CTRL);
   4.303 -
   4.304 -    if(hw->mac_type > e1000_82543)
   4.305 -        E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
   4.306 -    else
   4.307 -        E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
   4.308 -
   4.309 -    /* Force a reload from the EEPROM if necessary */
   4.310 -    if(hw->mac_type < e1000_82540) {
   4.311 -        /* Wait for reset to complete */
   4.312 -        udelay(10);
   4.313 -        ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
   4.314 -        ctrl_ext |= E1000_CTRL_EXT_EE_RST;
   4.315 -        E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
   4.316 -        E1000_WRITE_FLUSH(hw);
   4.317 -        /* Wait for EEPROM reload */
   4.318 -        msec_delay(2);
   4.319 -    } else {
   4.320 -        /* Wait for EEPROM reload (it happens automatically) */
   4.321 -        msec_delay(4);
   4.322 -        /* Dissable HW ARPs on ASF enabled adapters */
   4.323 +
   4.324 +    switch(hw->mac_type) {
   4.325 +        case e1000_82544:
   4.326 +        case e1000_82540:
   4.327 +        case e1000_82545:
   4.328 +        case e1000_82546:
   4.329 +        case e1000_82541:
   4.330 +        case e1000_82541_rev_2:
   4.331 +            /* These controllers can't ack the 64-bit write when issuing the
   4.332 +             * reset, so use IO-mapping as a workaround to issue the reset */
   4.333 +            E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
   4.334 +            break;
   4.335 +        case e1000_82545_rev_3:
   4.336 +        case e1000_82546_rev_3:
   4.337 +            /* Reset is performed on a shadow of the control register */
   4.338 +            E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
   4.339 +            break;
   4.340 +        default:
   4.341 +            E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
   4.342 +            break;
   4.343 +    }
   4.344 +
   4.345 +    /* After MAC reset, force reload of EEPROM to restore power-on settings to
   4.346 +     * device.  Later controllers reload the EEPROM automatically, so just wait
   4.347 +     * for reload to complete.
   4.348 +     */
   4.349 +    switch(hw->mac_type) {
   4.350 +        case e1000_82542_rev2_0:
   4.351 +        case e1000_82542_rev2_1:
   4.352 +        case e1000_82543:
   4.353 +        case e1000_82544:
   4.354 +            /* Wait for reset to complete */
   4.355 +            usec_delay(10);
   4.356 +            ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
   4.357 +            ctrl_ext |= E1000_CTRL_EXT_EE_RST;
   4.358 +            E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
   4.359 +            E1000_WRITE_FLUSH(hw);
   4.360 +            /* Wait for EEPROM reload */
   4.361 +            msec_delay(2);
   4.362 +            break;
   4.363 +        case e1000_82541:
   4.364 +        case e1000_82541_rev_2:
   4.365 +        case e1000_82547:
   4.366 +        case e1000_82547_rev_2:
   4.367 +            /* Wait for EEPROM reload */
   4.368 +            msec_delay(20);
   4.369 +            break;
   4.370 +        default:
   4.371 +            /* Wait for EEPROM reload (it happens automatically) */
   4.372 +            msec_delay(5);
   4.373 +            break;
   4.374 +    }
   4.375 +
   4.376 +    /* Disable HW ARPs on ASF enabled adapters */
   4.377 +    if(hw->mac_type >= e1000_82540) {
   4.378          manc = E1000_READ_REG(hw, MANC);
   4.379          manc &= ~(E1000_MANC_ARP_EN);
   4.380          E1000_WRITE_REG(hw, MANC, manc);
   4.381      }
   4.382 -    
   4.383 +
   4.384 +    if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
   4.385 +        e1000_phy_init_script(hw);
   4.386 +
   4.387 +        /* Configure activity LED after PHY reset */
   4.388 +        led_ctrl = E1000_READ_REG(hw, LEDCTL);
   4.389 +        led_ctrl &= IGP_ACTIVITY_LED_MASK;
   4.390 +        led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
   4.391 +        E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
   4.392 +    }
   4.393 +
   4.394      /* Clear interrupt mask to stop board from generating interrupts */
   4.395      DEBUGOUT("Masking off all interrupts\n");
   4.396      E1000_WRITE_REG(hw, IMC, 0xffffffff);
   4.397 @@ -192,14 +439,16 @@ e1000_reset_hw(struct e1000_hw *hw)
   4.398          if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
   4.399              e1000_pci_set_mwi(hw);
   4.400      }
   4.401 +
   4.402 +    return E1000_SUCCESS;
   4.403  }
   4.404  
   4.405  /******************************************************************************
   4.406   * Performs basic configuration of the adapter.
   4.407   *
   4.408   * hw - Struct containing variables accessed by shared code
   4.409 - * 
   4.410 - * Assumes that the controller has previously been reset and is in a 
   4.411 + *
   4.412 + * Assumes that the controller has previously been reset and is in a
   4.413   * post-reset uninitialized state. Initializes the receive address registers,
   4.414   * multicast table, and VLAN filter table. Calls routines to setup link
   4.415   * configuration and flow control settings. Clears all on-chip counters. Leaves
   4.416 @@ -208,7 +457,7 @@ e1000_reset_hw(struct e1000_hw *hw)
   4.417  int32_t
   4.418  e1000_init_hw(struct e1000_hw *hw)
   4.419  {
   4.420 -    uint32_t ctrl, status;
   4.421 +    uint32_t ctrl;
   4.422      uint32_t i;
   4.423      int32_t ret_val;
   4.424      uint16_t pcix_cmd_word;
   4.425 @@ -219,31 +468,13 @@ e1000_init_hw(struct e1000_hw *hw)
   4.426      DEBUGFUNC("e1000_init_hw");
   4.427  
   4.428      /* Initialize Identification LED */
   4.429 -    ret_val = e1000_id_led_init(hw);
   4.430 -    if(ret_val < 0) {
   4.431 +    if((ret_val = e1000_id_led_init(hw))) {
   4.432          DEBUGOUT("Error Initializing Identification LED\n");
   4.433          return ret_val;
   4.434      }
   4.435 -    
   4.436 -    /* Set the Media Type and exit with error if it is not valid. */
   4.437 -    if(hw->mac_type != e1000_82543) {
   4.438 -        /* tbi_compatibility is only valid on 82543 */
   4.439 -        hw->tbi_compatibility_en = FALSE;
   4.440 -    }
   4.441 -
   4.442 -    if(hw->mac_type >= e1000_82543) {
   4.443 -        status = E1000_READ_REG(hw, STATUS);
   4.444 -        if(status & E1000_STATUS_TBIMODE) {
   4.445 -            hw->media_type = e1000_media_type_fiber;
   4.446 -            /* tbi_compatibility not valid on fiber */
   4.447 -            hw->tbi_compatibility_en = FALSE;
   4.448 -        } else {
   4.449 -            hw->media_type = e1000_media_type_copper;
   4.450 -        }
   4.451 -    } else {
   4.452 -        /* This is an 82542 (fiber only) */
   4.453 -        hw->media_type = e1000_media_type_fiber;
   4.454 -    }
   4.455 +
   4.456 +    /* Set the media type and TBI compatibility */
   4.457 +    e1000_set_media_type(hw);
   4.458  
   4.459      /* Disabling VLAN filtering. */
   4.460      DEBUGOUT("Initializing the IEEE VLAN\n");
   4.461 @@ -288,21 +519,30 @@ e1000_init_hw(struct e1000_hw *hw)
   4.462          E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
   4.463      }
   4.464  
   4.465 -    /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
   4.466 -    if(hw->bus_type == e1000_bus_type_pcix) {
   4.467 -        e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
   4.468 -        e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
   4.469 -        cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
   4.470 -            PCIX_COMMAND_MMRBC_SHIFT;
   4.471 -        stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
   4.472 -            PCIX_STATUS_HI_MMRBC_SHIFT;
   4.473 -        if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
   4.474 -            stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
   4.475 -        if(cmd_mmrbc > stat_mmrbc) {
   4.476 -            pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
   4.477 -            pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
   4.478 -            e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
   4.479 +    switch(hw->mac_type) {
   4.480 +    case e1000_82545_rev_3:
   4.481 +    case e1000_82546_rev_3:
   4.482 +        break;
   4.483 +    default:
   4.484 +        /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
   4.485 +        if(hw->bus_type == e1000_bus_type_pcix) {
   4.486 +            e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
   4.487 +            e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
   4.488 +                &pcix_stat_hi_word);
   4.489 +            cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
   4.490 +                PCIX_COMMAND_MMRBC_SHIFT;
   4.491 +            stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
   4.492 +                PCIX_STATUS_HI_MMRBC_SHIFT;
   4.493 +            if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
   4.494 +                stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
   4.495 +            if(cmd_mmrbc > stat_mmrbc) {
   4.496 +                pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
   4.497 +                pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
   4.498 +                e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
   4.499 +                    &pcix_cmd_word);
   4.500 +            }
   4.501          }
   4.502 +        break;
   4.503      }
   4.504  
   4.505      /* Call a subroutine to configure the link and setup flow control. */
   4.506 @@ -326,14 +566,54 @@ e1000_init_hw(struct e1000_hw *hw)
   4.507  }
   4.508  
   4.509  /******************************************************************************
   4.510 + * Adjust SERDES output amplitude based on EEPROM setting.
   4.511 + *
   4.512 + * hw - Struct containing variables accessed by shared code.
   4.513 + *****************************************************************************/
   4.514 +static int32_t
   4.515 +e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
   4.516 +{
   4.517 +    uint16_t eeprom_data;
   4.518 +    int32_t  ret_val;
   4.519 +
   4.520 +    DEBUGFUNC("e1000_adjust_serdes_amplitude");
   4.521 +
   4.522 +    if(hw->media_type != e1000_media_type_internal_serdes)
   4.523 +        return E1000_SUCCESS;
   4.524 +
   4.525 +    switch(hw->mac_type) {
   4.526 +    case e1000_82545_rev_3:
   4.527 +    case e1000_82546_rev_3:
   4.528 +        break;
   4.529 +    default:
   4.530 +        return E1000_SUCCESS;
   4.531 +    }
   4.532 +
   4.533 +    if ((ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
   4.534 +                                     &eeprom_data))) {
   4.535 +        return ret_val;
   4.536 +    }
   4.537 +
   4.538 +    if(eeprom_data != EEPROM_RESERVED_WORD) {
   4.539 +        /* Adjust SERDES output amplitude only. */
   4.540 +        eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; 
   4.541 +        if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL,
   4.542 +                                          eeprom_data)))
   4.543 +            return ret_val;
   4.544 +    }
   4.545 +
   4.546 +    return E1000_SUCCESS;
   4.547 +}
   4.548 +
   4.549 +/******************************************************************************
   4.550   * Configures flow control and link settings.
   4.551 - * 
   4.552 + *
   4.553   * hw - Struct containing variables accessed by shared code
   4.554 - * 
   4.555 + *
   4.556   * Determines which flow control settings to use. Calls the apropriate media-
   4.557   * specific link configuration function. Configures the flow control settings.
   4.558   * Assuming the adapter has a valid link partner, a valid link should be
   4.559 - * established. Assumes the hardware has previously been reset and the 
   4.560 + * established. Assumes the hardware has previously been reset and the
   4.561   * transmitter and receiver are not enabled.
   4.562   *****************************************************************************/
   4.563  int32_t
   4.564 @@ -353,7 +633,7 @@ e1000_setup_link(struct e1000_hw *hw)
   4.565       * control setting, then the variable hw->fc will
   4.566       * be initialized based on a value in the EEPROM.
   4.567       */
   4.568 -    if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, &eeprom_data) < 0) {
   4.569 +    if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data) < 0) {
   4.570          DEBUGOUT("EEPROM Read Error\n");
   4.571          return -E1000_ERR_EEPROM;
   4.572      }
   4.573 @@ -361,7 +641,7 @@ e1000_setup_link(struct e1000_hw *hw)
   4.574      if(hw->fc == e1000_fc_default) {
   4.575          if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
   4.576              hw->fc = e1000_fc_none;
   4.577 -        else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 
   4.578 +        else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
   4.579                  EEPROM_WORD0F_ASM_DIR)
   4.580              hw->fc = e1000_fc_tx_pause;
   4.581          else
   4.582 @@ -390,15 +670,15 @@ e1000_setup_link(struct e1000_hw *hw)
   4.583       * or e1000_phy_setup() is called.
   4.584       */
   4.585      if(hw->mac_type == e1000_82543) {
   4.586 -        ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 
   4.587 +        ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
   4.588                      SWDPIO__EXT_SHIFT);
   4.589          E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
   4.590      }
   4.591  
   4.592      /* Call the necessary subroutine to configure the link. */
   4.593 -    ret_val = (hw->media_type == e1000_media_type_fiber) ?
   4.594 -              e1000_setup_fiber_link(hw) :
   4.595 -              e1000_setup_copper_link(hw);
   4.596 +    ret_val = (hw->media_type == e1000_media_type_copper) ?
   4.597 +              e1000_setup_copper_link(hw) :
   4.598 +              e1000_setup_fiber_serdes_link(hw);
   4.599  
   4.600      /* Initialize the flow control address, type, and PAUSE timer
   4.601       * registers to their default values.  This is done even if flow
   4.602 @@ -416,7 +696,7 @@ e1000_setup_link(struct e1000_hw *hw)
   4.603       * these registers will be set to a default threshold that may be
   4.604       * adjusted later by the driver's runtime code.  However, if the
   4.605       * ability to transmit pause frames in not enabled, then these
   4.606 -     * registers will be set to 0. 
   4.607 +     * registers will be set to 0.
   4.608       */
   4.609      if(!(hw->fc & e1000_fc_tx_pause)) {
   4.610          E1000_WRITE_REG(hw, FCRTL, 0);
   4.611 @@ -437,7 +717,7 @@ e1000_setup_link(struct e1000_hw *hw)
   4.612  }
   4.613  
   4.614  /******************************************************************************
   4.615 - * Sets up link for a fiber based adapter
   4.616 + * Sets up link for a fiber based or serdes based adapter
   4.617   *
   4.618   * hw - Struct containing variables accessed by shared code
   4.619   *
   4.620 @@ -445,41 +725,50 @@ e1000_setup_link(struct e1000_hw *hw)
   4.621   * link. Assumes the hardware has been previously reset and the transmitter
   4.622   * and receiver are not enabled.
   4.623   *****************************************************************************/
   4.624 -static int32_t 
   4.625 -e1000_setup_fiber_link(struct e1000_hw *hw)
   4.626 +static int32_t
   4.627 +e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
   4.628  {
   4.629      uint32_t ctrl;
   4.630      uint32_t status;
   4.631      uint32_t txcw = 0;
   4.632      uint32_t i;
   4.633 -    uint32_t signal;
   4.634 +    uint32_t signal = 0;
   4.635      int32_t ret_val;
   4.636  
   4.637 -    DEBUGFUNC("e1000_setup_fiber_link");
   4.638 -
   4.639 -    /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 
   4.640 -     * set when the optics detect a signal. On older adapters, it will be 
   4.641 -     * cleared when there is a signal
   4.642 +    DEBUGFUNC("e1000_setup_fiber_serdes_link");
   4.643 +
   4.644 +    /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
   4.645 +     * set when the optics detect a signal. On older adapters, it will be
   4.646 +     * cleared when there is a signal.  This applies to fiber media only.
   4.647 +     * If we're on serdes media, adjust the output amplitude to value set in
   4.648 +     * the EEPROM.
   4.649       */
   4.650      ctrl = E1000_READ_REG(hw, CTRL);
   4.651 -    if(hw->mac_type > e1000_82544) signal = E1000_CTRL_SWDPIN1;
   4.652 -    else signal = 0;
   4.653 -   
   4.654 +    if(hw->media_type == e1000_media_type_fiber)
   4.655 +        signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
   4.656 +
   4.657 +    if((ret_val = e1000_adjust_serdes_amplitude(hw)))
   4.658 +        return ret_val;
   4.659 +
   4.660      /* Take the link out of reset */
   4.661      ctrl &= ~(E1000_CTRL_LRST);
   4.662 -    
   4.663 +
   4.664 +    /* Adjust VCO speed to improve BER performance */
   4.665 +    if((ret_val = e1000_set_vco_speed(hw)))
   4.666 +        return ret_val;
   4.667 +
   4.668      e1000_config_collision_dist(hw);
   4.669  
   4.670      /* Check for a software override of the flow control settings, and setup
   4.671       * the device accordingly.  If auto-negotiation is enabled, then software
   4.672       * will have to set the "PAUSE" bits to the correct value in the Tranmsit
   4.673       * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
   4.674 -     * auto-negotiation is disabled, then software will have to manually 
   4.675 +     * auto-negotiation is disabled, then software will have to manually
   4.676       * configure the two flow control enable bits in the CTRL register.
   4.677       *
   4.678       * The possible values of the "fc" parameter are:
   4.679       *      0:  Flow control is completely disabled
   4.680 -     *      1:  Rx flow control is enabled (we can receive pause frames, but 
   4.681 +     *      1:  Rx flow control is enabled (we can receive pause frames, but
   4.682       *          not send pause frames).
   4.683       *      2:  Tx flow control is enabled (we can send pause frames but we do
   4.684       *          not support receiving pause frames).
   4.685 @@ -491,8 +780,8 @@ e1000_setup_fiber_link(struct e1000_hw *
   4.686          txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
   4.687          break;
   4.688      case e1000_fc_rx_pause:
   4.689 -        /* RX Flow control is enabled and TX Flow control is disabled by a 
   4.690 -         * software over-ride. Since there really isn't a way to advertise 
   4.691 +        /* RX Flow control is enabled and TX Flow control is disabled by a
   4.692 +         * software over-ride. Since there really isn't a way to advertise
   4.693           * that we are capable of RX Pause ONLY, we will advertise that we
   4.694           * support both symmetric and asymmetric RX PAUSE. Later, we will
   4.695           *  disable the adapter's ability to send PAUSE frames.
   4.696 @@ -500,7 +789,7 @@ e1000_setup_fiber_link(struct e1000_hw *
   4.697          txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
   4.698          break;
   4.699      case e1000_fc_tx_pause:
   4.700 -        /* TX Flow control is enabled, and RX Flow control is disabled, by a 
   4.701 +        /* TX Flow control is enabled, and RX Flow control is disabled, by a
   4.702           * software over-ride.
   4.703           */
   4.704          txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
   4.705 @@ -531,11 +820,13 @@ e1000_setup_fiber_link(struct e1000_hw *
   4.706      msec_delay(1);
   4.707  
   4.708      /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
   4.709 -     * indication in the Device Status Register.  Time-out if a link isn't 
   4.710 -     * seen in 500 milliseconds seconds (Auto-negotiation should complete in 
   4.711 +     * indication in the Device Status Register.  Time-out if a link isn't
   4.712 +     * seen in 500 milliseconds seconds (Auto-negotiation should complete in
   4.713       * less than 500 milliseconds even if the other end is doing it in SW).
   4.714 +     * For internal serdes, we just assume a signal is present, then poll.
   4.715       */
   4.716 -    if((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
   4.717 +    if(hw->media_type == e1000_media_type_internal_serdes ||
   4.718 +       (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
   4.719          DEBUGOUT("Looking for Link\n");
   4.720          for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
   4.721              msec_delay(10);
   4.722 @@ -543,19 +834,20 @@ e1000_setup_fiber_link(struct e1000_hw *
   4.723              if(status & E1000_STATUS_LU) break;
   4.724          }
   4.725          if(i == (LINK_UP_TIMEOUT / 10)) {
   4.726 -            /* AutoNeg failed to achieve a link, so we'll call 
   4.727 -             * e1000_check_for_link. This routine will force the link up if we
   4.728 -             * detect a signal. This will allow us to communicate with
   4.729 -             * non-autonegotiating link partners.
   4.730 -             */
   4.731              DEBUGOUT("Never got a valid link from auto-neg!!!\n");
   4.732              hw->autoneg_failed = 1;
   4.733 -            ret_val = e1000_check_for_link(hw);
   4.734 -            if(ret_val < 0) {
   4.735 -                DEBUGOUT("Error while checking for link\n");
   4.736 -                return ret_val;
   4.737 +            if(hw->media_type == e1000_media_type_fiber) {
   4.738 +                /* AutoNeg failed to achieve a link, so we'll call
   4.739 +                 * e1000_check_for_link. This routine will force the link up if
   4.740 +                 * we detect a signal. This will allow us to communicate with
   4.741 +                 * non-autonegotiating link partners.
   4.742 +                 */
   4.743 +                if((ret_val = e1000_check_for_link(hw))) {
   4.744 +                    DEBUGOUT("Error while checking for link\n");
   4.745 +                    return ret_val;
   4.746 +                }
   4.747 +                hw->autoneg_failed = 0;
   4.748              }
   4.749 -            hw->autoneg_failed = 0;
   4.750          } else {
   4.751              hw->autoneg_failed = 0;
   4.752              DEBUGOUT("Valid Link Found\n");
   4.753 @@ -563,7 +855,7 @@ e1000_setup_fiber_link(struct e1000_hw *
   4.754      } else {
   4.755          DEBUGOUT("No Signal Detected\n");
   4.756      }
   4.757 -    return 0;
   4.758 +    return E1000_SUCCESS;
   4.759  }
   4.760  
   4.761  /******************************************************************************
   4.762 @@ -571,10 +863,11 @@ e1000_setup_fiber_link(struct e1000_hw *
   4.763  *
   4.764  * hw - Struct containing variables accessed by shared code
   4.765  ******************************************************************************/
   4.766 -static int32_t 
   4.767 +static int32_t
   4.768  e1000_setup_copper_link(struct e1000_hw *hw)
   4.769  {
   4.770      uint32_t ctrl;
   4.771 +    uint32_t led_ctrl;
   4.772      int32_t ret_val;
   4.773      uint16_t i;
   4.774      uint16_t phy_data;
   4.775 @@ -597,166 +890,281 @@ e1000_setup_copper_link(struct e1000_hw 
   4.776      }
   4.777  
   4.778      /* Make sure we have a valid PHY */
   4.779 -    ret_val = e1000_detect_gig_phy(hw);
   4.780 -    if(ret_val < 0) {
   4.781 +    if((ret_val = e1000_detect_gig_phy(hw))) {
   4.782          DEBUGOUT("Error, did not detect valid phy.\n");
   4.783          return ret_val;
   4.784      }
   4.785      DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
   4.786  
   4.787 -    /* Enable CRS on TX. This must be set for half-duplex operation. */
   4.788 -    if(e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) {
   4.789 -        DEBUGOUT("PHY Read Error\n");
   4.790 -        return -E1000_ERR_PHY;
   4.791 -    }
   4.792 -    phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
   4.793 -
   4.794 -    /* Options:
   4.795 -     *   MDI/MDI-X = 0 (default)
   4.796 -     *   0 - Auto for all speeds
   4.797 -     *   1 - MDI mode
   4.798 -     *   2 - MDI-X mode
   4.799 -     *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
   4.800 -     */
   4.801 -    phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
   4.802 -
   4.803 -    switch (hw->mdix) {
   4.804 -    case 1:
   4.805 -        phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
   4.806 -        break;
   4.807 -    case 2:
   4.808 -        phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
   4.809 -        break;
   4.810 -    case 3:
   4.811 -        phy_data |= M88E1000_PSCR_AUTO_X_1000T;
   4.812 -        break;
   4.813 -    case 0:
   4.814 -    default:
   4.815 -        phy_data |= M88E1000_PSCR_AUTO_X_MODE;
   4.816 -        break;
   4.817 -    }
   4.818 -
   4.819 -    /* Options:
   4.820 -     *   disable_polarity_correction = 0 (default)
   4.821 -     *       Automatic Correction for Reversed Cable Polarity
   4.822 -     *   0 - Disabled
   4.823 -     *   1 - Enabled
   4.824 -     */
   4.825 -    phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
   4.826 -    if(hw->disable_polarity_correction == 1)
   4.827 -        phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
   4.828 -    if(e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) {
   4.829 -        DEBUGOUT("PHY Write Error\n");
   4.830 -        return -E1000_ERR_PHY;
   4.831 -    }
   4.832 -
   4.833 -    /* Force TX_CLK in the Extended PHY Specific Control Register
   4.834 -     * to 25MHz clock.
   4.835 -     */
   4.836 -    if(e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data) < 0) {
   4.837 -        DEBUGOUT("PHY Read Error\n");
   4.838 -        return -E1000_ERR_PHY;
   4.839 -    }
   4.840 -    phy_data |= M88E1000_EPSCR_TX_CLK_25;
   4.841 -
   4.842 -    if (hw->phy_revision < M88E1011_I_REV_4) {
   4.843 -        /* Configure Master and Slave downshift values */
   4.844 -        phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
   4.845 -                      M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
   4.846 -        phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
   4.847 -                     M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
   4.848 -        if(e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data) < 0) {
   4.849 -            DEBUGOUT("PHY Write Error\n");
   4.850 -            return -E1000_ERR_PHY;
   4.851 -        }
   4.852 -    }
   4.853 -
   4.854 -    /* SW Reset the PHY so all changes take effect */
   4.855 -    ret_val = e1000_phy_reset(hw);
   4.856 -    if(ret_val < 0) {
   4.857 -        DEBUGOUT("Error Resetting the PHY\n");
   4.858 -        return ret_val;
   4.859 -    }
   4.860 -    
   4.861 -    /* Options:
   4.862 -     *   autoneg = 1 (default)
   4.863 -     *      PHY will advertise value(s) parsed from
   4.864 -     *      autoneg_advertised and fc
   4.865 -     *   autoneg = 0
   4.866 -     *      PHY will be set to 10H, 10F, 100H, or 100F
   4.867 -     *      depending on value parsed from forced_speed_duplex.
   4.868 -     */
   4.869 -
   4.870 -    /* Is autoneg enabled?  This is enabled by default or by software override.
   4.871 -     * If so, call e1000_phy_setup_autoneg routine to parse the
   4.872 -     * autoneg_advertised and fc options. If autoneg is NOT enabled, then the
   4.873 -     * user should have provided a speed/duplex override.  If so, then call
   4.874 -     * e1000_phy_force_speed_duplex to parse and set this up.
   4.875 -     */
   4.876 -    if(hw->autoneg) {
   4.877 -        /* Perform some bounds checking on the hw->autoneg_advertised
   4.878 -         * parameter.  If this variable is zero, then set it to the default.
   4.879 -         */
   4.880 -        hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
   4.881 -
   4.882 -        /* If autoneg_advertised is zero, we assume it was not defaulted
   4.883 -         * by the calling code so we set to advertise full capability.
   4.884 -         */
   4.885 -        if(hw->autoneg_advertised == 0)
   4.886 -            hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
   4.887 -
   4.888 -        DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
   4.889 -        ret_val = e1000_phy_setup_autoneg(hw);
   4.890 -        if(ret_val < 0) {
   4.891 -            DEBUGOUT("Error Setting up Auto-Negotiation\n");
   4.892 -            return ret_val;
   4.893 -        }
   4.894 -        DEBUGOUT("Restarting Auto-Neg\n");
   4.895 -
   4.896 -        /* Restart auto-negotiation by setting the Auto Neg Enable bit and
   4.897 -         * the Auto Neg Restart bit in the PHY control register.
   4.898 -         */
   4.899 -        if(e1000_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) {
   4.900 -            DEBUGOUT("PHY Read Error\n");
   4.901 -            return -E1000_ERR_PHY;
   4.902 -        }
   4.903 -        phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
   4.904 -        if(e1000_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) {
   4.905 -            DEBUGOUT("PHY Write Error\n");
   4.906 -            return -E1000_ERR_PHY;
   4.907 -        }
   4.908 -
   4.909 -        /* Does the user want to wait for Auto-Neg to complete here, or
   4.910 -         * check at a later time (for example, callback routine).
   4.911 -         */
   4.912 -        if(hw->wait_autoneg_complete) {
   4.913 -            ret_val = e1000_wait_autoneg(hw);
   4.914 -            if(ret_val < 0) {
   4.915 -                DEBUGOUT("Error while waiting for autoneg to complete\n");
   4.916 +    if(hw->mac_type <= e1000_82543 ||
   4.917 +       hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
   4.918 +       hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
   4.919 +        hw->phy_reset_disable = FALSE;
   4.920 +
   4.921 +    if(!hw->phy_reset_disable) {
   4.922 +        if (hw->phy_type == e1000_phy_igp) {
   4.923 +
   4.924 +            if((ret_val = e1000_phy_reset(hw))) {
   4.925 +                DEBUGOUT("Error Resetting the PHY\n");
   4.926 +                return ret_val;
   4.927 +            }
   4.928 +
   4.929 +            /* Wait 10ms for MAC to configure PHY from eeprom settings */
   4.930 +            msec_delay(15);
   4.931 +
   4.932 +            /* Configure activity LED after PHY reset */
   4.933 +            led_ctrl = E1000_READ_REG(hw, LEDCTL);
   4.934 +            led_ctrl &= IGP_ACTIVITY_LED_MASK;
   4.935 +            led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
   4.936 +            E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
   4.937 +
   4.938 +            /* disable lplu d3 during driver init */
   4.939 +            if((ret_val = e1000_set_d3_lplu_state(hw, FALSE))) {
   4.940 +                DEBUGOUT("Error Disabling LPLU D3\n");
   4.941 +                return ret_val;
   4.942 +            }
   4.943 +
   4.944 +            /* Configure mdi-mdix settings */
   4.945 +            if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
   4.946 +                                             &phy_data)))
   4.947 +                return ret_val;
   4.948 +
   4.949 +            if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
   4.950 +                hw->dsp_config_state = e1000_dsp_config_disabled;
   4.951 +                /* Force MDI for IGP B-0 PHY */
   4.952 +                phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX |
   4.953 +                              IGP01E1000_PSCR_FORCE_MDI_MDIX);
   4.954 +                hw->mdix = 1;
   4.955 +
   4.956 +            } else {
   4.957 +                hw->dsp_config_state = e1000_dsp_config_enabled;
   4.958 +                phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
   4.959 +
   4.960 +                switch (hw->mdix) {
   4.961 +                case 1:
   4.962 +                    phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
   4.963 +                    break;
   4.964 +                case 2:
   4.965 +                    phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
   4.966 +                    break;
   4.967 +                case 0:
   4.968 +                default:
   4.969 +                    phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
   4.970 +                    break;
   4.971 +                }
   4.972 +            }
   4.973 +            if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
   4.974 +                                              phy_data)))
   4.975 +                return ret_val;
   4.976 +
   4.977 +            /* set auto-master slave resolution settings */
   4.978 +            if(hw->autoneg) {
   4.979 +                e1000_ms_type phy_ms_setting = hw->master_slave;
   4.980 +
   4.981 +                if(hw->ffe_config_state == e1000_ffe_config_active)
   4.982 +                    hw->ffe_config_state = e1000_ffe_config_enabled;
   4.983 +
   4.984 +                if(hw->dsp_config_state == e1000_dsp_config_activated)
   4.985 +                    hw->dsp_config_state = e1000_dsp_config_enabled;
   4.986 +
   4.987 +                /* when autonegotiation advertisment is only 1000Mbps then we
   4.988 +                 * should disable SmartSpeed and enable Auto MasterSlave
   4.989 +                 * resolution as hardware default. */
   4.990 +                if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
   4.991 +                    /* Disable SmartSpeed */
   4.992 +                    if((ret_val = e1000_read_phy_reg(hw,
   4.993 +                                                    IGP01E1000_PHY_PORT_CONFIG,
   4.994 +                                                    &phy_data)))
   4.995 +                        return ret_val;
   4.996 +                    phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
   4.997 +                    if((ret_val = e1000_write_phy_reg(hw,
   4.998 +                                                     IGP01E1000_PHY_PORT_CONFIG,
   4.999 +                                                     phy_data)))
  4.1000 +                        return ret_val;
  4.1001 +                    /* Set auto Master/Slave resolution process */
  4.1002 +                    if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
  4.1003 +                                                     &phy_data)))
  4.1004 +                        return ret_val;
  4.1005 +                    phy_data &= ~CR_1000T_MS_ENABLE;
  4.1006 +                    if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
  4.1007 +                                                      phy_data)))
  4.1008 +                        return ret_val;
  4.1009 +                }
  4.1010 +
  4.1011 +                if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
  4.1012 +                                                 &phy_data)))
  4.1013 +                    return ret_val;
  4.1014 +
  4.1015 +                /* load defaults for future use */
  4.1016 +                hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
  4.1017 +                                            ((phy_data & CR_1000T_MS_VALUE) ?
  4.1018 +                                             e1000_ms_force_master :
  4.1019 +                                             e1000_ms_force_slave) :
  4.1020 +                                             e1000_ms_auto;
  4.1021 +
  4.1022 +                switch (phy_ms_setting) {
  4.1023 +                case e1000_ms_force_master:
  4.1024 +                    phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
  4.1025 +                    break;
  4.1026 +                case e1000_ms_force_slave:
  4.1027 +                    phy_data |= CR_1000T_MS_ENABLE;
  4.1028 +                    phy_data &= ~(CR_1000T_MS_VALUE);
  4.1029 +                    break;
  4.1030 +                case e1000_ms_auto:
  4.1031 +                    phy_data &= ~CR_1000T_MS_ENABLE;
  4.1032 +                default:
  4.1033 +                    break;
  4.1034 +                }
  4.1035 +                if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
  4.1036 +                                                  phy_data)))
  4.1037 +                    return ret_val;
  4.1038 +            }
  4.1039 +        } else {
  4.1040 +            /* Enable CRS on TX. This must be set for half-duplex operation. */
  4.1041 +            if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
  4.1042 +                                             &phy_data)))
  4.1043 +                return ret_val;
  4.1044 +
  4.1045 +            phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
  4.1046 +
  4.1047 +            /* Options:
  4.1048 +             *   MDI/MDI-X = 0 (default)
  4.1049 +             *   0 - Auto for all speeds
  4.1050 +             *   1 - MDI mode
  4.1051 +             *   2 - MDI-X mode
  4.1052 +             *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
  4.1053 +             */
  4.1054 +            phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
  4.1055 +
  4.1056 +            switch (hw->mdix) {
  4.1057 +            case 1:
  4.1058 +                phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
  4.1059 +                break;
  4.1060 +            case 2:
  4.1061 +                phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
  4.1062 +                break;
  4.1063 +            case 3:
  4.1064 +                phy_data |= M88E1000_PSCR_AUTO_X_1000T;
  4.1065 +                break;
  4.1066 +            case 0:
  4.1067 +            default:
  4.1068 +                phy_data |= M88E1000_PSCR_AUTO_X_MODE;
  4.1069 +                break;
  4.1070 +            }
  4.1071 +
  4.1072 +            /* Options:
  4.1073 +             *   disable_polarity_correction = 0 (default)
  4.1074 +             *       Automatic Correction for Reversed Cable Polarity
  4.1075 +             *   0 - Disabled
  4.1076 +             *   1 - Enabled
  4.1077 +             */
  4.1078 +            phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
  4.1079 +            if(hw->disable_polarity_correction == 1)
  4.1080 +                phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
  4.1081 +            if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
  4.1082 +                                              phy_data)))
  4.1083 +                return ret_val;
  4.1084 +
  4.1085 +            /* Force TX_CLK in the Extended PHY Specific Control Register
  4.1086 +             * to 25MHz clock.
  4.1087 +             */
  4.1088 +            if((ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
  4.1089 +                                             &phy_data)))
  4.1090 +                return ret_val;
  4.1091 +
  4.1092 +            phy_data |= M88E1000_EPSCR_TX_CLK_25;
  4.1093 +
  4.1094 +            if (hw->phy_revision < M88E1011_I_REV_4) {
  4.1095 +                /* Configure Master and Slave downshift values */
  4.1096 +                phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
  4.1097 +                              M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
  4.1098 +                phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
  4.1099 +                             M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
  4.1100 +                if((ret_val = e1000_write_phy_reg(hw,
  4.1101 +                                                  M88E1000_EXT_PHY_SPEC_CTRL,
  4.1102 +                                                  phy_data)))
  4.1103 +                    return ret_val;
  4.1104 +            }
  4.1105 +
  4.1106 +            /* SW Reset the PHY so all changes take effect */
  4.1107 +            if((ret_val = e1000_phy_reset(hw))) {
  4.1108 +                DEBUGOUT("Error Resetting the PHY\n");
  4.1109                  return ret_val;
  4.1110              }
  4.1111          }
  4.1112 -    } else {
  4.1113 -        DEBUGOUT("Forcing speed and duplex\n");
  4.1114 -        ret_val = e1000_phy_force_speed_duplex(hw);
  4.1115 -        if(ret_val < 0) {
  4.1116 -            DEBUGOUT("Error Forcing Speed and Duplex\n");
  4.1117 -            return ret_val;
  4.1118 +
  4.1119 +        /* Options:
  4.1120 +         *   autoneg = 1 (default)
  4.1121 +         *      PHY will advertise value(s) parsed from
  4.1122 +         *      autoneg_advertised and fc
  4.1123 +         *   autoneg = 0
  4.1124 +         *      PHY will be set to 10H, 10F, 100H, or 100F
  4.1125 +         *      depending on value parsed from forced_speed_duplex.
  4.1126 +         */
  4.1127 +
  4.1128 +        /* Is autoneg enabled?  This is enabled by default or by software
  4.1129 +         * override.  If so, call e1000_phy_setup_autoneg routine to parse the
  4.1130 +         * autoneg_advertised and fc options. If autoneg is NOT enabled, then
  4.1131 +         * the user should have provided a speed/duplex override.  If so, then
  4.1132 +         * call e1000_phy_force_speed_duplex to parse and set this up.
  4.1133 +         */
  4.1134 +        if(hw->autoneg) {
  4.1135 +            /* Perform some bounds checking on the hw->autoneg_advertised
  4.1136 +             * parameter.  If this variable is zero, then set it to the default.
  4.1137 +             */
  4.1138 +            hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
  4.1139 +
  4.1140 +            /* If autoneg_advertised is zero, we assume it was not defaulted
  4.1141 +             * by the calling code so we set to advertise full capability.
  4.1142 +             */
  4.1143 +            if(hw->autoneg_advertised == 0)
  4.1144 +                hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  4.1145 +
  4.1146 +            DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
  4.1147 +            if((ret_val = e1000_phy_setup_autoneg(hw))) {
  4.1148 +                DEBUGOUT("Error Setting up Auto-Negotiation\n");
  4.1149 +                return ret_val;
  4.1150 +            }
  4.1151 +            DEBUGOUT("Restarting Auto-Neg\n");
  4.1152 +
  4.1153 +            /* Restart auto-negotiation by setting the Auto Neg Enable bit and
  4.1154 +             * the Auto Neg Restart bit in the PHY control register.
  4.1155 +             */
  4.1156 +            if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data)))
  4.1157 +                return ret_val;
  4.1158 +
  4.1159 +            phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
  4.1160 +            if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data)))
  4.1161 +                return ret_val;
  4.1162 +
  4.1163 +            /* Does the user want to wait for Auto-Neg to complete here, or
  4.1164 +             * check at a later time (for example, callback routine).
  4.1165 +             */
  4.1166 +            if(hw->wait_autoneg_complete) {
  4.1167 +                if((ret_val = e1000_wait_autoneg(hw))) {
  4.1168 +                    DEBUGOUT("Error while waiting for autoneg to complete\n");
  4.1169 +                    return ret_val;
  4.1170 +                }
  4.1171 +            }
  4.1172 +            hw->get_link_status = TRUE;
  4.1173 +        } else {
  4.1174 +            DEBUGOUT("Forcing speed and duplex\n");
  4.1175 +            if((ret_val = e1000_phy_force_speed_duplex(hw))) {
  4.1176 +                DEBUGOUT("Error Forcing Speed and Duplex\n");
  4.1177 +                return ret_val;
  4.1178 +            }
  4.1179          }
  4.1180 -    }
  4.1181 +    } /* !hw->phy_reset_disable */
  4.1182  
  4.1183      /* Check link status. Wait up to 100 microseconds for link to become
  4.1184       * valid.
  4.1185       */
  4.1186      for(i = 0; i < 10; i++) {
  4.1187 -        if(e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  4.1188 -            DEBUGOUT("PHY Read Error\n");
  4.1189 -            return -E1000_ERR_PHY;
  4.1190 -        }
  4.1191 -        if(e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  4.1192 -            DEBUGOUT("PHY Read Error\n");
  4.1193 -            return -E1000_ERR_PHY;
  4.1194 -        }
  4.1195 +        if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
  4.1196 +            return ret_val;
  4.1197 +        if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
  4.1198 +            return ret_val;
  4.1199 +
  4.1200          if(phy_data & MII_SR_LINK_STATUS) {
  4.1201              /* We have link, so we need to finish the config process:
  4.1202               *   1) Set up the MAC to the current PHY speed/duplex
  4.1203 @@ -769,25 +1177,31 @@ e1000_setup_copper_link(struct e1000_hw 
  4.1204              if(hw->mac_type >= e1000_82544) {
  4.1205                  e1000_config_collision_dist(hw);
  4.1206              } else {
  4.1207 -                ret_val = e1000_config_mac_to_phy(hw);
  4.1208 -                if(ret_val < 0) {
  4.1209 +                if((ret_val = e1000_config_mac_to_phy(hw))) {
  4.1210                      DEBUGOUT("Error configuring MAC to PHY settings\n");
  4.1211                      return ret_val;
  4.1212 -                  }
  4.1213 +                }
  4.1214              }
  4.1215 -            ret_val = e1000_config_fc_after_link_up(hw);
  4.1216 -            if(ret_val < 0) {
  4.1217 +            if((ret_val = e1000_config_fc_after_link_up(hw))) {
  4.1218                  DEBUGOUT("Error Configuring Flow Control\n");
  4.1219                  return ret_val;
  4.1220              }
  4.1221              DEBUGOUT("Valid link established!!!\n");
  4.1222 -            return 0;
  4.1223 +
  4.1224 +            if(hw->phy_type == e1000_phy_igp) {
  4.1225 +                if((ret_val = e1000_config_dsp_after_link_change(hw, TRUE))) {
  4.1226 +                    DEBUGOUT("Error Configuring DSP after link up\n");
  4.1227 +                    return ret_val;
  4.1228 +                }
  4.1229 +            }
  4.1230 +            DEBUGOUT("Valid link established!!!\n");
  4.1231 +            return E1000_SUCCESS;
  4.1232          }
  4.1233 -        udelay(10);
  4.1234 +        usec_delay(10);
  4.1235      }
  4.1236  
  4.1237      DEBUGOUT("Unable to establish link!!!\n");
  4.1238 -    return 0;
  4.1239 +    return E1000_SUCCESS;
  4.1240  }
  4.1241  
  4.1242  /******************************************************************************
  4.1243 @@ -798,22 +1212,20 @@ e1000_setup_copper_link(struct e1000_hw 
  4.1244  int32_t
  4.1245  e1000_phy_setup_autoneg(struct e1000_hw *hw)
  4.1246  {
  4.1247 +    int32_t ret_val;
  4.1248      uint16_t mii_autoneg_adv_reg;
  4.1249      uint16_t mii_1000t_ctrl_reg;
  4.1250  
  4.1251      DEBUGFUNC("e1000_phy_setup_autoneg");
  4.1252  
  4.1253      /* Read the MII Auto-Neg Advertisement Register (Address 4). */
  4.1254 -    if(e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg) < 0) {
  4.1255 -        DEBUGOUT("PHY Read Error\n");
  4.1256 -        return -E1000_ERR_PHY;
  4.1257 -    }
  4.1258 +    if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
  4.1259 +                                     &mii_autoneg_adv_reg)))
  4.1260 +        return ret_val;
  4.1261  
  4.1262      /* Read the MII 1000Base-T Control Register (Address 9). */
  4.1263 -    if(e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg) < 0) {
  4.1264 -        DEBUGOUT("PHY Read Error\n");
  4.1265 -        return -E1000_ERR_PHY;
  4.1266 -    }
  4.1267 +    if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg)))
  4.1268 +        return ret_val;
  4.1269  
  4.1270      /* Need to parse both autoneg_advertised and fc and set up
  4.1271       * the appropriate PHY registers.  First we will parse for
  4.1272 @@ -919,18 +1331,16 @@ e1000_phy_setup_autoneg(struct e1000_hw 
  4.1273          return -E1000_ERR_CONFIG;
  4.1274      }
  4.1275  
  4.1276 -    if(e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg) < 0) {
  4.1277 -        DEBUGOUT("PHY Write Error\n");
  4.1278 -        return -E1000_ERR_PHY;
  4.1279 -    }
  4.1280 +    if((ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV,
  4.1281 +                                      mii_autoneg_adv_reg)))
  4.1282 +        return ret_val;
  4.1283  
  4.1284      DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
  4.1285  
  4.1286 -    if(e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg) < 0) {
  4.1287 -        DEBUGOUT("PHY Write Error\n");
  4.1288 -        return -E1000_ERR_PHY;
  4.1289 -    }
  4.1290 -    return 0;
  4.1291 +    if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg)))
  4.1292 +        return ret_val;
  4.1293 +
  4.1294 +    return E1000_SUCCESS;
  4.1295  }
  4.1296  
  4.1297  /******************************************************************************
  4.1298 @@ -966,10 +1376,8 @@ e1000_phy_force_speed_duplex(struct e100
  4.1299      ctrl &= ~E1000_CTRL_ASDE;
  4.1300  
  4.1301      /* Read the MII Control Register. */
  4.1302 -    if(e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg) < 0) {
  4.1303 -        DEBUGOUT("PHY Read Error\n");
  4.1304 -        return -E1000_ERR_PHY;
  4.1305 -    }
  4.1306 +    if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg)))
  4.1307 +        return ret_val;
  4.1308  
  4.1309      /* We need to disable autoneg in order to force link and duplex. */
  4.1310  
  4.1311 @@ -1014,30 +1422,44 @@ e1000_phy_force_speed_duplex(struct e100
  4.1312      /* Write the configured values back to the Device Control Reg. */
  4.1313      E1000_WRITE_REG(hw, CTRL, ctrl);
  4.1314  
  4.1315 -    if(e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) {
  4.1316 -        DEBUGOUT("PHY Read Error\n");
  4.1317 -        return -E1000_ERR_PHY;
  4.1318 +    if (hw->phy_type == e1000_phy_m88) {
  4.1319 +        if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
  4.1320 +                                         &phy_data)))
  4.1321 +            return ret_val;
  4.1322 +
  4.1323 +        /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
  4.1324 +         * forced whenever speed are duplex are forced.
  4.1325 +         */
  4.1326 +        phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
  4.1327 +        if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
  4.1328 +                                          phy_data)))
  4.1329 +            return ret_val;
  4.1330 +
  4.1331 +        DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
  4.1332 +
  4.1333 +        /* Need to reset the PHY or these changes will be ignored */
  4.1334 +        mii_ctrl_reg |= MII_CR_RESET;
  4.1335 +    } else {
  4.1336 +        /* Clear Auto-Crossover to force MDI manually.  IGP requires MDI
  4.1337 +         * forced whenever speed or duplex are forced.
  4.1338 +         */
  4.1339 +        if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
  4.1340 +                                         &phy_data)))
  4.1341 +            return ret_val;
  4.1342 +
  4.1343 +        phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
  4.1344 +        phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
  4.1345 +
  4.1346 +        if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
  4.1347 +                                          phy_data)))
  4.1348 +            return ret_val;
  4.1349      }
  4.1350  
  4.1351 -    /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
  4.1352 -     * forced whenever speed are duplex are forced.
  4.1353 -     */
  4.1354 -    phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
  4.1355 -    if(e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) {
  4.1356 -        DEBUGOUT("PHY Write Error\n");
  4.1357 -        return -E1000_ERR_PHY;
  4.1358 -    }
  4.1359 -    DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
  4.1360 -
  4.1361 -    /* Need to reset the PHY or these changes will be ignored */
  4.1362 -    mii_ctrl_reg |= MII_CR_RESET;
  4.1363 -
  4.1364      /* Write back the modified PHY MII control register. */
  4.1365 -    if(e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg) < 0) {
  4.1366 -        DEBUGOUT("PHY Write Error\n");
  4.1367 -        return -E1000_ERR_PHY;
  4.1368 -    }
  4.1369 -    udelay(1);
  4.1370 +    if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg)))
  4.1371 +        return ret_val;
  4.1372 +
  4.1373 +    usec_delay(1);
  4.1374  
  4.1375      /* The wait_autoneg_complete flag may be a little misleading here.
  4.1376       * Since we are forcing speed and duplex, Auto-Neg is not enabled.
  4.1377 @@ -1056,22 +1478,18 @@ e1000_phy_force_speed_duplex(struct e100
  4.1378              /* Read the MII Status Register and wait for Auto-Neg Complete bit
  4.1379               * to be set.
  4.1380               */
  4.1381 -            if(e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
  4.1382 -                DEBUGOUT("PHY Read Error\n");
  4.1383 -                return -E1000_ERR_PHY;
  4.1384 -            }
  4.1385 -            if(e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
  4.1386 -                DEBUGOUT("PHY Read Error\n");
  4.1387 -                return -E1000_ERR_PHY;
  4.1388 -            }
  4.1389 +            if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
  4.1390 +                return ret_val;
  4.1391 +
  4.1392 +            if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
  4.1393 +                return ret_val;
  4.1394 +
  4.1395              if(mii_status_reg & MII_SR_LINK_STATUS) break;
  4.1396              msec_delay(100);
  4.1397          }
  4.1398          if(i == 0) { /* We didn't get link */
  4.1399              /* Reset the DSP and wait again for link. */
  4.1400 -            
  4.1401 -            ret_val = e1000_phy_reset_dsp(hw);
  4.1402 -            if(ret_val < 0) {
  4.1403 +            if((ret_val = e1000_phy_reset_dsp(hw))) {
  4.1404                  DEBUGOUT("Error Resetting PHY DSP\n");
  4.1405                  return ret_val;
  4.1406              }
  4.1407 @@ -1083,44 +1501,42 @@ e1000_phy_force_speed_duplex(struct e100
  4.1408              /* Read the MII Status Register and wait for Auto-Neg Complete bit
  4.1409               * to be set.
  4.1410               */
  4.1411 -            if(e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
  4.1412 -                DEBUGOUT("PHY Read Error\n");
  4.1413 -                return -E1000_ERR_PHY;
  4.1414 -            }
  4.1415 -            if(e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
  4.1416 -                DEBUGOUT("PHY Read Error\n");
  4.1417 -                return -E1000_ERR_PHY;
  4.1418 -            }
  4.1419 +            if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
  4.1420 +                return ret_val;
  4.1421 +
  4.1422 +            if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
  4.1423 +                return ret_val;
  4.1424          }
  4.1425      }
  4.1426 -    
  4.1427 -    /* Because we reset the PHY above, we need to re-force TX_CLK in the
  4.1428 -     * Extended PHY Specific Control Register to 25MHz clock.  This value
  4.1429 -     * defaults back to a 2.5MHz clock when the PHY is reset.
  4.1430 -     */
  4.1431 -    if(e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data) < 0) {
  4.1432 -        DEBUGOUT("PHY Read Error\n");
  4.1433 -        return -E1000_ERR_PHY;
  4.1434 -    }
  4.1435 -    phy_data |= M88E1000_EPSCR_TX_CLK_25;
  4.1436 -    if(e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data) < 0) {
  4.1437 -        DEBUGOUT("PHY Write Error\n");
  4.1438 -        return -E1000_ERR_PHY;
  4.1439 +
  4.1440 +    if (hw->phy_type == e1000_phy_m88) {
  4.1441 +        /* Because we reset the PHY above, we need to re-force TX_CLK in the
  4.1442 +         * Extended PHY Specific Control Register to 25MHz clock.  This value
  4.1443 +         * defaults back to a 2.5MHz clock when the PHY is reset.
  4.1444 +         */
  4.1445 +        if((ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
  4.1446 +                                         &phy_data)))
  4.1447 +            return ret_val;
  4.1448 +
  4.1449 +        phy_data |= M88E1000_EPSCR_TX_CLK_25;
  4.1450 +        if((ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
  4.1451 +                                          phy_data)))
  4.1452 +            return ret_val;
  4.1453 +
  4.1454 +        /* In addition, because of the s/w reset above, we need to enable CRS on
  4.1455 +         * TX.  This must be set for both full and half duplex operation.
  4.1456 +         */
  4.1457 +        if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
  4.1458 +                                         &phy_data)))
  4.1459 +            return ret_val;
  4.1460 +
  4.1461 +        phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
  4.1462 +        if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
  4.1463 +                                          phy_data)))
  4.1464 +            return ret_val;
  4.1465 +
  4.1466      }
  4.1467 -
  4.1468 -    /* In addition, because of the s/w reset above, we need to enable CRS on
  4.1469 -     * TX.  This must be set for both full and half duplex operation.
  4.1470 -     */
  4.1471 -    if(e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0) {
  4.1472 -        DEBUGOUT("PHY Read Error\n");
  4.1473 -        return -E1000_ERR_PHY;
  4.1474 -    }
  4.1475 -    phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
  4.1476 -    if(e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data) < 0) {
  4.1477 -        DEBUGOUT("PHY Write Error\n");
  4.1478 -        return -E1000_ERR_PHY;
  4.1479 -    }
  4.1480 -    return 0;
  4.1481 +    return E1000_SUCCESS;
  4.1482  }
  4.1483  
  4.1484  /******************************************************************************
  4.1485 @@ -1136,6 +1552,8 @@ e1000_config_collision_dist(struct e1000
  4.1486  {
  4.1487      uint32_t tctl;
  4.1488  
  4.1489 +    DEBUGFUNC("e1000_config_collision_dist");
  4.1490 +
  4.1491      tctl = E1000_READ_REG(hw, TCTL);
  4.1492  
  4.1493      tctl &= ~E1000_TCTL_COLD;
  4.1494 @@ -1158,6 +1576,7 @@ static int32_t
  4.1495  e1000_config_mac_to_phy(struct e1000_hw *hw)
  4.1496  {
  4.1497      uint32_t ctrl;
  4.1498 +    int32_t ret_val;
  4.1499      uint16_t phy_data;
  4.1500  
  4.1501      DEBUGFUNC("e1000_config_mac_to_phy");
  4.1502 @@ -1172,30 +1591,51 @@ e1000_config_mac_to_phy(struct e1000_hw 
  4.1503      /* Set up duplex in the Device Control and Transmit Control
  4.1504       * registers depending on negotiated values.
  4.1505       */
  4.1506 -    if(e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
  4.1507 -        DEBUGOUT("PHY Read Error\n");
  4.1508 -        return -E1000_ERR_PHY;
  4.1509 +    if (hw->phy_type == e1000_phy_igp) {
  4.1510 +        if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
  4.1511 +                                         &phy_data)))
  4.1512 +            return ret_val;
  4.1513 +
  4.1514 +        if(phy_data & IGP01E1000_PSSR_FULL_DUPLEX) ctrl |= E1000_CTRL_FD;
  4.1515 +        else ctrl &= ~E1000_CTRL_FD;
  4.1516 +
  4.1517 +        e1000_config_collision_dist(hw);
  4.1518 +
  4.1519 +        /* Set up speed in the Device Control register depending on
  4.1520 +         * negotiated values.
  4.1521 +         */
  4.1522 +        if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
  4.1523 +           IGP01E1000_PSSR_SPEED_1000MBPS)
  4.1524 +            ctrl |= E1000_CTRL_SPD_1000;
  4.1525 +        else if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
  4.1526 +                IGP01E1000_PSSR_SPEED_100MBPS)
  4.1527 +            ctrl |= E1000_CTRL_SPD_100;
  4.1528 +    } else {
  4.1529 +        if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
  4.1530 +                                         &phy_data)))
  4.1531 +            return ret_val;
  4.1532 +
  4.1533 +        if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD;
  4.1534 +        else ctrl &= ~E1000_CTRL_FD;
  4.1535 +
  4.1536 +        e1000_config_collision_dist(hw);
  4.1537 +
  4.1538 +        /* Set up speed in the Device Control register depending on
  4.1539 +         * negotiated values.
  4.1540 +         */
  4.1541 +        if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
  4.1542 +            ctrl |= E1000_CTRL_SPD_1000;
  4.1543 +        else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
  4.1544 +            ctrl |= E1000_CTRL_SPD_100;
  4.1545      }
  4.1546 -    if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD;
  4.1547 -    else ctrl &= ~E1000_CTRL_FD;
  4.1548 -
  4.1549 -    e1000_config_collision_dist(hw);
  4.1550 -
  4.1551 -    /* Set up speed in the Device Control register depending on
  4.1552 -     * negotiated values.
  4.1553 -     */
  4.1554 -    if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
  4.1555 -        ctrl |= E1000_CTRL_SPD_1000;
  4.1556 -    else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
  4.1557 -        ctrl |= E1000_CTRL_SPD_100;
  4.1558      /* Write the configured values back to the Device Control Reg. */
  4.1559      E1000_WRITE_REG(hw, CTRL, ctrl);
  4.1560 -    return 0;
  4.1561 +    return E1000_SUCCESS;
  4.1562  }
  4.1563  
  4.1564  /******************************************************************************
  4.1565   * Forces the MAC's flow control settings.
  4.1566 - * 
  4.1567 + *
  4.1568   * hw - Struct containing variables accessed by shared code
  4.1569   *
  4.1570   * Sets the TFCE and RFCE bits in the device control register to reflect
  4.1571 @@ -1204,7 +1644,7 @@ e1000_config_mac_to_phy(struct e1000_hw 
  4.1572   * by the PHY rather than the MAC. Software must also configure these
  4.1573   * bits when link is forced on a fiber connection.
  4.1574   *****************************************************************************/
  4.1575 -static int32_t
  4.1576 +int32_t
  4.1577  e1000_force_mac_fc(struct e1000_hw *hw)
  4.1578  {
  4.1579      uint32_t ctrl;
  4.1580 @@ -1257,12 +1697,12 @@ e1000_force_mac_fc(struct e1000_hw *hw)
  4.1581          ctrl &= (~E1000_CTRL_TFCE);
  4.1582  
  4.1583      E1000_WRITE_REG(hw, CTRL, ctrl);
  4.1584 -    return 0;
  4.1585 +    return E1000_SUCCESS;
  4.1586  }
  4.1587  
  4.1588  /******************************************************************************
  4.1589   * Configures flow control settings after link is established
  4.1590 - * 
  4.1591 + *
  4.1592   * hw - Struct containing variables accessed by shared code
  4.1593   *
  4.1594   * Should be called immediately after a valid link has been established.
  4.1595 @@ -1288,9 +1728,9 @@ e1000_config_fc_after_link_up(struct e10
  4.1596       * configuration of the MAC to match the "fc" parameter.
  4.1597       */
  4.1598      if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
  4.1599 +       ((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed)) ||
  4.1600         ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
  4.1601 -        ret_val = e1000_force_mac_fc(hw);
  4.1602 -        if(ret_val < 0) {
  4.1603 +        if((ret_val = e1000_force_mac_fc(hw))) {
  4.1604              DEBUGOUT("Error forcing flow control settings\n");
  4.1605              return ret_val;
  4.1606          }
  4.1607 @@ -1306,14 +1746,10 @@ e1000_config_fc_after_link_up(struct e10
  4.1608           * has completed.  We read this twice because this reg has
  4.1609           * some "sticky" (latched) bits.
  4.1610           */
  4.1611 -        if(e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
  4.1612 -            DEBUGOUT("PHY Read Error \n");
  4.1613 -            return -E1000_ERR_PHY;
  4.1614 -        }
  4.1615 -        if(e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
  4.1616 -            DEBUGOUT("PHY Read Error \n");
  4.1617 -            return -E1000_ERR_PHY;
  4.1618 -        }
  4.1619 +        if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
  4.1620 +            return ret_val;
  4.1621 +        if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
  4.1622 +            return ret_val;
  4.1623  
  4.1624          if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
  4.1625              /* The AutoNeg process has completed, so we now need to
  4.1626 @@ -1322,14 +1758,12 @@ e1000_config_fc_after_link_up(struct e10
  4.1627               * Register (Address 5) to determine how flow control was
  4.1628               * negotiated.
  4.1629               */
  4.1630 -            if(e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
  4.1631 -                DEBUGOUT("PHY Read Error\n");
  4.1632 -                return -E1000_ERR_PHY;
  4.1633 -            }
  4.1634 -            if(e1000_read_phy_reg(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg) < 0) {
  4.1635 -                DEBUGOUT("PHY Read Error\n");
  4.1636 -                return -E1000_ERR_PHY;
  4.1637 -            }
  4.1638 +            if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
  4.1639 +                                             &mii_nway_adv_reg)))
  4.1640 +                return ret_val;
  4.1641 +            if((ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
  4.1642 +                                             &mii_nway_lp_ability_reg)))
  4.1643 +                return ret_val;
  4.1644  
  4.1645              /* Two bits in the Auto Negotiation Advertisement Register
  4.1646               * (Address 4) and two bits in the Auto Negotiation Base
  4.1647 @@ -1435,7 +1869,7 @@ e1000_config_fc_after_link_up(struct e10
  4.1648                      hw->original_fc == e1000_fc_tx_pause) {
  4.1649                  hw->fc = e1000_fc_none;
  4.1650                  DEBUGOUT("Flow Control = NONE.\r\n");
  4.1651 -            } else {
  4.1652 +            } else if(!hw->fc_strict_ieee) {
  4.1653                  hw->fc = e1000_fc_rx_pause;
  4.1654                  DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
  4.1655              }
  4.1656 @@ -1444,7 +1878,10 @@ e1000_config_fc_after_link_up(struct e10
  4.1657               * negotiated to HALF DUPLEX, flow control should not be
  4.1658               * enabled per IEEE 802.3 spec.
  4.1659               */
  4.1660 -            e1000_get_speed_and_duplex(hw, &speed, &duplex);
  4.1661 +            if((ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex))) {
  4.1662 +                DEBUGOUT("Error getting link speed and duplex\n");
  4.1663 +                return ret_val;
  4.1664 +            }
  4.1665  
  4.1666              if(duplex == HALF_DUPLEX)
  4.1667                  hw->fc = e1000_fc_none;
  4.1668 @@ -1452,16 +1889,15 @@ e1000_config_fc_after_link_up(struct e10
  4.1669              /* Now we call a subroutine to actually force the MAC
  4.1670               * controller to use the correct flow control settings.
  4.1671               */
  4.1672 -            ret_val = e1000_force_mac_fc(hw);
  4.1673 -            if(ret_val < 0) {
  4.1674 +            if((ret_val = e1000_force_mac_fc(hw))) {
  4.1675                  DEBUGOUT("Error forcing flow control settings\n");
  4.1676                  return ret_val;
  4.1677 -             }
  4.1678 +            }
  4.1679          } else {
  4.1680              DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
  4.1681          }
  4.1682      }
  4.1683 -    return 0;
  4.1684 +    return E1000_SUCCESS;
  4.1685  }
  4.1686  
  4.1687  /******************************************************************************
  4.1688 @@ -1478,19 +1914,19 @@ e1000_check_for_link(struct e1000_hw *hw
  4.1689      uint32_t ctrl;
  4.1690      uint32_t status;
  4.1691      uint32_t rctl;
  4.1692 -    uint32_t signal;
  4.1693 +    uint32_t signal = 0;
  4.1694      int32_t ret_val;
  4.1695      uint16_t phy_data;
  4.1696      uint16_t lp_capability;
  4.1697  
  4.1698      DEBUGFUNC("e1000_check_for_link");
  4.1699 -    
  4.1700 -    /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be 
  4.1701 -     * set when the optics detect a signal. On older adapters, it will be 
  4.1702 -     * cleared when there is a signal
  4.1703 +
  4.1704 +    /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
  4.1705 +     * set when the optics detect a signal. On older adapters, it will be
  4.1706 +     * cleared when there is a signal.  This applies to fiber media only.
  4.1707       */
  4.1708 -    if(hw->mac_type > e1000_82544) signal = E1000_CTRL_SWDPIN1;
  4.1709 -    else signal = 0;
  4.1710 +    if(hw->media_type == e1000_media_type_fiber)
  4.1711 +        signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
  4.1712  
  4.1713      ctrl = E1000_READ_REG(hw, CTRL);
  4.1714      status = E1000_READ_REG(hw, STATUS);
  4.1715 @@ -1508,19 +1944,20 @@ e1000_check_for_link(struct e1000_hw *hw
  4.1716           * of the PHY.
  4.1717           * Read the register twice since the link bit is sticky.
  4.1718           */
  4.1719 -        if(e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  4.1720 -            DEBUGOUT("PHY Read Error\n");
  4.1721 -            return -E1000_ERR_PHY;
  4.1722 -        }
  4.1723 -        if(e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  4.1724 -            DEBUGOUT("PHY Read Error\n");
  4.1725 -            return -E1000_ERR_PHY;
  4.1726 -        }
  4.1727 +        if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
  4.1728 +            return ret_val;
  4.1729 +        if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
  4.1730 +            return ret_val;
  4.1731  
  4.1732          if(phy_data & MII_SR_LINK_STATUS) {
  4.1733              hw->get_link_status = FALSE;
  4.1734 +            /* Check if there was DownShift, must be checked immediately after
  4.1735 +             * link-up */
  4.1736 +            e1000_check_downshift(hw);
  4.1737 +
  4.1738          } else {
  4.1739              /* No link detected */
  4.1740 +            e1000_config_dsp_after_link_change(hw, FALSE);
  4.1741              return 0;
  4.1742          }
  4.1743  
  4.1744 @@ -1529,6 +1966,9 @@ e1000_check_for_link(struct e1000_hw *hw
  4.1745           */
  4.1746          if(!hw->autoneg) return -E1000_ERR_CONFIG;
  4.1747  
  4.1748 +        /* optimize the dsp settings for the igp phy */
  4.1749 +        e1000_config_dsp_after_link_change(hw, TRUE);
  4.1750 +
  4.1751          /* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
  4.1752           * have Si on board that is 82544 or newer, Auto
  4.1753           * Speed Detection takes care of MAC speed/duplex
  4.1754 @@ -1540,19 +1980,17 @@ e1000_check_for_link(struct e1000_hw *hw
  4.1755          if(hw->mac_type >= e1000_82544)
  4.1756              e1000_config_collision_dist(hw);
  4.1757          else {
  4.1758 -            ret_val = e1000_config_mac_to_phy(hw);
  4.1759 -            if(ret_val < 0) {
  4.1760 +            if((ret_val = e1000_config_mac_to_phy(hw))) {
  4.1761                  DEBUGOUT("Error configuring MAC to PHY settings\n");
  4.1762                  return ret_val;
  4.1763              }
  4.1764          }
  4.1765  
  4.1766 -        /* Configure Flow Control now that Auto-Neg has completed. First, we 
  4.1767 +        /* Configure Flow Control now that Auto-Neg has completed. First, we
  4.1768           * need to restore the desired flow control settings because we may
  4.1769           * have had to re-autoneg with a different link partner.
  4.1770           */
  4.1771 -        ret_val = e1000_config_fc_after_link_up(hw);
  4.1772 -        if(ret_val < 0) {
  4.1773 +        if((ret_val = e1000_config_fc_after_link_up(hw))) {
  4.1774              DEBUGOUT("Error configuring flow control\n");
  4.1775              return ret_val;
  4.1776          }
  4.1777 @@ -1567,16 +2005,15 @@ e1000_check_for_link(struct e1000_hw *hw
  4.1778           * partner is TBI-based, and we turn on TBI Compatibility.
  4.1779           */
  4.1780          if(hw->tbi_compatibility_en) {
  4.1781 -            if(e1000_read_phy_reg(hw, PHY_LP_ABILITY, &lp_capability) < 0) {
  4.1782 -                DEBUGOUT("PHY Read Error\n");
  4.1783 -                return -E1000_ERR_PHY;
  4.1784 -            }
  4.1785 +            if((ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
  4.1786 +                                             &lp_capability)))
  4.1787 +                return ret_val;
  4.1788              if(lp_capability & (NWAY_LPAR_10T_HD_CAPS |
  4.1789                                  NWAY_LPAR_10T_FD_CAPS |
  4.1790                                  NWAY_LPAR_100TX_HD_CAPS |
  4.1791                                  NWAY_LPAR_100TX_FD_CAPS |
  4.1792                                  NWAY_LPAR_100T4_CAPS)) {
  4.1793 -                /* If our link partner advertises anything in addition to 
  4.1794 +                /* If our link partner advertises anything in addition to
  4.1795                   * gigabit, we do not need to enable TBI compatibility.
  4.1796                   */
  4.1797                  if(hw->tbi_compatibility_on) {
  4.1798 @@ -1627,8 +2064,7 @@ e1000_check_for_link(struct e1000_hw *hw
  4.1799          E1000_WRITE_REG(hw, CTRL, ctrl);
  4.1800  
  4.1801          /* Configure Flow Control after forcing link up. */
  4.1802 -        ret_val = e1000_config_fc_after_link_up(hw);
  4.1803 -        if(ret_val < 0) {
  4.1804 +        if((ret_val = e1000_config_fc_after_link_up(hw))) {
  4.1805              DEBUGOUT("Error configuring flow control\n");
  4.1806              return ret_val;
  4.1807          }
  4.1808 @@ -1645,7 +2081,7 @@ e1000_check_for_link(struct e1000_hw *hw
  4.1809          E1000_WRITE_REG(hw, TXCW, hw->txcw);
  4.1810          E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
  4.1811      }
  4.1812 -    return 0;
  4.1813 +    return E1000_SUCCESS;
  4.1814  }
  4.1815  
  4.1816  /******************************************************************************
  4.1817 @@ -1655,12 +2091,14 @@ e1000_check_for_link(struct e1000_hw *hw
  4.1818   * speed - Speed of the connection
  4.1819   * duplex - Duplex setting of the connection
  4.1820   *****************************************************************************/
  4.1821 -void
  4.1822 +int32_t
  4.1823  e1000_get_speed_and_duplex(struct e1000_hw *hw,
  4.1824                             uint16_t *speed,
  4.1825                             uint16_t *duplex)
  4.1826  {
  4.1827      uint32_t status;
  4.1828 +    int32_t ret_val;
  4.1829 +    uint16_t phy_data;
  4.1830  
  4.1831      DEBUGFUNC("e1000_get_speed_and_duplex");
  4.1832  
  4.1833 @@ -1689,6 +2127,27 @@ e1000_get_speed_and_duplex(struct e1000_
  4.1834          *speed = SPEED_1000;
  4.1835          *duplex = FULL_DUPLEX;
  4.1836      }
  4.1837 +
  4.1838 +    /* IGP01 PHY may advertise full duplex operation after speed downgrade even
  4.1839 +     * if it is operating at half duplex.  Here we set the duplex settings to
  4.1840 +     * match the duplex in the link partner's capabilities.
  4.1841 +     */
  4.1842 +    if(hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
  4.1843 +        if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data)))
  4.1844 +            return ret_val;
  4.1845 +
  4.1846 +        if(!(phy_data & NWAY_ER_LP_NWAY_CAPS))
  4.1847 +            *duplex = HALF_DUPLEX;
  4.1848 +        else {
  4.1849 +            if((ret_val == e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data)))
  4.1850 +                return ret_val;
  4.1851 +            if((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
  4.1852 +               (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
  4.1853 +                *duplex = HALF_DUPLEX;
  4.1854 +        }
  4.1855 +    }
  4.1856 +
  4.1857 +    return E1000_SUCCESS;
  4.1858  }
  4.1859  
  4.1860  /******************************************************************************
  4.1861 @@ -1699,6 +2158,7 @@ e1000_get_speed_and_duplex(struct e1000_
  4.1862  int32_t
  4.1863  e1000_wait_autoneg(struct e1000_hw *hw)
  4.1864  {
  4.1865 +    int32_t ret_val;
  4.1866      uint16_t i;
  4.1867      uint16_t phy_data;
  4.1868  
  4.1869 @@ -1710,20 +2170,16 @@ e1000_wait_autoneg(struct e1000_hw *hw)
  4.1870          /* Read the MII Status Register and wait for Auto-Neg
  4.1871           * Complete bit to be set.
  4.1872           */
  4.1873 -        if(e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  4.1874 -            DEBUGOUT("PHY Read Error\n");
  4.1875 -            return -E1000_ERR_PHY;
  4.1876 -        }
  4.1877 -        if(e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  4.1878 -            DEBUGOUT("PHY Read Error\n");
  4.1879 -            return -E1000_ERR_PHY;
  4.1880 -        }
  4.1881 +        if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
  4.1882 +            return ret_val;
  4.1883 +        if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
  4.1884 +            return ret_val;
  4.1885          if(phy_data & MII_SR_AUTONEG_COMPLETE) {
  4.1886 -            return 0;
  4.1887 +            return E1000_SUCCESS;
  4.1888          }
  4.1889          msec_delay(100);
  4.1890      }
  4.1891 -    return 0;
  4.1892 +    return E1000_SUCCESS;
  4.1893  }
  4.1894  
  4.1895  /******************************************************************************
  4.1896 @@ -1737,11 +2193,11 @@ e1000_raise_mdi_clk(struct e1000_hw *hw,
  4.1897                      uint32_t *ctrl)
  4.1898  {
  4.1899      /* Raise the clock input to the Management Data Clock (by setting the MDC
  4.1900 -     * bit), and then delay 2 microseconds.
  4.1901 +     * bit), and then delay 10 microseconds.
  4.1902       */
  4.1903      E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
  4.1904      E1000_WRITE_FLUSH(hw);
  4.1905 -    udelay(2);
  4.1906 +    usec_delay(10);
  4.1907  }
  4.1908  
  4.1909  /******************************************************************************
  4.1910 @@ -1755,11 +2211,11 @@ e1000_lower_mdi_clk(struct e1000_hw *hw,
  4.1911                      uint32_t *ctrl)
  4.1912  {
  4.1913      /* Lower the clock input to the Management Data Clock (by clearing the MDC
  4.1914 -     * bit), and then delay 2 microseconds.
  4.1915 +     * bit), and then delay 10 microseconds.
  4.1916       */
  4.1917      E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
  4.1918      E1000_WRITE_FLUSH(hw);
  4.1919 -    udelay(2);
  4.1920 +    usec_delay(10);
  4.1921  }
  4.1922  
  4.1923  /******************************************************************************
  4.1924 @@ -1780,7 +2236,7 @@ e1000_shift_out_mdi_bits(struct e1000_hw
  4.1925      uint32_t mask;
  4.1926  
  4.1927      /* We need to shift "count" number of bits out to the PHY. So, the value
  4.1928 -     * in the "data" parameter will be shifted out to the PHY one bit at a 
  4.1929 +     * in the "data" parameter will be shifted out to the PHY one bit at a
  4.1930       * time. In order to do this, "data" must be broken down into bits.
  4.1931       */
  4.1932      mask = 0x01;
  4.1933 @@ -1803,7 +2259,7 @@ e1000_shift_out_mdi_bits(struct e1000_hw
  4.1934          E1000_WRITE_REG(hw, CTRL, ctrl);
  4.1935          E1000_WRITE_FLUSH(hw);
  4.1936  
  4.1937 -        udelay(2);
  4.1938 +        usec_delay(10);
  4.1939  
  4.1940          e1000_raise_mdi_clk(hw, &ctrl);
  4.1941          e1000_lower_mdi_clk(hw, &ctrl);
  4.1942 @@ -1817,7 +2273,7 @@ e1000_shift_out_mdi_bits(struct e1000_hw
  4.1943  *
  4.1944  * hw - Struct containing variables accessed by shared code
  4.1945  *
  4.1946 -* Bits are shifted in in MSB to LSB order. 
  4.1947 +* Bits are shifted in in MSB to LSB order.
  4.1948  ******************************************************************************/
  4.1949  static uint16_t
  4.1950  e1000_shift_in_mdi_bits(struct e1000_hw *hw)
  4.1951 @@ -1832,7 +2288,7 @@ e1000_shift_in_mdi_bits(struct e1000_hw 
  4.1952       * These two bits are ignored by us and thrown away. Bits are "shifted in"
  4.1953       * by raising the input to the Management Data Clock (setting the MDC bit),
  4.1954       * and then reading the value of the MDIO bit.
  4.1955 -     */ 
  4.1956 +     */
  4.1957      ctrl = E1000_READ_REG(hw, CTRL);
  4.1958  
  4.1959      /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
  4.1960 @@ -1865,8 +2321,8 @@ e1000_shift_in_mdi_bits(struct e1000_hw 
  4.1961  }
  4.1962  
  4.1963  /*****************************************************************************
  4.1964 -* Reads the value from a PHY register
  4.1965 -*
  4.1966 +* Reads the value from a PHY register, if the value is on a specific non zero
  4.1967 +* page, sets the page first.
  4.1968  * hw - Struct containing variables accessed by shared code
  4.1969  * reg_addr - address of the PHY register to read
  4.1970  ******************************************************************************/
  4.1971 @@ -1875,11 +2331,33 @@ e1000_read_phy_reg(struct e1000_hw *hw,
  4.1972                     uint32_t reg_addr,
  4.1973                     uint16_t *phy_data)
  4.1974  {
  4.1975 +    uint32_t ret_val;
  4.1976 +
  4.1977 +    DEBUGFUNC("e1000_read_phy_reg");
  4.1978 +
  4.1979 +    if(hw->phy_type == e1000_phy_igp &&
  4.1980 +       (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
  4.1981 +        if((ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
  4.1982 +                                             (uint16_t)reg_addr)))
  4.1983 +            return ret_val;
  4.1984 +    }
  4.1985 +
  4.1986 +    ret_val = e1000_read_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
  4.1987 +                                    phy_data);
  4.1988 +
  4.1989 +    return ret_val;
  4.1990 +}
  4.1991 +
  4.1992 +int32_t
  4.1993 +e1000_read_phy_reg_ex(struct e1000_hw *hw,
  4.1994 +                      uint32_t reg_addr,
  4.1995 +                      uint16_t *phy_data)
  4.1996 +{
  4.1997      uint32_t i;
  4.1998      uint32_t mdic = 0;
  4.1999      const uint32_t phy_addr = 1;
  4.2000  
  4.2001 -    DEBUGFUNC("XXXXe1000_read_phy_reg");
  4.2002 +    DEBUGFUNC("e1000_read_phy_reg_ex");
  4.2003  
  4.2004      if(reg_addr > MAX_PHY_REG_ADDRESS) {
  4.2005          DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
  4.2006 @@ -1892,14 +2370,14 @@ e1000_read_phy_reg(struct e1000_hw *hw,
  4.2007           * PHY to retrieve the desired data.
  4.2008           */
  4.2009          mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
  4.2010 -                (phy_addr << E1000_MDIC_PHY_SHIFT) | 
  4.2011 +                (phy_addr << E1000_MDIC_PHY_SHIFT) |
  4.2012                  (E1000_MDIC_OP_READ));
  4.2013  
  4.2014          E1000_WRITE_REG(hw, MDIC, mdic);
  4.2015  
  4.2016          /* Poll the ready bit to see if the MDI read completed */
  4.2017          for(i = 0; i < 64; i++) {
  4.2018 -            udelay(10);
  4.2019 +            usec_delay(50);
  4.2020              mdic = E1000_READ_REG(hw, MDIC);
  4.2021              if(mdic & E1000_MDIC_READY) break;
  4.2022          }
  4.2023 @@ -1930,7 +2408,7 @@ e1000_read_phy_reg(struct e1000_hw *hw,
  4.2024           * READ operation is performed.  These two bits are thrown away
  4.2025           * followed by a shift in of 16 bits which contains the desired data.
  4.2026           */
  4.2027 -        mdic = ((reg_addr) | (phy_addr << 5) | 
  4.2028 +        mdic = ((reg_addr) | (phy_addr << 5) |
  4.2029                  (PHY_OP_READ << 10) | (PHY_SOF << 12));
  4.2030  
  4.2031          e1000_shift_out_mdi_bits(hw, mdic, 14);
  4.2032 @@ -1941,7 +2419,7 @@ e1000_read_phy_reg(struct e1000_hw *hw,
  4.2033           */
  4.2034          *phy_data = e1000_shift_in_mdi_bits(hw);
  4.2035      }
  4.2036 -    return 0;
  4.2037 +    return E1000_SUCCESS;
  4.2038  }
  4.2039  
  4.2040  /******************************************************************************
  4.2041 @@ -1956,11 +2434,33 @@ e1000_write_phy_reg(struct e1000_hw *hw,
  4.2042                      uint32_t reg_addr,
  4.2043                      uint16_t phy_data)
  4.2044  {
  4.2045 +    uint32_t ret_val;
  4.2046 +
  4.2047 +    DEBUGFUNC("e1000_write_phy_reg");
  4.2048 +
  4.2049 +    if(hw->phy_type == e1000_phy_igp &&
  4.2050 +       (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
  4.2051 +        if((ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
  4.2052 +                                             (uint16_t)reg_addr)))
  4.2053 +            return ret_val;
  4.2054 +    }
  4.2055 +
  4.2056 +    ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
  4.2057 +                                     phy_data);
  4.2058 +
  4.2059 +    return ret_val;
  4.2060 +}
  4.2061 +
  4.2062 +int32_t
  4.2063 +e1000_write_phy_reg_ex(struct e1000_hw *hw,
  4.2064 +                    uint32_t reg_addr,
  4.2065 +                    uint16_t phy_data)
  4.2066 +{
  4.2067      uint32_t i;
  4.2068      uint32_t mdic = 0;
  4.2069      const uint32_t phy_addr = 1;
  4.2070  
  4.2071 -    DEBUGFUNC("e1000_write_phy_reg");
  4.2072 +    DEBUGFUNC("e1000_write_phy_reg_ex");
  4.2073  
  4.2074      if(reg_addr > MAX_PHY_REG_ADDRESS) {
  4.2075          DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
  4.2076 @@ -1974,14 +2474,14 @@ e1000_write_phy_reg(struct e1000_hw *hw,
  4.2077           */
  4.2078          mdic = (((uint32_t) phy_data) |
  4.2079                  (reg_addr << E1000_MDIC_REG_SHIFT) |
  4.2080 -                (phy_addr << E1000_MDIC_PHY_SHIFT) | 
  4.2081 +                (phy_addr << E1000_MDIC_PHY_SHIFT) |
  4.2082                  (E1000_MDIC_OP_WRITE));
  4.2083  
  4.2084          E1000_WRITE_REG(hw, MDIC, mdic);
  4.2085  
  4.2086          /* Poll the ready bit to see if the MDI read completed */
  4.2087          for(i = 0; i < 64; i++) {
  4.2088 -            udelay(10);
  4.2089 +            usec_delay(50);
  4.2090              mdic = E1000_READ_REG(hw, MDIC);
  4.2091              if(mdic & E1000_MDIC_READY) break;
  4.2092          }
  4.2093 @@ -1992,12 +2492,12 @@ e1000_write_phy_reg(struct e1000_hw *hw,
  4.2094      } else {
  4.2095          /* We'll need to use the SW defined pins to shift the write command
  4.2096           * out to the PHY. We first send a preamble to the PHY to signal the
  4.2097 -         * beginning of the MII instruction.  This is done by sending 32 
  4.2098 +         * beginning of the MII instruction.  This is done by sending 32
  4.2099           * consecutive "1" bits.
  4.2100           */
  4.2101          e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
  4.2102  
  4.2103 -        /* Now combine the remaining required fields that will indicate a 
  4.2104 +        /* Now combine the remaining required fields that will indicate a
  4.2105           * write operation. We use this method instead of calling the
  4.2106           * e1000_shift_out_mdi_bits routine for each field in the command. The
  4.2107           * format of a MII write instruction is as follows:
  4.2108 @@ -2010,7 +2510,8 @@ e1000_write_phy_reg(struct e1000_hw *hw,
  4.2109  
  4.2110          e1000_shift_out_mdi_bits(hw, mdic, 32);
  4.2111      }
  4.2112 -    return 0;
  4.2113 +
  4.2114 +    return E1000_SUCCESS;
  4.2115  }
  4.2116  
  4.2117  /******************************************************************************
  4.2118 @@ -2021,8 +2522,8 @@ e1000_write_phy_reg(struct e1000_hw *hw,
  4.2119  void
  4.2120  e1000_phy_hw_reset(struct e1000_hw *hw)
  4.2121  {
  4.2122 -    uint32_t ctrl;
  4.2123 -    uint32_t ctrl_ext;
  4.2124 +    uint32_t ctrl, ctrl_ext;
  4.2125 +    uint32_t led_ctrl;
  4.2126  
  4.2127      DEBUGFUNC("e1000_phy_hw_reset");
  4.2128  
  4.2129 @@ -2052,7 +2553,15 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
  4.2130          E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  4.2131          E1000_WRITE_FLUSH(hw);
  4.2132      }
  4.2133 -    udelay(150);
  4.2134 +    usec_delay(150);
  4.2135 +
  4.2136 +    if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
  4.2137 +        /* Configure activity LED after PHY reset */
  4.2138 +        led_ctrl = E1000_READ_REG(hw, LEDCTL);
  4.2139 +        led_ctrl &= IGP_ACTIVITY_LED_MASK;
  4.2140 +        led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
  4.2141 +        E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
  4.2142 +    }
  4.2143  }
  4.2144  
  4.2145  /******************************************************************************
  4.2146 @@ -2065,21 +2574,26 @@ e1000_phy_hw_reset(struct e1000_hw *hw)
  4.2147  int32_t
  4.2148  e1000_phy_reset(struct e1000_hw *hw)
  4.2149  {
  4.2150 +    int32_t ret_val;
  4.2151      uint16_t phy_data;
  4.2152  
  4.2153      DEBUGFUNC("e1000_phy_reset");
  4.2154  
  4.2155 -    if(e1000_read_phy_reg(hw, PHY_CTRL, &phy_data) < 0) {
  4.2156 -        DEBUGOUT("PHY Read Error\n");
  4.2157 -        return -E1000_ERR_PHY;
  4.2158 -    }
  4.2159 -    phy_data |= MII_CR_RESET;
  4.2160 -    if(e1000_write_phy_reg(hw, PHY_CTRL, phy_data) < 0) {
  4.2161 -        DEBUGOUT("PHY Write Error\n");
  4.2162 -        return -E1000_ERR_PHY;
  4.2163 -    }
  4.2164 -    udelay(1);
  4.2165 -    return 0;
  4.2166 +    if(hw->mac_type != e1000_82541_rev_2) {
  4.2167 +        if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data)))
  4.2168 +            return ret_val;
  4.2169 +
  4.2170 +        phy_data |= MII_CR_RESET;
  4.2171 +        if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data)))
  4.2172 +            return ret_val;
  4.2173 +
  4.2174 +        usec_delay(1);
  4.2175 +    } else e1000_phy_hw_reset(hw);
  4.2176 +
  4.2177 +    if(hw->phy_type == e1000_phy_igp)
  4.2178 +        e1000_phy_init_script(hw);
  4.2179 +
  4.2180 +    return E1000_SUCCESS;
  4.2181  }
  4.2182  
  4.2183  /******************************************************************************
  4.2184 @@ -2090,22 +2604,21 @@ e1000_phy_reset(struct e1000_hw *hw)
  4.2185  int32_t
  4.2186  e1000_detect_gig_phy(struct e1000_hw *hw)
  4.2187  {
  4.2188 +    int32_t phy_init_status, ret_val;
  4.2189      uint16_t phy_id_high, phy_id_low;
  4.2190      boolean_t match = FALSE;
  4.2191  
  4.2192      DEBUGFUNC("e1000_detect_gig_phy");
  4.2193  
  4.2194      /* Read the PHY ID Registers to identify which PHY is onboard. */
  4.2195 -    if(e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high) < 0) {
  4.2196 -        DEBUGOUT("PHY Read Error\n");
  4.2197 -        return -E1000_ERR_PHY;
  4.2198 -    }
  4.2199 +    if((ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high)))
  4.2200 +        return ret_val;
  4.2201 +
  4.2202      hw->phy_id = (uint32_t) (phy_id_high << 16);
  4.2203 -    udelay(2);
  4.2204 -    if(e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low) < 0) {
  4.2205 -        DEBUGOUT("PHY Read Error\n");
  4.2206 -        return -E1000_ERR_PHY;
  4.2207 -    }
  4.2208 +    usec_delay(20);
  4.2209 +    if((ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low)))
  4.2210 +        return ret_val;
  4.2211 +
  4.2212      hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
  4.2213      hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
  4.2214  
  4.2215 @@ -2118,16 +2631,26 @@ e1000_detect_gig_phy(struct e1000_hw *hw
  4.2216          break;
  4.2217      case e1000_82540:
  4.2218      case e1000_82545:
  4.2219 +    case e1000_82545_rev_3:
  4.2220      case e1000_82546:
  4.2221 +    case e1000_82546_rev_3:
  4.2222          if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
  4.2223          break;
  4.2224 +    case e1000_82541:
  4.2225 +    case e1000_82541_rev_2:
  4.2226 +    case e1000_82547:
  4.2227 +    case e1000_82547_rev_2:
  4.2228 +        if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
  4.2229 +        break;
  4.2230      default:
  4.2231          DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
  4.2232          return -E1000_ERR_CONFIG;
  4.2233      }
  4.2234 -    if(match) {
  4.2235 +    phy_init_status = e1000_set_phy_type(hw);
  4.2236 +
  4.2237 +    if ((match) && (phy_init_status == E1000_SUCCESS)) {
  4.2238          DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
  4.2239 -        return 0;
  4.2240 +        return E1000_SUCCESS;
  4.2241      }
  4.2242      DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
  4.2243      return -E1000_ERR_PHY;
  4.2244 @@ -2141,21 +2664,152 @@ e1000_detect_gig_phy(struct e1000_hw *hw
  4.2245  static int32_t
  4.2246  e1000_phy_reset_dsp(struct e1000_hw *hw)
  4.2247  {
  4.2248 -    int32_t ret_val = -E1000_ERR_PHY;
  4.2249 +    int32_t ret_val;
  4.2250      DEBUGFUNC("e1000_phy_reset_dsp");
  4.2251 -    
  4.2252 +
  4.2253      do {
  4.2254 -        if(e1000_write_phy_reg(hw, 29, 0x001d) < 0) break;
  4.2255 -        if(e1000_write_phy_reg(hw, 30, 0x00c1) < 0) break;
  4.2256 -        if(e1000_write_phy_reg(hw, 30, 0x0000) < 0) break;
  4.2257 -        ret_val = 0;
  4.2258 +        if((ret_val = e1000_write_phy_reg(hw, 29, 0x001d))) break;
  4.2259 +        if((ret_val = e1000_write_phy_reg(hw, 30, 0x00c1))) break;
  4.2260 +        if((ret_val = e1000_write_phy_reg(hw, 30, 0x0000))) break;
  4.2261 +        ret_val = E1000_SUCCESS;
  4.2262      } while(0);
  4.2263  
  4.2264 -    if(ret_val < 0) DEBUGOUT("PHY Write Error\n");
  4.2265      return ret_val;
  4.2266  }
  4.2267  
  4.2268  /******************************************************************************
  4.2269 +* Get PHY information from various PHY registers for igp PHY only.
  4.2270 +*
  4.2271 +* hw - Struct containing variables accessed by shared code
  4.2272 +* phy_info - PHY information structure
  4.2273 +******************************************************************************/
  4.2274 +int32_t
  4.2275 +e1000_phy_igp_get_info(struct e1000_hw *hw,
  4.2276 +                       struct e1000_phy_info *phy_info)
  4.2277 +{
  4.2278 +    int32_t ret_val;
  4.2279 +    uint16_t phy_data, polarity, min_length, max_length, average;
  4.2280 +
  4.2281 +    DEBUGFUNC("e1000_phy_igp_get_info");
  4.2282 +
  4.2283 +    /* The downshift status is checked only once, after link is established,
  4.2284 +     * and it stored in the hw->speed_downgraded parameter. */
  4.2285 +    phy_info->downshift = hw->speed_downgraded;
  4.2286 +
  4.2287 +    /* IGP01E1000 does not need to support it. */
  4.2288 +    phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
  4.2289 +
  4.2290 +    /* IGP01E1000 always correct polarity reversal */
  4.2291 +    phy_info->polarity_correction = e1000_polarity_reversal_enabled;
  4.2292 +
  4.2293 +    /* Check polarity status */
  4.2294 +    if((ret_val = e1000_check_polarity(hw, &polarity)))
  4.2295 +        return ret_val;
  4.2296 +
  4.2297 +    phy_info->cable_polarity = polarity;
  4.2298 +
  4.2299 +    if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
  4.2300 +                                     &phy_data)))
  4.2301 +        return ret_val;
  4.2302 +
  4.2303 +    phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >>
  4.2304 +                          IGP01E1000_PSSR_MDIX_SHIFT;
  4.2305 +
  4.2306 +    if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
  4.2307 +       IGP01E1000_PSSR_SPEED_1000MBPS) {
  4.2308 +        /* Local/Remote Receiver Information are only valid at 1000 Mbps */
  4.2309 +        if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data)))
  4.2310 +            return ret_val;
  4.2311 +
  4.2312 +        phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
  4.2313 +                             SR_1000T_LOCAL_RX_STATUS_SHIFT;
  4.2314 +        phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
  4.2315 +                              SR_1000T_REMOTE_RX_STATUS_SHIFT;
  4.2316 +
  4.2317 +        /* Get cable length */
  4.2318 +        if((ret_val = e1000_get_cable_length(hw, &min_length, &max_length)))
  4.2319 +            return ret_val;
  4.2320 +
  4.2321 +        /* transalte to old method */
  4.2322 +        average = (max_length + min_length) / 2;
  4.2323 +
  4.2324 +        if(average <= e1000_igp_cable_length_50)
  4.2325 +            phy_info->cable_length = e1000_cable_length_50;
  4.2326 +        else if(average <= e1000_igp_cable_length_80)
  4.2327 +            phy_info->cable_length = e1000_cable_length_50_80;
  4.2328 +        else if(average <= e1000_igp_cable_length_110)
  4.2329 +            phy_info->cable_length = e1000_cable_length_80_110;
  4.2330 +        else if(average <= e1000_igp_cable_length_140)
  4.2331 +            phy_info->cable_length = e1000_cable_length_110_140;
  4.2332 +        else
  4.2333 +            phy_info->cable_length = e1000_cable_length_140;
  4.2334 +    }
  4.2335 +
  4.2336 +    return E1000_SUCCESS;
  4.2337 +}
  4.2338 +
  4.2339 +/******************************************************************************
  4.2340 +* Get PHY information from various PHY registers fot m88 PHY only.
  4.2341 +*
  4.2342 +* hw - Struct containing variables accessed by shared code
  4.2343 +* phy_info - PHY information structure
  4.2344 +******************************************************************************/
  4.2345 +int32_t
  4.2346 +e1000_phy_m88_get_info(struct e1000_hw *hw,
  4.2347 +                       struct e1000_phy_info *phy_info)
  4.2348 +{
  4.2349 +    int32_t ret_val;
  4.2350 +    uint16_t phy_data, polarity;
  4.2351 +
  4.2352 +    DEBUGFUNC("e1000_phy_m88_get_info");
  4.2353 +
  4.2354 +    /* The downshift status is checked only once, after link is established,
  4.2355 +     * and it stored in the hw->speed_downgraded parameter. */
  4.2356 +    phy_info->downshift = hw->speed_downgraded;
  4.2357 +
  4.2358 +    if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data)))
  4.2359 +        return ret_val;
  4.2360 +
  4.2361 +    phy_info->extended_10bt_distance =
  4.2362 +        (phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
  4.2363 +        M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT;
  4.2364 +    phy_info->polarity_correction =
  4.2365 +        (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
  4.2366 +        M88E1000_PSCR_POLARITY_REVERSAL_SHIFT;
  4.2367 +
  4.2368 +    /* Check polarity status */
  4.2369 +    if((ret_val = e1000_check_polarity(hw, &polarity)))
  4.2370 +        return ret_val;
  4.2371 +
  4.2372 +    phy_info->cable_polarity = polarity;
  4.2373 +
  4.2374 +    if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data)))
  4.2375 +        return ret_val;
  4.2376 +
  4.2377 +    phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >>
  4.2378 +                          M88E1000_PSSR_MDIX_SHIFT;
  4.2379 +
  4.2380 +    if(phy_data & M88E1000_PSSR_1000MBS) {
  4.2381 +        /* Cable Length Estimation and Local/Remote Receiver Informatoion
  4.2382 +         * are only valid at 1000 Mbps
  4.2383 +         */
  4.2384 +        phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
  4.2385 +                                  M88E1000_PSSR_CABLE_LENGTH_SHIFT);
  4.2386 +
  4.2387 +        if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data)))
  4.2388 +            return ret_val;
  4.2389 +
  4.2390 +        phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
  4.2391 +                             SR_1000T_LOCAL_RX_STATUS_SHIFT;
  4.2392 +
  4.2393 +        phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
  4.2394 +                              SR_1000T_REMOTE_RX_STATUS_SHIFT;
  4.2395 +    }
  4.2396 +
  4.2397 +    return E1000_SUCCESS;
  4.2398 +}
  4.2399 +
  4.2400 +/******************************************************************************
  4.2401  * Get PHY information from various PHY registers
  4.2402  *
  4.2403  * hw - Struct containing variables accessed by shared code
  4.2404 @@ -2165,7 +2819,7 @@ int32_t
  4.2405  e1000_phy_get_info(struct e1000_hw *hw,
  4.2406                     struct e1000_phy_info *phy_info)
  4.2407  {
  4.2408 -    int32_t ret_val = -E1000_ERR_PHY;
  4.2409 +    int32_t ret_val;
  4.2410      uint16_t phy_data;
  4.2411  
  4.2412      DEBUGFUNC("e1000_phy_get_info");
  4.2413 @@ -2173,6 +2827,7 @@ e1000_phy_get_info(struct e1000_hw *hw,
  4.2414      phy_info->cable_length = e1000_cable_length_undefined;
  4.2415      phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
  4.2416      phy_info->cable_polarity = e1000_rev_polarity_undefined;
  4.2417 +    phy_info->downshift = e1000_downshift_undefined;
  4.2418      phy_info->polarity_correction = e1000_polarity_reversal_undefined;
  4.2419      phy_info->mdix_mode = e1000_auto_x_mode_undefined;
  4.2420      phy_info->local_rx = e1000_1000t_rx_status_undefined;
  4.2421 @@ -2183,47 +2838,21 @@ e1000_phy_get_info(struct e1000_hw *hw,
  4.2422          return -E1000_ERR_CONFIG;
  4.2423      }
  4.2424  
  4.2425 -    do {
  4.2426 -        if(e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) break;
  4.2427 -        if(e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) break;
  4.2428 -        if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
  4.2429 -            DEBUGOUT("PHY info is only valid if link is up\n");
  4.2430 -            return -E1000_ERR_CONFIG;
  4.2431 -        }
  4.2432 -
  4.2433 -        if(e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data) < 0)
  4.2434 -            break;
  4.2435 -        phy_info->extended_10bt_distance =
  4.2436 -            (phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
  4.2437 -            M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT;
  4.2438 -        phy_info->polarity_correction =
  4.2439 -            (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
  4.2440 -            M88E1000_PSCR_POLARITY_REVERSAL_SHIFT;
  4.2441 -
  4.2442 -        if(e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0)
  4.2443 -            break;
  4.2444 -        phy_info->cable_polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
  4.2445 -            M88E1000_PSSR_REV_POLARITY_SHIFT;
  4.2446 -        phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >>
  4.2447 -            M88E1000_PSSR_MDIX_SHIFT;
  4.2448 -        if(phy_data & M88E1000_PSSR_1000MBS) {
  4.2449 -            /* Cable Length Estimation and Local/Remote Receiver Informatoion
  4.2450 -             * are only valid at 1000 Mbps
  4.2451 -             */
  4.2452 -            phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
  4.2453 -                                      M88E1000_PSSR_CABLE_LENGTH_SHIFT);
  4.2454 -            if(e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data) < 0) 
  4.2455 -                break;
  4.2456 -            phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
  4.2457 -                SR_1000T_LOCAL_RX_STATUS_SHIFT;
  4.2458 -            phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
  4.2459 -                SR_1000T_REMOTE_RX_STATUS_SHIFT;
  4.2460 -        }
  4.2461 -        ret_val = 0;
  4.2462 -    } while(0);
  4.2463 -
  4.2464 -    if(ret_val < 0) DEBUGOUT("PHY Read Error\n");
  4.2465 -    return ret_val;
  4.2466 +    if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
  4.2467 +        return ret_val;
  4.2468 +
  4.2469 +    if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
  4.2470 +        return ret_val;
  4.2471 +
  4.2472 +    if((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
  4.2473 +        DEBUGOUT("PHY info is only valid if link is up\n");
  4.2474 +        return -E1000_ERR_CONFIG;
  4.2475 +    }
  4.2476 +
  4.2477 +    if(hw->phy_type == e1000_phy_igp)
  4.2478 +        return e1000_phy_igp_get_info(hw, phy_info);
  4.2479 +    else
  4.2480 +        return e1000_phy_m88_get_info(hw, phy_info);
  4.2481  }
  4.2482  
  4.2483  int32_t
  4.2484 @@ -2236,7 +2865,125 @@ e1000_validate_mdi_setting(struct e1000_
  4.2485          hw->mdix = 1;
  4.2486          return -E1000_ERR_CONFIG;
  4.2487      }
  4.2488 -    return 0;
  4.2489 +    return E1000_SUCCESS;
  4.2490 +}
  4.2491 +
  4.2492 +
  4.2493 +/******************************************************************************
  4.2494 + * Sets up eeprom variables in the hw struct.  Must be called after mac_type
  4.2495 + * is configured.
  4.2496 + *
  4.2497 + * hw - Struct containing variables accessed by shared code
  4.2498 + *****************************************************************************/
  4.2499 +void
  4.2500 +e1000_init_eeprom_params(struct e1000_hw *hw)
  4.2501 +{
  4.2502 +    struct e1000_eeprom_info *eeprom = &hw->eeprom;
  4.2503 +    uint32_t eecd = E1000_READ_REG(hw, EECD);
  4.2504 +    uint16_t eeprom_size;
  4.2505 +
  4.2506 +    DEBUGFUNC("e1000_init_eeprom_params");
  4.2507 +
  4.2508 +    switch (hw->mac_type) {
  4.2509 +    case e1000_82542_rev2_0:
  4.2510 +    case e1000_82542_rev2_1:
  4.2511 +    case e1000_82543:
  4.2512 +    case e1000_82544:
  4.2513 +        eeprom->type = e1000_eeprom_microwire;
  4.2514 +        eeprom->word_size = 64;
  4.2515 +        eeprom->opcode_bits = 3;
  4.2516 +        eeprom->address_bits = 6;
  4.2517 +        eeprom->delay_usec = 50;
  4.2518 +        break;
  4.2519 +    case e1000_82540:
  4.2520 +    case e1000_82545:
  4.2521 +    case e1000_82545_rev_3:
  4.2522 +    case e1000_82546:
  4.2523 +    case e1000_82546_rev_3:
  4.2524 +        eeprom->type = e1000_eeprom_microwire;
  4.2525 +        eeprom->opcode_bits = 3;
  4.2526 +        eeprom->delay_usec = 50;
  4.2527 +        if(eecd & E1000_EECD_SIZE) {
  4.2528 +            eeprom->word_size = 256;
  4.2529 +            eeprom->address_bits = 8;
  4.2530 +        } else {
  4.2531 +            eeprom->word_size = 64;
  4.2532 +            eeprom->address_bits = 6;
  4.2533 +        }
  4.2534 +        break;
  4.2535 +    case e1000_82541:
  4.2536 +    case e1000_82541_rev_2:
  4.2537 +    case e1000_82547:
  4.2538 +    case e1000_82547_rev_2:
  4.2539 +        if (eecd & E1000_EECD_TYPE) {
  4.2540 +            eeprom->type = e1000_eeprom_spi;
  4.2541 +            eeprom->opcode_bits = 8;
  4.2542 +            eeprom->delay_usec = 1;
  4.2543 +            if (eecd & E1000_EECD_ADDR_BITS) {
  4.2544 +                eeprom->page_size = 32;
  4.2545 +                eeprom->address_bits = 16;
  4.2546 +            } else {
  4.2547 +                eeprom->page_size = 8;
  4.2548 +                eeprom->address_bits = 8;
  4.2549 +            }
  4.2550 +        } else {
  4.2551 +            eeprom->type = e1000_eeprom_microwire;
  4.2552 +            eeprom->opcode_bits = 3;
  4.2553 +            eeprom->delay_usec = 50;
  4.2554 +            if (eecd & E1000_EECD_ADDR_BITS) {
  4.2555 +                eeprom->word_size = 256;
  4.2556 +                eeprom->address_bits = 8;
  4.2557 +            } else {
  4.2558 +                eeprom->word_size = 64;
  4.2559 +                eeprom->address_bits = 6;
  4.2560 +            }
  4.2561 +        }
  4.2562 +        break;
  4.2563 +    default:
  4.2564 +        eeprom->type = e1000_eeprom_spi;
  4.2565 +        eeprom->opcode_bits = 8;
  4.2566 +        eeprom->delay_usec = 1;
  4.2567 +        if (eecd & E1000_EECD_ADDR_BITS) {
  4.2568 +            eeprom->page_size = 32;
  4.2569 +            eeprom->address_bits = 16;
  4.2570 +        } else {
  4.2571 +            eeprom->page_size = 8;
  4.2572 +            eeprom->address_bits = 8;
  4.2573 +        }
  4.2574 +        break;
  4.2575 +    }
  4.2576 +
  4.2577 +    if (eeprom->type == e1000_eeprom_spi) {
  4.2578 +        eeprom->word_size = 64;
  4.2579 +        if (e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size) == 0) {
  4.2580 +            eeprom_size &= EEPROM_SIZE_MASK;
  4.2581 +
  4.2582 +            switch (eeprom_size) {
  4.2583 +            case EEPROM_SIZE_16KB:
  4.2584 +                eeprom->word_size = 8192;
  4.2585 +                break;
  4.2586 +            case EEPROM_SIZE_8KB:
  4.2587 +                eeprom->word_size = 4096;
  4.2588 +                break;
  4.2589 +            case EEPROM_SIZE_4KB:
  4.2590 +                eeprom->word_size = 2048;
  4.2591 +                break;
  4.2592 +            case EEPROM_SIZE_2KB:
  4.2593 +                eeprom->word_size = 1024;
  4.2594 +                break;
  4.2595 +            case EEPROM_SIZE_1KB:
  4.2596 +                eeprom->word_size = 512;
  4.2597 +                break;
  4.2598 +            case EEPROM_SIZE_512B:
  4.2599 +                eeprom->word_size = 256;
  4.2600 +                break;
  4.2601 +            case EEPROM_SIZE_128B:
  4.2602 +            default:
  4.2603 +                eeprom->word_size = 64;
  4.2604 +                break;
  4.2605 +            }
  4.2606 +        }
  4.2607 +    }
  4.2608  }
  4.2609  
  4.2610  /******************************************************************************
  4.2611 @@ -2255,26 +3002,26 @@ e1000_raise_ee_clk(struct e1000_hw *hw,
  4.2612      *eecd = *eecd | E1000_EECD_SK;
  4.2613      E1000_WRITE_REG(hw, EECD, *eecd);
  4.2614      E1000_WRITE_FLUSH(hw);
  4.2615 -    udelay(50);
  4.2616 +    usec_delay(hw->eeprom.delay_usec);
  4.2617  }
  4.2618  
  4.2619  /******************************************************************************
  4.2620   * Lowers the EEPROM's clock input.
  4.2621   *
  4.2622 - * hw - Struct containing variables accessed by shared code 
  4.2623 + * hw - Struct containing variables accessed by shared code
  4.2624   * eecd - EECD's current value
  4.2625   *****************************************************************************/
  4.2626  static void
  4.2627  e1000_lower_ee_clk(struct e1000_hw *hw,
  4.2628                     uint32_t *eecd)
  4.2629  {
  4.2630 -    /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 
  4.2631 -     * wait 50 microseconds. 
  4.2632 +    /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
  4.2633 +     * wait 50 microseconds.
  4.2634       */
  4.2635      *eecd = *eecd & ~E1000_EECD_SK;
  4.2636      E1000_WRITE_REG(hw, EECD, *eecd);
  4.2637      E1000_WRITE_FLUSH(hw);
  4.2638 -    udelay(50);
  4.2639 +    usec_delay(hw->eeprom.delay_usec);
  4.2640  }
  4.2641  
  4.2642  /******************************************************************************
  4.2643 @@ -2289,16 +3036,21 @@ e1000_shift_out_ee_bits(struct e1000_hw 
  4.2644                          uint16_t data,
  4.2645                          uint16_t count)
  4.2646  {
  4.2647 +    struct e1000_eeprom_info *eeprom = &hw->eeprom;
  4.2648      uint32_t eecd;
  4.2649      uint32_t mask;
  4.2650  
  4.2651      /* We need to shift "count" bits out to the EEPROM. So, value in the
  4.2652       * "data" parameter will be shifted out to the EEPROM one bit at a time.
  4.2653 -     * In order to do this, "data" must be broken down into bits. 
  4.2654 +     * In order to do this, "data" must be broken down into bits.
  4.2655       */
  4.2656      mask = 0x01 << (count - 1);
  4.2657      eecd = E1000_READ_REG(hw, EECD);
  4.2658 -    eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
  4.2659 +    if (eeprom->type == e1000_eeprom_microwire) {
  4.2660 +        eecd &= ~E1000_EECD_DO;
  4.2661 +    } else if (eeprom->type == e1000_eeprom_spi) {
  4.2662 +        eecd |= E1000_EECD_DO;
  4.2663 +    }
  4.2664      do {
  4.2665          /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
  4.2666           * and then raising and then lowering the clock (the SK bit controls
  4.2667 @@ -2313,7 +3065,7 @@ e1000_shift_out_ee_bits(struct e1000_hw 
  4.2668          E1000_WRITE_REG(hw, EECD, eecd);
  4.2669          E1000_WRITE_FLUSH(hw);
  4.2670  
  4.2671 -        udelay(50);
  4.2672 +        usec_delay(eeprom->delay_usec);
  4.2673  
  4.2674          e1000_raise_ee_clk(hw, &eecd);
  4.2675          e1000_lower_ee_clk(hw, &eecd);
  4.2676 @@ -2333,7 +3085,8 @@ e1000_shift_out_ee_bits(struct e1000_hw 
  4.2677   * hw - Struct containing variables accessed by shared code
  4.2678   *****************************************************************************/
  4.2679  static uint16_t
  4.2680 -e1000_shift_in_ee_bits(struct e1000_hw *hw)
  4.2681 +e1000_shift_in_ee_bits(struct e1000_hw *hw,
  4.2682 +                       uint16_t count)
  4.2683  {
  4.2684      uint32_t eecd;
  4.2685      uint32_t i;
  4.2686 @@ -2351,7 +3104,7 @@ e1000_shift_in_ee_bits(struct e1000_hw *
  4.2687      eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
  4.2688      data = 0;
  4.2689  
  4.2690 -    for(i = 0; i < 16; i++) {
  4.2691 +    for(i = 0; i < count; i++) {
  4.2692          data = data << 1;
  4.2693          e1000_raise_ee_clk(hw, &eecd);
  4.2694  
  4.2695 @@ -2372,134 +3125,28 @@ e1000_shift_in_ee_bits(struct e1000_hw *
  4.2696   *
  4.2697   * hw - Struct containing variables accessed by shared code
  4.2698   *
  4.2699 - * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 
  4.2700 + * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
  4.2701   * function should be called before issuing a command to the EEPROM.
  4.2702   *****************************************************************************/
  4.2703 -static void
  4.2704 -e1000_setup_eeprom(struct e1000_hw *hw)
  4.2705 +static int32_t
  4.2706 +e1000_acquire_eeprom(struct e1000_hw *hw)
  4.2707  {
  4.2708 -    uint32_t eecd;
  4.2709 -
  4.2710 -    eecd = E1000_READ_REG(hw, EECD);
  4.2711 -
  4.2712 -    /* Clear SK and DI */
  4.2713 -    eecd &= ~(E1000_EECD_SK | E1000_EECD_DI);
  4.2714 -    E1000_WRITE_REG(hw, EECD, eecd);
  4.2715 -
  4.2716 -    /* Set CS */
  4.2717 -    eecd |= E1000_EECD_CS;
  4.2718 -    E1000_WRITE_REG(hw, EECD, eecd);
  4.2719 -}
  4.2720 -
  4.2721 -/******************************************************************************
  4.2722 - * Returns EEPROM to a "standby" state
  4.2723 - * 
  4.2724 - * hw - Struct containing variables accessed by shared code
  4.2725 - *****************************************************************************/
  4.2726 -static void
  4.2727 -e1000_standby_eeprom(struct e1000_hw *hw)
  4.2728 -{
  4.2729 -    uint32_t eecd;
  4.2730 +    struct e1000_eeprom_info *eeprom = &hw->eeprom;
  4.2731 +    uint32_t eecd, i=0;
  4.2732 +
  4.2733 +    DEBUGFUNC("e1000_acquire_eeprom");
  4.2734  
  4.2735      eecd = E1000_READ_REG(hw, EECD);
  4.2736  
  4.2737 -    /* Deselct EEPROM */
  4.2738 -    eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
  4.2739 -    E1000_WRITE_REG(hw, EECD, eecd);
  4.2740 -    E1000_WRITE_FLUSH(hw);
  4.2741 -    udelay(50);
  4.2742 -
  4.2743 -    /* Clock high */
  4.2744 -    eecd |= E1000_EECD_SK;
  4.2745 -    E1000_WRITE_REG(hw, EECD, eecd);
  4.2746 -    E1000_WRITE_FLUSH(hw);
  4.2747 -    udelay(50);
  4.2748 -
  4.2749 -    /* Select EEPROM */
  4.2750 -    eecd |= E1000_EECD_CS;
  4.2751 -    E1000_WRITE_REG(hw, EECD, eecd);
  4.2752 -    E1000_WRITE_FLUSH(hw);
  4.2753 -    udelay(50);
  4.2754 -
  4.2755 -    /* Clock low */
  4.2756 -    eecd &= ~E1000_EECD_SK;
  4.2757 -    E1000_WRITE_REG(hw, EECD, eecd);
  4.2758 -    E1000_WRITE_FLUSH(hw);
  4.2759 -    udelay(50);
  4.2760 -}
  4.2761 -
  4.2762 -/******************************************************************************
  4.2763 - * Raises then lowers the EEPROM's clock pin
  4.2764 - *
  4.2765 - * hw - Struct containing variables accessed by shared code
  4.2766 - *****************************************************************************/
  4.2767 -static void
  4.2768 -e1000_clock_eeprom(struct e1000_hw *hw)
  4.2769 -{
  4.2770 -    uint32_t eecd;
  4.2771 -
  4.2772 -    eecd = E1000_READ_REG(hw, EECD);
  4.2773 -
  4.2774 -    /* Rising edge of clock */
  4.2775 -    eecd |= E1000_EECD_SK;
  4.2776 -    E1000_WRITE_REG(hw, EECD, eecd);
  4.2777 -    E1000_WRITE_FLUSH(hw);
  4.2778 -    udelay(50);
  4.2779 -
  4.2780 -    /* Falling edge of clock */
  4.2781 -    eecd &= ~E1000_EECD_SK;
  4.2782 -    E1000_WRITE_REG(hw, EECD, eecd);
  4.2783 -    E1000_WRITE_FLUSH(hw);
  4.2784 -    udelay(50);
  4.2785 -}
  4.2786 -
  4.2787 -/******************************************************************************
  4.2788 - * Terminates a command by lowering the EEPROM's chip select pin
  4.2789 - *
  4.2790 - * hw - Struct containing variables accessed by shared code
  4.2791 - *****************************************************************************/
  4.2792 -static void
  4.2793 -e1000_cleanup_eeprom(struct e1000_hw *hw)
  4.2794 -{
  4.2795 -    uint32_t eecd;
  4.2796 -
  4.2797 -    eecd = E1000_READ_REG(hw, EECD);
  4.2798 -
  4.2799 -    eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
  4.2800 -
  4.2801 -    E1000_WRITE_REG(hw, EECD, eecd);
  4.2802 -
  4.2803 -    e1000_clock_eeprom(hw);
  4.2804 -}
  4.2805 -
  4.2806 -/******************************************************************************
  4.2807 - * Reads a 16 bit word from the EEPROM.
  4.2808 - *
  4.2809 - * hw - Struct containing variables accessed by shared code
  4.2810 - * offset - offset of  word in the EEPROM to read
  4.2811 - * data - word read from the EEPROM 
  4.2812 - *****************************************************************************/
  4.2813 -int32_t
  4.2814 -e1000_read_eeprom(struct e1000_hw *hw,
  4.2815 -                  uint16_t offset,
  4.2816 -                  uint16_t *data)
  4.2817 -{
  4.2818 -    uint32_t eecd;
  4.2819 -    uint32_t i = 0;
  4.2820 -    boolean_t large_eeprom = FALSE;
  4.2821 -
  4.2822 -    DEBUGFUNC("e1000_read_eeprom");
  4.2823 -
  4.2824      /* Request EEPROM Access */
  4.2825      if(hw->mac_type > e1000_82544) {
  4.2826 -        eecd = E1000_READ_REG(hw, EECD);
  4.2827 -        if(eecd & E1000_EECD_SIZE) large_eeprom = TRUE;
  4.2828          eecd |= E1000_EECD_REQ;
  4.2829          E1000_WRITE_REG(hw, EECD, eecd);
  4.2830          eecd = E1000_READ_REG(hw, EECD);
  4.2831 -        while((!(eecd & E1000_EECD_GNT)) && (i < 100)) {
  4.2832 +        while((!(eecd & E1000_EECD_GNT)) &&
  4.2833 +              (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
  4.2834              i++;
  4.2835 -            udelay(5);
  4.2836 +            usec_delay(5);
  4.2837              eecd = E1000_READ_REG(hw, EECD);
  4.2838          }
  4.2839          if(!(eecd & E1000_EECD_GNT)) {
  4.2840 @@ -2510,38 +3157,250 @@ e1000_read_eeprom(struct e1000_hw *hw,
  4.2841          }
  4.2842      }
  4.2843  
  4.2844 -    /*  Prepare the EEPROM for reading  */
  4.2845 -    e1000_setup_eeprom(hw);
  4.2846 -
  4.2847 -    /*  Send the READ command (opcode + addr)  */
  4.2848 -    e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE, 3);
  4.2849 -    if(large_eeprom) {
  4.2850 -        /* If we have a 256 word EEPROM, there are 8 address bits */
  4.2851 -        e1000_shift_out_ee_bits(hw, offset, 8);
  4.2852 -    } else {
  4.2853 -        /* If we have a 64 word EEPROM, there are 6 address bits */
  4.2854 -        e1000_shift_out_ee_bits(hw, offset, 6);
  4.2855 +    /* Setup EEPROM for Read/Write */
  4.2856 +
  4.2857 +    if (eeprom->type == e1000_eeprom_microwire) {
  4.2858 +        /* Clear SK and DI */
  4.2859 +        eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
  4.2860 +        E1000_WRITE_REG(hw, EECD, eecd);
  4.2861 +
  4.2862 +        /* Set CS */
  4.2863 +        eecd |= E1000_EECD_CS;
  4.2864 +        E1000_WRITE_REG(hw, EECD, eecd);
  4.2865 +    } else if (eeprom->type == e1000_eeprom_spi) {
  4.2866 +        /* Clear SK and CS */
  4.2867 +        eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
  4.2868 +        E1000_WRITE_REG(hw, EECD, eecd);
  4.2869 +        usec_delay(1);
  4.2870      }
  4.2871  
  4.2872 -    /* Read the data */
  4.2873 -    *data = e1000_shift_in_ee_bits(hw);
  4.2874 -
  4.2875 -    /* End this read operation */
  4.2876 -    e1000_standby_eeprom(hw);
  4.2877 +    return E1000_SUCCESS;
  4.2878 +}
  4.2879 +
  4.2880 +/******************************************************************************
  4.2881 + * Returns EEPROM to a "standby" state
  4.2882 + *
  4.2883 + * hw - Struct containing variables accessed by shared code
  4.2884 + *****************************************************************************/
  4.2885 +static void
  4.2886 +e1000_standby_eeprom(struct e1000_hw *hw)
  4.2887 +{
  4.2888 +    struct e1000_eeprom_info *eeprom = &hw->eeprom;
  4.2889 +    uint32_t eecd;
  4.2890 +
  4.2891 +    eecd = E1000_READ_REG(hw, EECD);
  4.2892 +
  4.2893 +    if(eeprom->type == e1000_eeprom_microwire) {
  4.2894 +        eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
  4.2895 +        E1000_WRITE_REG(hw, EECD, eecd);
  4.2896 +        E1000_WRITE_FLUSH(hw);
  4.2897 +        usec_delay(eeprom->delay_usec);
  4.2898 +
  4.2899 +        /* Clock high */
  4.2900 +        eecd |= E1000_EECD_SK;
  4.2901 +        E1000_WRITE_REG(hw, EECD, eecd);
  4.2902 +        E1000_WRITE_FLUSH(hw);
  4.2903 +        usec_delay(eeprom->delay_usec);
  4.2904 +
  4.2905 +        /* Select EEPROM */
  4.2906 +        eecd |= E1000_EECD_CS;
  4.2907 +        E1000_WRITE_REG(hw, EECD, eecd);
  4.2908 +        E1000_WRITE_FLUSH(hw);
  4.2909 +        usec_delay(eeprom->delay_usec);
  4.2910 +
  4.2911 +        /* Clock low */
  4.2912 +        eecd &= ~E1000_EECD_SK;
  4.2913 +        E1000_WRITE_REG(hw, EECD, eecd);
  4.2914 +        E1000_WRITE_FLUSH(hw);
  4.2915 +        usec_delay(eeprom->delay_usec);
  4.2916 +    } else if(eeprom->type == e1000_eeprom_spi) {
  4.2917 +        /* Toggle CS to flush commands */
  4.2918 +        eecd |= E1000_EECD_CS;
  4.2919 +        E1000_WRITE_REG(hw, EECD, eecd);
  4.2920 +        E1000_WRITE_FLUSH(hw);
  4.2921 +        usec_delay(eeprom->delay_usec);
  4.2922 +        eecd &= ~E1000_EECD_CS;
  4.2923 +        E1000_WRITE_REG(hw, EECD, eecd);
  4.2924 +        E1000_WRITE_FLUSH(hw);
  4.2925 +        usec_delay(eeprom->delay_usec);
  4.2926 +    }
  4.2927 +}
  4.2928 +
  4.2929 +/******************************************************************************
  4.2930 + * Terminates a command by inverting the EEPROM's chip select pin
  4.2931 + *
  4.2932 + * hw - Struct containing variables accessed by shared code
  4.2933 + *****************************************************************************/
  4.2934 +static void
  4.2935 +e1000_release_eeprom(struct e1000_hw *hw)
  4.2936 +{
  4.2937 +    uint32_t eecd;
  4.2938 +
  4.2939 +    DEBUGFUNC("e1000_release_eeprom");
  4.2940 +
  4.2941 +    eecd = E1000_READ_REG(hw, EECD);
  4.2942 +
  4.2943 +    if (hw->eeprom.type == e1000_eeprom_spi) {
  4.2944 +        eecd |= E1000_EECD_CS;  /* Pull CS high */
  4.2945 +        eecd &= ~E1000_EECD_SK; /* Lower SCK */
  4.2946 +
  4.2947 +        E1000_WRITE_REG(hw, EECD, eecd);
  4.2948 +
  4.2949 +        usec_delay(hw->eeprom.delay_usec);
  4.2950 +    } else if(hw->eeprom.type == e1000_eeprom_microwire) {
  4.2951 +        /* cleanup eeprom */
  4.2952 +
  4.2953 +        /* CS on Microwire is active-high */
  4.2954 +        eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
  4.2955 +
  4.2956 +        E1000_WRITE_REG(hw, EECD, eecd);
  4.2957 +
  4.2958 +        /* Rising edge of clock */
  4.2959 +        eecd |= E1000_EECD_SK;
  4.2960 +        E1000_WRITE_REG(hw, EECD, eecd);
  4.2961 +        E1000_WRITE_FLUSH(hw);
  4.2962 +        usec_delay(hw->eeprom.delay_usec);
  4.2963 +
  4.2964 +        /* Falling edge of clock */
  4.2965 +        eecd &= ~E1000_EECD_SK;
  4.2966 +        E1000_WRITE_REG(hw, EECD, eecd);
  4.2967 +        E1000_WRITE_FLUSH(hw);
  4.2968 +        usec_delay(hw->eeprom.delay_usec);
  4.2969 +    }
  4.2970  
  4.2971      /* Stop requesting EEPROM access */
  4.2972      if(hw->mac_type > e1000_82544) {
  4.2973 -        eecd = E1000_READ_REG(hw, EECD);
  4.2974          eecd &= ~E1000_EECD_REQ;
  4.2975          E1000_WRITE_REG(hw, EECD, eecd);
  4.2976      }
  4.2977 -
  4.2978 -    return 0;
  4.2979 +}
  4.2980 +
  4.2981 +/******************************************************************************
  4.2982 + * Reads a 16 bit word from the EEPROM.
  4.2983 + *
  4.2984 + * hw - Struct containing variables accessed by shared code
  4.2985 + *****************************************************************************/
  4.2986 +int32_t
  4.2987 +e1000_spi_eeprom_ready(struct e1000_hw *hw)
  4.2988 +{
  4.2989 +    uint16_t retry_count = 0;
  4.2990 +    uint8_t spi_stat_reg;
  4.2991 +
  4.2992 +    DEBUGFUNC("e1000_spi_eeprom_ready");
  4.2993 +
  4.2994 +    /* Read "Status Register" repeatedly until the LSB is cleared.  The
  4.2995 +     * EEPROM will signal that the command has been completed by clearing
  4.2996 +     * bit 0 of the internal status register.  If it's not cleared within
  4.2997 +     * 5 milliseconds, then error out.
  4.2998 +     */
  4.2999 +    retry_count = 0;
  4.3000 +    do {
  4.3001 +        e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
  4.3002 +                                hw->eeprom.opcode_bits);
  4.3003 +        spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
  4.3004 +        if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
  4.3005 +            break;
  4.3006 +
  4.3007 +        usec_delay(5);
  4.3008 +        retry_count += 5;
  4.3009 +
  4.3010 +    } while(retry_count < EEPROM_MAX_RETRY_SPI);
  4.3011 +
  4.3012 +    /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
  4.3013 +     * only 0-5mSec on 5V devices)
  4.3014 +     */
  4.3015 +    if(retry_count >= EEPROM_MAX_RETRY_SPI) {
  4.3016 +        DEBUGOUT("SPI EEPROM Status error\n");
  4.3017 +        return -E1000_ERR_EEPROM;
  4.3018 +    }
  4.3019 +
  4.3020 +    return E1000_SUCCESS;
  4.3021 +}
  4.3022 +
  4.3023 +/******************************************************************************
  4.3024 + * Reads a 16 bit word from the EEPROM.
  4.3025 + *
  4.3026 + * hw - Struct containing variables accessed by shared code
  4.3027 + * offset - offset of  word in the EEPROM to read
  4.3028 + * data - word read from the EEPROM
  4.3029 + * words - number of words to read
  4.3030 + *****************************************************************************/
  4.3031 +int32_t
  4.3032 +e1000_read_eeprom(struct e1000_hw *hw,
  4.3033 +                  uint16_t offset,
  4.3034 +                  uint16_t words,
  4.3035 +                  uint16_t *data)
  4.3036 +{
  4.3037 +    struct e1000_eeprom_info *eeprom = &hw->eeprom;
  4.3038 +    uint32_t i = 0;
  4.3039 +
  4.3040 +    DEBUGFUNC("e1000_read_eeprom");
  4.3041 +
  4.3042 +    /* A check for invalid values:  offset too large, too many words, and not
  4.3043 +     * enough words.
  4.3044 +     */
  4.3045 +    if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) ||
  4.3046 +       (words == 0)) {
  4.3047 +        DEBUGOUT("\"words\" parameter out of bounds\n");
  4.3048 +        return -E1000_ERR_EEPROM;
  4.3049 +    }
  4.3050 +
  4.3051 +    /* Prepare the EEPROM for reading  */
  4.3052 +    if(e1000_acquire_eeprom(hw) != E1000_SUCCESS)
  4.3053 +        return -E1000_ERR_EEPROM;
  4.3054 +
  4.3055 +    if(eeprom->type == e1000_eeprom_spi) {
  4.3056 +        uint16_t word_in;
  4.3057 +        uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
  4.3058 +
  4.3059 +        if(e1000_spi_eeprom_ready(hw)) {
  4.3060 +            e1000_release_eeprom(hw);
  4.3061 +            return -E1000_ERR_EEPROM;
  4.3062 +        }
  4.3063 +
  4.3064 +        e1000_standby_eeprom(hw);
  4.3065 +
  4.3066 +        /* Some SPI eeproms use the 8th address bit embedded in the opcode */
  4.3067 +        if((eeprom->address_bits == 8) && (offset >= 128))
  4.3068 +            read_opcode |= EEPROM_A8_OPCODE_SPI;
  4.3069 +
  4.3070 +        /* Send the READ command (opcode + addr)  */
  4.3071 +        e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
  4.3072 +        e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
  4.3073 +
  4.3074 +        /* Read the data.  The address of the eeprom internally increments with
  4.3075 +         * each byte (spi) being read, saving on the overhead of eeprom setup
  4.3076 +         * and tear-down.  The address counter will roll over if reading beyond
  4.3077 +         * the size of the eeprom, thus allowing the entire memory to be read
  4.3078 +         * starting from any offset. */
  4.3079 +        for (i = 0; i < words; i++) {
  4.3080 +            word_in = e1000_shift_in_ee_bits(hw, 16);
  4.3081 +            data[i] = (word_in >> 8) | (word_in << 8);
  4.3082 +        }
  4.3083 +    } else if(eeprom->type == e1000_eeprom_microwire) {
  4.3084 +        for (i = 0; i < words; i++) {
  4.3085 +            /* Send the READ command (opcode + addr)  */
  4.3086 +            e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
  4.3087 +                                    eeprom->opcode_bits);
  4.3088 +            e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
  4.3089 +                                    eeprom->address_bits);
  4.3090 +
  4.3091 +            /* Read the data.  For microwire, each word requires the overhead
  4.3092 +             * of eeprom setup and tear-down. */
  4.3093 +            data[i] = e1000_shift_in_ee_bits(hw, 16);
  4.3094 +            e1000_standby_eeprom(hw);
  4.3095 +        }
  4.3096 +    }
  4.3097 +
  4.3098 +    /* End this read operation */
  4.3099 +    e1000_release_eeprom(hw);
  4.3100 +
  4.3101 +    return E1000_SUCCESS;
  4.3102  }
  4.3103  
  4.3104  /******************************************************************************
  4.3105   * Verifies that the EEPROM has a valid checksum
  4.3106 - * 
  4.3107 + *
  4.3108   * hw - Struct containing variables accessed by shared code
  4.3109   *
  4.3110   * Reads the first 64 16 bit words of the EEPROM and sums the values read.
  4.3111 @@ -2557,17 +3416,17 @@ e1000_validate_eeprom_checksum(struct e1
  4.3112      DEBUGFUNC("e1000_validate_eeprom_checksum");
  4.3113  
  4.3114      for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
  4.3115 -        if(e1000_read_eeprom(hw, i, &eeprom_data) < 0) {
  4.3116 +        if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
  4.3117              DEBUGOUT("EEPROM Read Error\n");
  4.3118              return -E1000_ERR_EEPROM;
  4.3119          }
  4.3120          checksum += eeprom_data;
  4.3121      }
  4.3122  
  4.3123 -    if(checksum == (uint16_t) EEPROM_SUM) {
  4.3124 -        return 0;
  4.3125 -    } else {
  4.3126 -        DEBUGOUT("EEPROM Checksum Invalid\n");    
  4.3127 +    if(checksum == (uint16_t) EEPROM_SUM)
  4.3128 +        return E1000_SUCCESS;
  4.3129 +    else {
  4.3130 +        DEBUGOUT("EEPROM Checksum Invalid\n");
  4.3131          return -E1000_ERR_EEPROM;
  4.3132      }
  4.3133  }
  4.3134 @@ -2589,133 +3448,216 @@ e1000_update_eeprom_checksum(struct e100
  4.3135      DEBUGFUNC("e1000_update_eeprom_checksum");
  4.3136  
  4.3137      for(i = 0; i < EEPROM_CHECKSUM_REG; i++) {
  4.3138 -        if(e1000_read_eeprom(hw, i, &eeprom_data) < 0) {
  4.3139 +        if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
  4.3140              DEBUGOUT("EEPROM Read Error\n");
  4.3141              return -E1000_ERR_EEPROM;
  4.3142          }
  4.3143          checksum += eeprom_data;
  4.3144      }
  4.3145      checksum = (uint16_t) EEPROM_SUM - checksum;
  4.3146 -    if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, checksum) < 0) {
  4.3147 +    if(e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
  4.3148          DEBUGOUT("EEPROM Write Error\n");
  4.3149          return -E1000_ERR_EEPROM;
  4.3150      }
  4.3151 -    return 0;
  4.3152 +    return E1000_SUCCESS;
  4.3153  }
  4.3154  
  4.3155  /******************************************************************************
  4.3156 - * Writes a 16 bit word to a given offset in the EEPROM.
  4.3157 + * Parent function for writing words to the different EEPROM types.
  4.3158   *
  4.3159   * hw - Struct containing variables accessed by shared code
  4.3160   * offset - offset within the EEPROM to be written to
  4.3161 - * data - 16 bit word to be writen to the EEPROM
  4.3162 + * words - number of words to write
  4.3163 + * data - 16 bit word to be written to the EEPROM
  4.3164   *
  4.3165 - * If e1000_update_eeprom_checksum is not called after this function, the 
  4.3166 + * If e1000_update_eeprom_checksum is not called after this function, the
  4.3167   * EEPROM will most likely contain an invalid checksum.
  4.3168   *****************************************************************************/
  4.3169  int32_t
  4.3170  e1000_write_eeprom(struct e1000_hw *hw,
  4.3171                     uint16_t offset,
  4.3172 -                   uint16_t data)
  4.3173 +                   uint16_t words,
  4.3174 +                   uint16_t *data)
  4.3175  {
  4.3176 -    uint32_t eecd;
  4.3177 -    uint32_t i = 0;
  4.3178 +    struct e1000_eeprom_info *eeprom = &hw->eeprom;
  4.3179      int32_t status = 0;
  4.3180 -    boolean_t large_eeprom = FALSE;
  4.3181  
  4.3182      DEBUGFUNC("e1000_write_eeprom");
  4.3183  
  4.3184 -    /* Request EEPROM Access */
  4.3185 -    if(hw->mac_type > e1000_82544) {
  4.3186 -        eecd = E1000_READ_REG(hw, EECD);
  4.3187 -        if(eecd & E1000_EECD_SIZE) large_eeprom = TRUE;
  4.3188 -        eecd |= E1000_EECD_REQ;
  4.3189 -        E1000_WRITE_REG(hw, EECD, eecd);
  4.3190 -        eecd = E1000_READ_REG(hw, EECD);
  4.3191 -        while((!(eecd & E1000_EECD_GNT)) && (i < 100)) {
  4.3192 -            i++;
  4.3193 -            udelay(5);
  4.3194 -            eecd = E1000_READ_REG(hw, EECD);
  4.3195 -        }
  4.3196 -        if(!(eecd & E1000_EECD_GNT)) {
  4.3197 -            eecd &= ~E1000_EECD_REQ;
  4.3198 -            E1000_WRITE_REG(hw, EECD, eecd);
  4.3199 -            DEBUGOUT("Could not acquire EEPROM grant\n");
  4.3200 -            return -E1000_ERR_EEPROM;
  4.3201 -        }
  4.3202 +    /* A check for invalid values:  offset too large, too many words, and not
  4.3203 +     * enough words.
  4.3204 +     */
  4.3205 +    if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) ||
  4.3206 +       (words == 0)) {
  4.3207 +        DEBUGOUT("\"words\" parameter out of bounds\n");
  4.3208 +        return -E1000_ERR_EEPROM;
  4.3209      }
  4.3210  
  4.3211      /* Prepare the EEPROM for writing  */
  4.3212 -    e1000_setup_eeprom(hw);
  4.3213 -
  4.3214 -    /* Send the 9-bit (or 11-bit on large EEPROM) EWEN (write enable) command
  4.3215 -     * to the EEPROM (5-bit opcode plus 4/6-bit dummy). This puts the EEPROM
  4.3216 -     * into write/erase mode. 
  4.3217 +    if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
  4.3218 +        return -E1000_ERR_EEPROM;
  4.3219 +
  4.3220 +    if(eeprom->type == e1000_eeprom_microwire)
  4.3221 +        status = e1000_write_eeprom_microwire(hw, offset, words, data);
  4.3222 +    else
  4.3223 +        status = e1000_write_eeprom_spi(hw, offset, words, data);
  4.3224 +
  4.3225 +    /* Done with writing */
  4.3226 +    e1000_release_eeprom(hw);
  4.3227 +
  4.3228 +    return status;
  4.3229 +}
  4.3230 +
  4.3231 +/******************************************************************************
  4.3232 + * Writes a 16 bit word to a given offset in an SPI EEPROM.
  4.3233 + *
  4.3234 + * hw - Struct containing variables accessed by shared code
  4.3235 + * offset - offset within the EEPROM to be written to
  4.3236 + * words - number of words to write
  4.3237 + * data - pointer to array of 8 bit words to be written to the EEPROM
  4.3238 + *
  4.3239 + *****************************************************************************/
  4.3240 +int32_t
  4.3241 +e1000_write_eeprom_spi(struct e1000_hw *hw,
  4.3242 +                       uint16_t offset,
  4.3243 +                       uint16_t words,
  4.3244 +                       uint16_t *data)
  4.3245 +{
  4.3246 +    struct e1000_eeprom_info *eeprom = &hw->eeprom;
  4.3247 +    uint16_t widx = 0;
  4.3248 +
  4.3249 +    DEBUGFUNC("e1000_write_eeprom_spi");
  4.3250 +
  4.3251 +    while (widx < words) {
  4.3252 +        uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
  4.3253 +
  4.3254 +        if(e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
  4.3255 +
  4.3256 +        e1000_standby_eeprom(hw);
  4.3257 +
  4.3258 +        /*  Send the WRITE ENABLE command (8 bit opcode )  */
  4.3259 +        e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
  4.3260 +                                    eeprom->opcode_bits);
  4.3261 +
  4.3262 +        e1000_standby_eeprom(hw);
  4.3263 +
  4.3264 +        /* Some SPI eeproms use the 8th address bit embedded in the opcode */
  4.3265 +        if((eeprom->address_bits == 8) && (offset >= 128))
  4.3266 +            write_opcode |= EEPROM_A8_OPCODE_SPI;
  4.3267 +
  4.3268 +        /* Send the Write command (8-bit opcode + addr) */
  4.3269 +        e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
  4.3270 +
  4.3271 +        e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2),
  4.3272 +                                eeprom->address_bits);
  4.3273 +
  4.3274 +        /* Send the data */
  4.3275 +
  4.3276 +        /* Loop to allow for up to whole page write (32 bytes) of eeprom */
  4.3277 +        while (widx < words) {
  4.3278 +            uint16_t word_out = data[widx];
  4.3279 +            word_out = (word_out >> 8) | (word_out << 8);
  4.3280 +            e1000_shift_out_ee_bits(hw, word_out, 16);
  4.3281 +            widx++;
  4.3282 +
  4.3283 +            /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
  4.3284 +             * operation, while the smaller eeproms are capable of an 8-byte
  4.3285 +             * PAGE WRITE operation.  Break the inner loop to pass new address
  4.3286 +             */
  4.3287 +            if((((offset + widx)*2) % eeprom->page_size) == 0) {
  4.3288 +                e1000_standby_eeprom(hw);
  4.3289 +                break;
  4.3290 +            }
  4.3291 +        }
  4.3292 +    }
  4.3293 +
  4.3294 +    return E1000_SUCCESS;
  4.3295 +}
  4.3296 +
  4.3297 +/******************************************************************************
  4.3298 + * Writes a 16 bit word to a given offset in a Microwire EEPROM.
  4.3299 + *
  4.3300 + * hw - Struct containing variables accessed by shared code
  4.3301 + * offset - offset within the EEPROM to be written to
  4.3302 + * words - number of words to write
  4.3303 + * data - pointer to array of 16 bit words to be written to the EEPROM
  4.3304 + *
  4.3305 + *****************************************************************************/
  4.3306 +int32_t
  4.3307 +e1000_write_eeprom_microwire(struct e1000_hw *hw,
  4.3308 +                             uint16_t offset,
  4.3309 +                             uint16_t words,
  4.3310 +                             uint16_t *data)
  4.3311 +{
  4.3312 +    struct e1000_eeprom_info *eeprom = &hw->eeprom;
  4.3313 +    uint32_t eecd;
  4.3314 +    uint16_t words_written = 0;
  4.3315 +    uint16_t i = 0;
  4.3316 +
  4.3317 +    DEBUGFUNC("e1000_write_eeprom_microwire");
  4.3318 +
  4.3319 +    /* Send the write enable command to the EEPROM (3-bit opcode plus
  4.3320 +     * 6/8-bit dummy address beginning with 11).  It's less work to include
  4.3321 +     * the 11 of the dummy address as part of the opcode than it is to shift
  4.3322 +     * it over the correct number of bits for the address.  This puts the
  4.3323 +     * EEPROM into write/erase mode.
  4.3324       */
  4.3325 -    e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE, 5);
  4.3326 -    if(large_eeprom) 
  4.3327 -        e1000_shift_out_ee_bits(hw, 0, 6);
  4.3328 -    else
  4.3329 -        e1000_shift_out_ee_bits(hw, 0, 4);
  4.3330 +    e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
  4.3331 +                            (uint16_t)(eeprom->opcode_bits + 2));
  4.3332 +
  4.3333 +    e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
  4.3334  
  4.3335      /* Prepare the EEPROM */
  4.3336      e1000_standby_eeprom(hw);
  4.3337  
  4.3338 -    /* Send the Write command (3-bit opcode + addr) */
  4.3339 -    e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE, 3);
  4.3340 -    if(large_eeprom) 
  4.3341 -        /* If we have a 256 word EEPROM, there are 8 address bits */
  4.3342 -        e1000_shift_out_ee_bits(hw, offset, 8);
  4.3343 -    else
  4.3344 -        /* If we have a 64 word EEPROM, there are 6 address bits */
  4.3345 -        e1000_shift_out_ee_bits(hw, offset, 6);
  4.3346 -
  4.3347 -    /* Send the data */
  4.3348 -    e1000_shift_out_ee_bits(hw, data, 16);
  4.3349 -
  4.3350 -    /* Toggle the CS line.  This in effect tells to EEPROM to actually execute 
  4.3351 -     * the command in question.
  4.3352 -     */
  4.3353 -    e1000_standby_eeprom(hw);
  4.3354 -
  4.3355 -    /* Now read DO repeatedly until is high (equal to '1').  The EEEPROM will
  4.3356 -     * signal that the command has been completed by raising the DO signal.
  4.3357 -     * If DO does not go high in 10 milliseconds, then error out.
  4.3358 -     */
  4.3359 -    for(i = 0; i < 200; i++) {
  4.3360 -        eecd = E1000_READ_REG(hw, EECD);
  4.3361 -        if(eecd & E1000_EECD_DO) break;
  4.3362 -        udelay(50);
  4.3363 +    while (words_written < words) {
  4.3364 +        /* Send the Write command (3-bit opcode + addr) */
  4.3365 +        e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
  4.3366 +                                eeprom->opcode_bits);
  4.3367 +
  4.3368 +        e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written),
  4.3369 +                                eeprom->address_bits);
  4.3370 +
  4.3371 +        /* Send the data */
  4.3372 +        e1000_shift_out_ee_bits(hw, data[words_written], 16);
  4.3373 +
  4.3374 +        /* Toggle the CS line.  This in effect tells the EEPROM to execute
  4.3375 +         * the previous command.
  4.3376 +         */
  4.3377 +        e1000_standby_eeprom(hw);
  4.3378 +
  4.3379 +        /* Read DO repeatedly until it is high (equal to '1').  The EEPROM will
  4.3380 +         * signal that the command has been completed by raising the DO signal.
  4.3381 +         * If DO does not go high in 10 milliseconds, then error out.
  4.3382 +         */
  4.3383 +        for(i = 0; i < 200; i++) {
  4.3384 +            eecd = E1000_READ_REG(hw, EECD);
  4.3385 +            if(eecd & E1000_EECD_DO) break;
  4.3386 +            usec_delay(50);
  4.3387 +        }
  4.3388 +        if(i == 200) {
  4.3389 +            DEBUGOUT("EEPROM Write did not complete\n");
  4.3390 +            return -E1000_ERR_EEPROM;
  4.3391 +        }
  4.3392 +
  4.3393 +        /* Recover from write */
  4.3394 +        e1000_standby_eeprom(hw);
  4.3395 +
  4.3396 +        words_written++;
  4.3397      }
  4.3398 -    if(i == 200) {
  4.3399 -        DEBUGOUT("EEPROM Write did not complete\n");
  4.3400 -        status = -E1000_ERR_EEPROM;
  4.3401 -    }
  4.3402 -
  4.3403 -    /* Recover from write */
  4.3404 -    e1000_standby_eeprom(hw);
  4.3405 -
  4.3406 -    /* Send the 9-bit (or 11-bit on large EEPROM) EWDS (write disable) command
  4.3407 -     * to the EEPROM (5-bit opcode plus 4/6-bit dummy). This takes the EEPROM
  4.3408 -     * out of write/erase mode.
  4.3409 +
  4.3410 +    /* Send the write disable command to the EEPROM (3-bit opcode plus
  4.3411 +     * 6/8-bit dummy address beginning with 10).  It's less work to include
  4.3412 +     * the 10 of the dummy address as part of the opcode than it is to shift
  4.3413 +     * it over the correct number of bits for the address.  This takes the
  4.3414 +     * EEPROM out of write/erase mode.
  4.3415       */
  4.3416 -    e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE, 5);
  4.3417 -    if(large_eeprom) 
  4.3418 -        e1000_shift_out_ee_bits(hw, 0, 6);
  4.3419 -    else
  4.3420 -        e1000_shift_out_ee_bits(hw, 0, 4);
  4.3421 -
  4.3422 -    /* Done with writing */
  4.3423 -    e1000_cleanup_eeprom(hw);
  4.3424 -
  4.3425 -    /* Stop requesting EEPROM access */
  4.3426 -    if(hw->mac_type > e1000_82544) {
  4.3427 -        eecd = E1000_READ_REG(hw, EECD);
  4.3428 -        eecd &= ~E1000_EECD_REQ;
  4.3429 -        E1000_WRITE_REG(hw, EECD, eecd);
  4.3430 -    }
  4.3431 -
  4.3432 -    return status;
  4.3433 +    e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
  4.3434 +                            (uint16_t)(eeprom->opcode_bits + 2));
  4.3435 +
  4.3436 +    e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
  4.3437 +
  4.3438 +    return E1000_SUCCESS;
  4.3439  }
  4.3440  
  4.3441  /******************************************************************************
  4.3442 @@ -2734,7 +3676,7 @@ e1000_read_part_num(struct e1000_hw *hw,
  4.3443      DEBUGFUNC("e1000_read_part_num");
  4.3444  
  4.3445      /* Get word 0 from EEPROM */
  4.3446 -    if(e1000_read_eeprom(hw, offset, &eeprom_data) < 0) {
  4.3447 +    if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
  4.3448          DEBUGOUT("EEPROM Read Error\n");
  4.3449          return -E1000_ERR_EEPROM;
  4.3450      }
  4.3451 @@ -2742,14 +3684,14 @@ e1000_read_part_num(struct e1000_hw *hw,
  4.3452      *part_num = (uint32_t) (eeprom_data << 16);
  4.3453  
  4.3454      /* Get word 1 from EEPROM */
  4.3455 -    if(e1000_read_eeprom(hw, ++offset, &eeprom_data) < 0) {
  4.3456 +    if(e1000_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) {
  4.3457          DEBUGOUT("EEPROM Read Error\n");
  4.3458          return -E1000_ERR_EEPROM;
  4.3459      }
  4.3460      /* Save word 1 in lower half of part_num */
  4.3461      *part_num |= eeprom_data;
  4.3462  
  4.3463 -    return 0;
  4.3464 +    return E1000_SUCCESS;
  4.3465  }
  4.3466  
  4.3467  /******************************************************************************
  4.3468 @@ -2768,14 +3710,14 @@ e1000_read_mac_addr(struct e1000_hw * hw
  4.3469  
  4.3470      for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
  4.3471          offset = i >> 1;
  4.3472 -        if(e1000_read_eeprom(hw, offset, &eeprom_data) < 0) {
  4.3473 +        if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
  4.3474              DEBUGOUT("EEPROM Read Error\n");
  4.3475              return -E1000_ERR_EEPROM;
  4.3476          }
  4.3477          hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
  4.3478          hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
  4.3479      }
  4.3480 -    if((hw->mac_type == e1000_82546) &&
  4.3481 +    if(((hw->mac_type == e1000_82546) || (hw->mac_type == e1000_82546_rev_3)) &&
  4.3482         (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
  4.3483          if(hw->perm_mac_addr[5] & 0x01)
  4.3484              hw->perm_mac_addr[5] &= ~(0x01);
  4.3485 @@ -2784,13 +3726,13 @@ e1000_read_mac_addr(struct e1000_hw * hw
  4.3486      }
  4.3487      for(i = 0; i < NODE_ADDRESS_SIZE; i++)
  4.3488          hw->mac_addr[i] = hw->perm_mac_addr[i];
  4.3489 -    return 0;
  4.3490 +    return E1000_SUCCESS;
  4.3491  }
  4.3492  
  4.3493  /******************************************************************************
  4.3494   * Initializes receive address filters.
  4.3495   *
  4.3496 - * hw - Struct containing variables accessed by shared code 
  4.3497 + * hw - Struct containing variables accessed by shared code
  4.3498   *
  4.3499   * Places the MAC address in receive address register 0 and clears the rest
  4.3500   * of the receive addresss registers. Clears the multicast table. Assumes
  4.3501 @@ -2835,7 +3777,7 @@ e1000_init_rx_addrs(struct e1000_hw *hw)
  4.3502   *
  4.3503   * The given list replaces any existing list. Clears the last 15 receive
  4.3504   * address registers and the multicast table. Uses receive address registers
  4.3505 - * for the first 15 multicast addresses, and hashes the rest into the 
  4.3506 + * for the first 15 multicast addresses, and hashes the rest into the
  4.3507   * multicast table.
  4.3508   *****************************************************************************/
  4.3509  void
  4.3510 @@ -2884,7 +3826,7 @@ e1000_mc_addr_list_update(struct e1000_h
  4.3511          DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
  4.3512  
  4.3513          /* Place this multicast address in the RAR if there is room, *
  4.3514 -         * else put it in the MTA            
  4.3515 +         * else put it in the MTA
  4.3516           */
  4.3517          if(rar_used_count < E1000_RAR_ENTRIES) {
  4.3518              e1000_rar_set(hw,
  4.3519 @@ -2902,7 +3844,7 @@ e1000_mc_addr_list_update(struct e1000_h
  4.3520   * Hashes an address to determine its location in the multicast table
  4.3521   *
  4.3522   * hw - Struct containing variables accessed by shared code
  4.3523 - * mc_addr - the multicast address to hash 
  4.3524 + * mc_addr - the multicast address to hash
  4.3525   *****************************************************************************/
  4.3526  uint32_t
  4.3527  e1000_hash_mc_addr(struct e1000_hw *hw,
  4.3528 @@ -2911,7 +3853,7 @@ e1000_hash_mc_addr(struct e1000_hw *hw,
  4.3529      uint32_t hash_value = 0;
  4.3530  
  4.3531      /* The portion of the address that is used for the hash table is
  4.3532 -     * determined by the mc_filter_type setting.  
  4.3533 +     * determined by the mc_filter_type setting.
  4.3534       */
  4.3535      switch (hw->mc_filter_type) {
  4.3536      /* [0] [1] [2] [3] [4] [5]
  4.3537 @@ -2954,12 +3896,12 @@ e1000_mta_set(struct e1000_hw *hw,
  4.3538      uint32_t mta;
  4.3539      uint32_t temp;
  4.3540  
  4.3541 -    /* The MTA is a register array of 128 32-bit registers.  
  4.3542 -     * It is treated like an array of 4096 bits.  We want to set 
  4.3543 +    /* The MTA is a register array of 128 32-bit registers.
  4.3544 +     * It is treated like an array of 4096 bits.  We want to set
  4.3545       * bit BitArray[hash_value]. So we figure out what register
  4.3546       * the bit is in, read it, OR in the new bit, then write
  4.3547 -     * back the new value.  The register is determined by the 
  4.3548 -     * upper 7 bits of the hash value and the bit within that 
  4.3549 +     * back the new value.  The register is determined by the
  4.3550 +     * upper 7 bits of the hash value and the bit within that
  4.3551       * register are determined by the lower 5 bits of the value.
  4.3552       */
  4.3553      hash_reg = (hash_value >> 5) & 0x7F;
  4.3554 @@ -2997,7 +3939,7 @@ e1000_rar_set(struct e1000_hw *hw,
  4.3555      uint32_t rar_low, rar_high;
  4.3556  
  4.3557      /* HW expects these in little endian so we reverse the byte order
  4.3558 -     * from network order (big endian) to little endian              
  4.3559 +     * from network order (big endian) to little endian
  4.3560       */
  4.3561      rar_low = ((uint32_t) addr[0] |
  4.3562                 ((uint32_t) addr[1] << 8) |
  4.3563 @@ -3055,24 +3997,24 @@ e1000_id_led_init(struct e1000_hw * hw)
  4.3564      const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
  4.3565      uint16_t eeprom_data, i, temp;
  4.3566      const uint16_t led_mask = 0x0F;
  4.3567 -        
  4.3568 +
  4.3569      DEBUGFUNC("e1000_id_led_init");
  4.3570 -    
  4.3571 +
  4.3572      if(hw->mac_type < e1000_82540) {
  4.3573          /* Nothing to do */
  4.3574 -        return 0;
  4.3575 +        return E1000_SUCCESS;
  4.3576      }
  4.3577 -    
  4.3578 +
  4.3579      ledctl = E1000_READ_REG(hw, LEDCTL);
  4.3580      hw->ledctl_default = ledctl;
  4.3581      hw->ledctl_mode1 = hw->ledctl_default;
  4.3582      hw->ledctl_mode2 = hw->ledctl_default;
  4.3583 -        
  4.3584 -    if(e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, &eeprom_data) < 0) {
  4.3585 +
  4.3586 +    if(e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
  4.3587          DEBUGOUT("EEPROM Read Error\n");
  4.3588          return -E1000_ERR_EEPROM;
  4.3589      }
  4.3590 -    if((eeprom_data== ID_LED_RESERVED_0000) || 
  4.3591 +    if((eeprom_data== ID_LED_RESERVED_0000) ||
  4.3592         (eeprom_data == ID_LED_RESERVED_FFFF)) eeprom_data = ID_LED_DEFAULT;
  4.3593      for(i = 0; i < 4; i++) {
  4.3594          temp = (eeprom_data >> (i << 2)) & led_mask;
  4.3595 @@ -3111,7 +4053,7 @@ e1000_id_led_init(struct e1000_hw * hw)
  4.3596              break;
  4.3597          }
  4.3598      }
  4.3599 -    return 0;
  4.3600 +    return E1000_SUCCESS;
  4.3601  }
  4.3602  
  4.3603  /******************************************************************************
  4.3604 @@ -3123,45 +4065,48 @@ int32_t
  4.3605  e1000_setup_led(struct e1000_hw *hw)
  4.3606  {
  4.3607      uint32_t ledctl;
  4.3608 - 
  4.3609 +    int32_t ret_val = E1000_SUCCESS;
  4.3610 +
  4.3611      DEBUGFUNC("e1000_setup_led");
  4.3612 -   
  4.3613 -    switch(hw->device_id) {
  4.3614 -    case E1000_DEV_ID_82542:
  4.3615 -    case E1000_DEV_ID_82543GC_FIBER:
  4.3616 -    case E1000_DEV_ID_82543GC_COPPER:
  4.3617 -    case E1000_DEV_ID_82544EI_COPPER:
  4.3618 -    case E1000_DEV_ID_82544EI_FIBER:
  4.3619 -    case E1000_DEV_ID_82544GC_COPPER:
  4.3620 -    case E1000_DEV_ID_82544GC_LOM:
  4.3621 +
  4.3622 +    switch(hw->mac_type) {
  4.3623 +    case e1000_82542_rev2_0:
  4.3624 +    case e1000_82542_rev2_1:
  4.3625 +    case e1000_82543:
  4.3626 +    case e1000_82544:
  4.3627          /* No setup necessary */
  4.3628          break;
  4.3629 -    case E1000_DEV_ID_82545EM_FIBER:
  4.3630 -    case E1000_DEV_ID_82546EB_FIBER:
  4.3631 -        ledctl = E1000_READ_REG(hw, LEDCTL);
  4.3632 -        /* Save current LEDCTL settings */
  4.3633 -        hw->ledctl_default = ledctl;
  4.3634 -        /* Turn off LED0 */
  4.3635 -        ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
  4.3636 -                    E1000_LEDCTL_LED0_BLINK | 
  4.3637 -                    E1000_LEDCTL_LED0_MODE_MASK);
  4.3638 -        ledctl |= (E1000_LEDCTL_MODE_LED_OFF << E1000_LEDCTL_LED0_MODE_SHIFT);
  4.3639 -        E1000_WRITE_REG(hw, LEDCTL, ledctl);
  4.3640 +    case e1000_82541:
  4.3641 +    case e1000_82547:
  4.3642 +    case e1000_82541_rev_2:
  4.3643 +    case e1000_82547_rev_2:
  4.3644 +        /* Turn off PHY Smart Power Down (if enabled) */
  4.3645 +        if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
  4.3646 +                                         &hw->phy_spd_default)))
  4.3647 +            return ret_val;
  4.3648 +        if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
  4.3649 +                                          (uint16_t)(hw->phy_spd_default &
  4.3650 +                                          ~IGP01E1000_GMII_SPD))))
  4.3651 +            return ret_val;
  4.3652 +        /* Fall Through */
  4.3653 +    default:
  4.3654 +        if(hw->media_type == e1000_media_type_fiber) {
  4.3655 +            ledctl = E1000_READ_REG(hw, LEDCTL);
  4.3656 +            /* Save current LEDCTL settings */
  4.3657 +            hw->ledctl_default = ledctl;
  4.3658 +            /* Turn off LED0 */
  4.3659 +            ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
  4.3660 +                        E1000_LEDCTL_LED0_BLINK |
  4.3661 +                        E1000_LEDCTL_LED0_MODE_MASK);
  4.3662 +            ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
  4.3663 +                       E1000_LEDCTL_LED0_MODE_SHIFT);
  4.3664 +            E1000_WRITE_REG(hw, LEDCTL, ledctl);
  4.3665 +        } else if(hw->media_type == e1000_media_type_copper)
  4.3666 +            E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
  4.3667          break;
  4.3668 -    case E1000_DEV_ID_82540EP:
  4.3669 -    case E1000_DEV_ID_82540EP_LOM:
  4.3670 -    case E1000_DEV_ID_82540EP_LP:
  4.3671 -    case E1000_DEV_ID_82540EM:
  4.3672 -    case E1000_DEV_ID_82540EM_LOM:
  4.3673 -    case E1000_DEV_ID_82545EM_COPPER:
  4.3674 -    case E1000_DEV_ID_82546EB_COPPER:
  4.3675 -        E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
  4.3676 -        break;
  4.3677 -    default:
  4.3678 -        DEBUGOUT("Invalid device ID\n");
  4.3679 -        return -E1000_ERR_CONFIG;
  4.3680      }
  4.3681 -    return 0;
  4.3682 +
  4.3683 +    return E1000_SUCCESS;
  4.3684  }
  4.3685  
  4.3686  /******************************************************************************
  4.3687 @@ -3172,37 +4117,35 @@ e1000_setup_led(struct e1000_hw *hw)
  4.3688  int32_t
  4.3689  e1000_cleanup_led(struct e1000_hw *hw)
  4.3690  {
  4.3691 +    int32_t ret_val = E1000_SUCCESS;
  4.3692 +
  4.3693      DEBUGFUNC("e1000_cleanup_led");
  4.3694  
  4.3695 -    switch(hw->device_id) {
  4.3696 -    case E1000_DEV_ID_82542:
  4.3697 -    case E1000_DEV_ID_82543GC_FIBER:
  4.3698 -    case E1000_DEV_ID_82543GC_COPPER:
  4.3699 -    case E1000_DEV_ID_82544EI_COPPER:
  4.3700 -    case E1000_DEV_ID_82544EI_FIBER:
  4.3701 -    case E1000_DEV_ID_82544GC_COPPER:
  4.3702 -    case E1000_DEV_ID_82544GC_LOM:
  4.3703 +    switch(hw->mac_type) {
  4.3704 +    case e1000_82542_rev2_0:
  4.3705 +    case e1000_82542_rev2_1:
  4.3706 +    case e1000_82543:
  4.3707 +    case e1000_82544:
  4.3708          /* No cleanup necessary */
  4.3709          break;
  4.3710 -    case E1000_DEV_ID_82540EP:
  4.3711 -    case E1000_DEV_ID_82540EP_LOM:
  4.3712 -    case E1000_DEV_ID_82540EP_LP:
  4.3713 -    case E1000_DEV_ID_82540EM:
  4.3714 -    case E1000_DEV_ID_82540EM_LOM:
  4.3715 -    case E1000_DEV_ID_82545EM_COPPER:
  4.3716 -    case E1000_DEV_ID_82545EM_FIBER:
  4.3717 -    case E1000_DEV_ID_82546EB_COPPER:
  4.3718 -    case E1000_DEV_ID_82546EB_FIBER:
  4.3719 +    case e1000_82541:
  4.3720 +    case e1000_82547:
  4.3721 +    case e1000_82541_rev_2:
  4.3722 +    case e1000_82547_rev_2:
  4.3723 +        /* Turn on PHY Smart Power Down (if previously enabled) */
  4.3724 +        if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
  4.3725 +                                          hw->phy_spd_default)))
  4.3726 +            return ret_val;
  4.3727 +        /* Fall Through */
  4.3728 +    default:
  4.3729          /* Restore LEDCTL settings */
  4.3730          E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
  4.3731          break;
  4.3732 -    default:
  4.3733 -        DEBUGOUT("Invalid device ID\n");
  4.3734 -        return -E1000_ERR_CONFIG;
  4.3735      }
  4.3736 -    return 0;
  4.3737 +
  4.3738 +    return E1000_SUCCESS;
  4.3739  }
  4.3740 -    
  4.3741 +
  4.3742  /******************************************************************************
  4.3743   * Turns on the software controllable LED
  4.3744   *
  4.3745 @@ -3211,46 +4154,44 @@ e1000_cleanup_led(struct e1000_hw *hw)
  4.3746  int32_t
  4.3747  e1000_led_on(struct e1000_hw *hw)
  4.3748  {
  4.3749 -    uint32_t ctrl;
  4.3750 +    uint32_t ctrl = E1000_READ_REG(hw, CTRL);
  4.3751  
  4.3752      DEBUGFUNC("e1000_led_on");
  4.3753  
  4.3754 -    switch(hw->device_id) {
  4.3755 -    case E1000_DEV_ID_82542:
  4.3756 -    case E1000_DEV_ID_82543GC_FIBER:
  4.3757 -    case E1000_DEV_ID_82543GC_COPPER:
  4.3758 -    case E1000_DEV_ID_82544EI_FIBER:
  4.3759 -        ctrl = E1000_READ_REG(hw, CTRL);
  4.3760 +    switch(hw->mac_type) {
  4.3761 +    case e1000_82542_rev2_0:
  4.3762 +    case e1000_82542_rev2_1:
  4.3763 +    case e1000_82543:
  4.3764          /* Set SW Defineable Pin 0 to turn on the LED */
  4.3765          ctrl |= E1000_CTRL_SWDPIN0;
  4.3766          ctrl |= E1000_CTRL_SWDPIO0;
  4.3767 -        E1000_WRITE_REG(hw, CTRL, ctrl);
  4.3768          break;
  4.3769 -    case E1000_DEV_ID_82544EI_COPPER:
  4.3770 -    case E1000_DEV_ID_82544GC_COPPER:
  4.3771 -    case E1000_DEV_ID_82544GC_LOM:
  4.3772 -    case E1000_DEV_ID_82545EM_FIBER:
  4.3773 -    case E1000_DEV_ID_82546EB_FIBER:
  4.3774 -        ctrl = E1000_READ_REG(hw, CTRL);
  4.3775 -        /* Clear SW Defineable Pin 0 to turn on the LED */
  4.3776 -        ctrl &= ~E1000_CTRL_SWDPIN0;
  4.3777 -        ctrl |= E1000_CTRL_SWDPIO0;
  4.3778 -        E1000_WRITE_REG(hw, CTRL, ctrl);
  4.3779 -        break;
  4.3780 -    case E1000_DEV_ID_82540EP:
  4.3781 -    case E1000_DEV_ID_82540EP_LOM:
  4.3782 -    case E1000_DEV_ID_82540EP_LP:
  4.3783 -    case E1000_DEV_ID_82540EM:
  4.3784 -    case E1000_DEV_ID_82540EM_LOM:
  4.3785 -    case E1000_DEV_ID_82545EM_COPPER:
  4.3786 -    case E1000_DEV_ID_82546EB_COPPER:
  4.3787 -        E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
  4.3788 +    case e1000_82544:
  4.3789 +        if(hw->media_type == e1000_media_type_fiber) {
  4.3790 +            /* Set SW Defineable Pin 0 to turn on the LED */
  4.3791 +            ctrl |= E1000_CTRL_SWDPIN0;
  4.3792 +            ctrl |= E1000_CTRL_SWDPIO0;
  4.3793 +        } else {
  4.3794 +            /* Clear SW Defineable Pin 0 to turn on the LED */
  4.3795 +            ctrl &= ~E1000_CTRL_SWDPIN0;
  4.3796 +            ctrl |= E1000_CTRL_SWDPIO0;
  4.3797 +        }
  4.3798          break;
  4.3799      default:
  4.3800 -        DEBUGOUT("Invalid device ID\n");
  4.3801 -        return -E1000_ERR_CONFIG;
  4.3802 +        if(hw->media_type == e1000_media_type_fiber) {
  4.3803 +            /* Clear SW Defineable Pin 0 to turn on the LED */
  4.3804 +            ctrl &= ~E1000_CTRL_SWDPIN0;
  4.3805 +            ctrl |= E1000_CTRL_SWDPIO0;
  4.3806 +        } else if(hw->media_type == e1000_media_type_copper) {
  4.3807 +            E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
  4.3808 +            return E1000_SUCCESS;
  4.3809 +        }
  4.3810 +        break;
  4.3811      }
  4.3812 -    return 0;
  4.3813 +
  4.3814 +    E1000_WRITE_REG(hw, CTRL, ctrl);
  4.3815 +
  4.3816 +    return E1000_SUCCESS;
  4.3817  }
  4.3818  
  4.3819  /******************************************************************************
  4.3820 @@ -3261,50 +4202,48 @@ e1000_led_on(struct e1000_hw *hw)
  4.3821  int32_t
  4.3822  e1000_led_off(struct e1000_hw *hw)
  4.3823  {
  4.3824 -    uint32_t ctrl;
  4.3825 +    uint32_t ctrl = E1000_READ_REG(hw, CTRL);
  4.3826  
  4.3827      DEBUGFUNC("e1000_led_off");
  4.3828  
  4.3829 -    switch(hw->device_id) {
  4.3830 -    case E1000_DEV_ID_82542:
  4.3831 -    case E1000_DEV_ID_82543GC_FIBER:
  4.3832 -    case E1000_DEV_ID_82543GC_COPPER:
  4.3833 -    case E1000_DEV_ID_82544EI_FIBER:
  4.3834 -        ctrl = E1000_READ_REG(hw, CTRL);
  4.3835 +    switch(hw->mac_type) {
  4.3836 +    case e1000_82542_rev2_0:
  4.3837 +    case e1000_82542_rev2_1:
  4.3838 +    case e1000_82543:
  4.3839          /* Clear SW Defineable Pin 0 to turn off the LED */
  4.3840          ctrl &= ~E1000_CTRL_SWDPIN0;
  4.3841          ctrl |= E1000_CTRL_SWDPIO0;
  4.3842 -        E1000_WRITE_REG(hw, CTRL, ctrl);
  4.3843          break;
  4.3844 -    case E1000_DEV_ID_82544EI_COPPER:
  4.3845 -    case E1000_DEV_ID_82544GC_COPPER:
  4.3846 -    case E1000_DEV_ID_82544GC_LOM:
  4.3847 -    case E1000_DEV_ID_82545EM_FIBER:
  4.3848 -    case E1000_DEV_ID_82546EB_FIBER:
  4.3849 -        ctrl = E1000_READ_REG(hw, CTRL);
  4.3850 -        /* Set SW Defineable Pin 0 to turn off the LED */
  4.3851 -        ctrl |= E1000_CTRL_SWDPIN0;
  4.3852 -        ctrl |= E1000_CTRL_SWDPIO0;
  4.3853 -        E1000_WRITE_REG(hw, CTRL, ctrl);
  4.3854 -        break;
  4.3855 -    case E1000_DEV_ID_82540EP:
  4.3856 -    case E1000_DEV_ID_82540EP_LOM:
  4.3857 -    case E1000_DEV_ID_82540EP_LP:
  4.3858 -    case E1000_DEV_ID_82540EM:
  4.3859 -    case E1000_DEV_ID_82540EM_LOM:
  4.3860 -    case E1000_DEV_ID_82545EM_COPPER:
  4.3861 -    case E1000_DEV_ID_82546EB_COPPER:
  4.3862 -        E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
  4.3863 +    case e1000_82544:
  4.3864 +        if(hw->media_type == e1000_media_type_fiber) {
  4.3865 +            /* Clear SW Defineable Pin 0 to turn off the LED */
  4.3866 +            ctrl &= ~E1000_CTRL_SWDPIN0;
  4.3867 +            ctrl |= E1000_CTRL_SWDPIO0;
  4.3868 +        } else {
  4.3869 +            /* Set SW Defineable Pin 0 to turn off the LED */
  4.3870 +            ctrl |= E1000_CTRL_SWDPIN0;
  4.3871 +            ctrl |= E1000_CTRL_SWDPIO0;
  4.3872 +        }
  4.3873          break;
  4.3874      default:
  4.3875 -        DEBUGOUT("Invalid device ID\n");
  4.3876 -        return -E1000_ERR_CONFIG;
  4.3877 +        if(hw->media_type == e1000_media_type_fiber) {
  4.3878 +            /* Set SW Defineable Pin 0 to turn off the LED */
  4.3879 +            ctrl |= E1000_CTRL_SWDPIN0;
  4.3880 +            ctrl |= E1000_CTRL_SWDPIO0;
  4.3881 +        } else if(hw->media_type == e1000_media_type_copper) {
  4.3882 +            E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
  4.3883 +            return E1000_SUCCESS;
  4.3884 +        }
  4.3885 +        break;
  4.3886      }
  4.3887 -    return 0;
  4.3888 +
  4.3889 +    E1000_WRITE_REG(hw, CTRL, ctrl);
  4.3890 +
  4.3891 +    return E1000_SUCCESS;
  4.3892  }
  4.3893  
  4.3894  /******************************************************************************
  4.3895 - * Clears all hardware statistics counters. 
  4.3896 + * Clears all hardware statistics counters.
  4.3897   *
  4.3898   * hw - Struct containing variables accessed by shared code
  4.3899   *****************************************************************************/
  4.3900 @@ -3423,8 +4362,7 @@ e1000_update_adaptive(struct e1000_hw *h
  4.3901      DEBUGFUNC("e1000_update_adaptive");
  4.3902  
  4.3903      if(hw->adaptive_ifs) {
  4.3904 -        if((hw->collision_delta * hw->ifs_ratio) > 
  4.3905 -           hw->tx_packet_delta) {
  4.3906 +        if((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
  4.3907              if(hw->tx_packet_delta > MIN_NUM_XMITS) {
  4.3908                  hw->in_ifs_mode = TRUE;
  4.3909                  if(hw->current_ifs_val < hw->ifs_max_val) {
  4.3910 @@ -3436,8 +4374,7 @@ e1000_update_adaptive(struct e1000_hw *h
  4.3911                  }
  4.3912              }
  4.3913          } else {
  4.3914 -            if((hw->in_ifs_mode == TRUE) && 
  4.3915 -               (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
  4.3916 +            if(hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
  4.3917                  hw->current_ifs_val = 0;
  4.3918                  hw->in_ifs_mode = FALSE;
  4.3919                  E1000_WRITE_REG(hw, AIT, 0);
  4.3920 @@ -3450,7 +4387,7 @@ e1000_update_adaptive(struct e1000_hw *h
  4.3921  
  4.3922  /******************************************************************************
  4.3923   * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
  4.3924 - * 
  4.3925 + *
  4.3926   * hw - Struct containing variables accessed by shared code
  4.3927   * frame_len - The length of the frame in question
  4.3928   * mac_addr - The Ethernet destination address of the frame in question
  4.3929 @@ -3478,16 +4415,16 @@ e1000_tbi_adjust_stats(struct e1000_hw *
  4.3930      carry_bit = 0x80000000 & stats->gorcl;
  4.3931      stats->gorcl += frame_len;
  4.3932      /* If the high bit of Gorcl (the low 32 bits of the Good Octets
  4.3933 -     * Received Count) was one before the addition, 
  4.3934 -     * AND it is zero after, then we lost the carry out, 
  4.3935 +     * Received Count) was one before the addition,
  4.3936 +     * AND it is zero after, then we lost the carry out,
  4.3937       * need to add one to Gorch (Good Octets Received Count High).
  4.3938 -     * This could be simplified if all environments supported 
  4.3939 +     * This could be simplified if all environments supported
  4.3940       * 64-bit integers.
  4.3941       */
  4.3942      if(carry_bit && ((stats->gorcl & 0x80000000) == 0))
  4.3943          stats->gorch++;
  4.3944      /* Is this a broadcast or multicast?  Check broadcast first,
  4.3945 -     * since the test for a multicast frame will test positive on 
  4.3946 +     * since the test for a multicast frame will test positive on
  4.3947       * a broadcast frame.
  4.3948       */
  4.3949      if((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
  4.3950 @@ -3548,7 +4485,11 @@ e1000_get_bus_info(struct e1000_hw *hw)
  4.3951      status = E1000_READ_REG(hw, STATUS);
  4.3952      hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
  4.3953                     e1000_bus_type_pcix : e1000_bus_type_pci;
  4.3954 -    if(hw->bus_type == e1000_bus_type_pci) {
  4.3955 +
  4.3956 +    if(hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
  4.3957 +        hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
  4.3958 +                        e1000_bus_speed_66 : e1000_bus_speed_120;
  4.3959 +    } else if(hw->bus_type == e1000_bus_type_pci) {
  4.3960          hw->bus_speed = (status & E1000_STATUS_PCI66) ?
  4.3961                          e1000_bus_speed_66 : e1000_bus_speed_33;
  4.3962      } else {
  4.3963 @@ -3608,3 +4549,547 @@ e1000_write_reg_io(struct e1000_hw *hw,
  4.3964      e1000_io_write(hw, io_data, value);
  4.3965  }
  4.3966  
  4.3967 +
  4.3968 +/******************************************************************************
  4.3969 + * Estimates the cable length.
  4.3970 + *
  4.3971 + * hw - Struct containing variables accessed by shared code
  4.3972 + * min_length - The estimated minimum length
  4.3973 + * max_length - The estimated maximum length
  4.3974 + *
  4.3975 + * returns: - E1000_ERR_XXX
  4.3976 + *            E1000_SUCCESS
  4.3977 + *
  4.3978 + * This function always returns a ranged length (minimum & maximum).
  4.3979 + * So for M88 phy's, this function interprets the one value returned from the
  4.3980 + * register to the minimum and maximum range.
  4.3981 + * For IGP phy's, the function calculates the range by the AGC registers.
  4.3982 + *****************************************************************************/
  4.3983 +int32_t
  4.3984 +e1000_get_cable_length(struct e1000_hw *hw,
  4.3985 +                       uint16_t *min_length,
  4.3986 +                       uint16_t *max_length)
  4.3987 +{
  4.3988 +    int32_t ret_val;
  4.3989 +    uint16_t agc_value = 0;
  4.3990 +    uint16_t cur_agc, min_agc = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
  4.3991 +    uint16_t i, phy_data;
  4.3992 +
  4.3993 +    DEBUGFUNC("e1000_get_cable_length");
  4.3994 +
  4.3995 +    *min_length = *max_length = 0;
  4.3996 +
  4.3997 +    /* Use old method for Phy older than IGP */
  4.3998 +    if(hw->phy_type == e1000_phy_m88) {
  4.3999 +        if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
  4.4000 +                                         &phy_data)))
  4.4001 +            return ret_val;
  4.4002 +
  4.4003 +        /* Convert the enum value to ranged values */
  4.4004 +        switch((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
  4.4005 +               M88E1000_PSSR_CABLE_LENGTH_SHIFT) {
  4.4006 +        case e1000_cable_length_50:
  4.4007 +            *min_length = 0;
  4.4008 +            *max_length = e1000_igp_cable_length_50;
  4.4009 +            break;
  4.4010 +        case e1000_cable_length_50_80:
  4.4011 +            *min_length = e1000_igp_cable_length_50;
  4.4012 +            *max_length = e1000_igp_cable_length_80;
  4.4013 +            break;
  4.4014 +        case e1000_cable_length_80_110:
  4.4015 +            *min_length = e1000_igp_cable_length_80;
  4.4016 +            *max_length = e1000_igp_cable_length_110;
  4.4017 +            break;
  4.4018 +        case e1000_cable_length_110_140:
  4.4019 +            *min_length = e1000_igp_cable_length_110;
  4.4020 +            *max_length = e1000_igp_cable_length_140;
  4.4021 +            break;
  4.4022 +        case e1000_cable_length_140:
  4.4023 +            *min_length = e1000_igp_cable_length_140;
  4.4024 +            *max_length = e1000_igp_cable_length_170;
  4.4025 +            break;
  4.4026 +        default:
  4.4027 +            return -E1000_ERR_PHY;
  4.4028 +            break;
  4.4029 +        }
  4.4030 +    } else if(hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
  4.4031 +        uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
  4.4032 +                                                         {IGP01E1000_PHY_AGC_A,
  4.4033 +                                                          IGP01E1000_PHY_AGC_B,
  4.4034 +                                                          IGP01E1000_PHY_AGC_C,
  4.4035 +                                                          IGP01E1000_PHY_AGC_D};
  4.4036 +        /* Read the AGC registers for all channels */
  4.4037 +        for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
  4.4038 +
  4.4039 +            if((ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data)))
  4.4040 +                return ret_val;
  4.4041 +
  4.4042 +            cur_agc = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
  4.4043 +
  4.4044 +            /* Array bound check. */
  4.4045 +            if((cur_agc >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
  4.4046 +               (cur_agc == 0))
  4.4047 +                return -E1000_ERR_PHY;
  4.4048 +
  4.4049 +            agc_value += cur_agc;
  4.4050 +
  4.4051 +            /* Update minimal AGC value. */
  4.4052 +            if(min_agc > cur_agc)
  4.4053 +                min_agc = cur_agc;
  4.4054 +        }
  4.4055 +
  4.4056 +        /* Remove the minimal AGC result for length < 50m */
  4.4057 +        if(agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
  4.4058 +            agc_value -= min_agc;
  4.4059 +
  4.4060 +            /* Get the average length of the remaining 3 channels */
  4.4061 +            agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
  4.4062 +        } else {
  4.4063 +            /* Get the average length of all the 4 channels. */
  4.4064 +            agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
  4.4065 +        }
  4.4066 +
  4.4067 +        /* Set the range of the calculated length. */
  4.4068 +        *min_length = ((e1000_igp_cable_length_table[agc_value] -
  4.4069 +                       IGP01E1000_AGC_RANGE) > 0) ?
  4.4070 +                       (e1000_igp_cable_length_table[agc_value] -
  4.4071 +                       IGP01E1000_AGC_RANGE) : 0;
  4.4072 +        *max_length = e1000_igp_cable_length_table[agc_value] +
  4.4073 +                      IGP01E1000_AGC_RANGE;
  4.4074 +    }
  4.4075 +
  4.4076 +    return E1000_SUCCESS;
  4.4077 +}
  4.4078 +
  4.4079 +/******************************************************************************
  4.4080 + * Check the cable polarity
  4.4081 + *
  4.4082 + * hw - Struct containing variables accessed by shared code
  4.4083 + * polarity - output parameter : 0 - Polarity is not reversed
  4.4084 + *                               1 - Polarity is reversed.
  4.4085 + *
  4.4086 + * returns: - E1000_ERR_XXX
  4.4087 + *            E1000_SUCCESS
  4.4088 + *
  4.4089 + * For phy's older then IGP, this function simply reads the polarity bit in the
  4.4090 + * Phy Status register.  For IGP phy's, this bit is valid only if link speed is
  4.4091 + * 10 Mbps.  If the link speed is 100 Mbps there is no polarity so this bit will
  4.4092 + * return 0.  If the link speed is 1000 Mbps the polarity status is in the
  4.4093 + * IGP01E1000_PHY_PCS_INIT_REG.
  4.4094 + *****************************************************************************/
  4.4095 +int32_t
  4.4096 +e1000_check_polarity(struct e1000_hw *hw,
  4.4097 +                     uint16_t *polarity)
  4.4098 +{
  4.4099 +    int32_t ret_val;
  4.4100 +    uint16_t phy_data;
  4.4101 +
  4.4102 +    DEBUGFUNC("e1000_check_polarity");
  4.4103 +
  4.4104 +    if(hw->phy_type == e1000_phy_m88) {
  4.4105 +        /* return the Polarity bit in the Status register. */
  4.4106 +        if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
  4.4107 +                                         &phy_data)))
  4.4108 +            return ret_val;
  4.4109 +        *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
  4.4110 +                    M88E1000_PSSR_REV_POLARITY_SHIFT;
  4.4111 +    } else if(hw->phy_type == e1000_phy_igp) {
  4.4112 +        /* Read the Status register to check the speed */
  4.4113 +        if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
  4.4114 +                                         &phy_data)))
  4.4115 +            return ret_val;
  4.4116 +
  4.4117 +        /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
  4.4118 +         * find the polarity status */
  4.4119 +        if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
  4.4120 +           IGP01E1000_PSSR_SPEED_1000MBPS) {
  4.4121 +
  4.4122 +            /* Read the GIG initialization PCS register (0x00B4) */
  4.4123 +            if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
  4.4124 +                                             &phy_data)))
  4.4125 +                return ret_val;
  4.4126 +
  4.4127 +            /* Check the polarity bits */
  4.4128 +            *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 1 : 0;
  4.4129 +        } else {
  4.4130 +            /* For 10 Mbps, read the polarity bit in the status register. (for
  4.4131 +             * 100 Mbps this bit is always 0) */
  4.4132 +            *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED;
  4.4133 +        }
  4.4134 +    }
  4.4135 +    return E1000_SUCCESS;
  4.4136 +}
  4.4137 +
  4.4138 +/******************************************************************************
  4.4139 + * Check if Downshift occured
  4.4140 + *
  4.4141 + * hw - Struct containing variables accessed by shared code
  4.4142 + * downshift - output parameter : 0 - No Downshift ocured.
  4.4143 + *                                1 - Downshift ocured.
  4.4144 + *
  4.4145 + * returns: - E1000_ERR_XXX
  4.4146 + *            E1000_SUCCESS 
  4.4147 + *
  4.4148 + * For phy's older then IGP, this function reads the Downshift bit in the Phy
  4.4149 + * Specific Status register.  For IGP phy's, it reads the Downgrade bit in the
  4.4150 + * Link Health register.  In IGP this bit is latched high, so the driver must
  4.4151 + * read it immediately after link is established.
  4.4152 + *****************************************************************************/
  4.4153 +int32_t
  4.4154 +e1000_check_downshift(struct e1000_hw *hw)
  4.4155 +{
  4.4156 +    int32_t ret_val;
  4.4157 +    uint16_t phy_data;
  4.4158 +
  4.4159 +    DEBUGFUNC("e1000_check_downshift");
  4.4160 +
  4.4161 +    if(hw->phy_type == e1000_phy_igp) {
  4.4162 +        if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
  4.4163 +                                         &phy_data)))
  4.4164 +            return ret_val;
  4.4165 +
  4.4166 +        hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
  4.4167 +    }
  4.4168 +    else if(hw->phy_type == e1000_phy_m88) {
  4.4169 +        if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
  4.4170 +                                         &phy_data)))
  4.4171 +            return ret_val;
  4.4172 +
  4.4173 +        hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
  4.4174 +                               M88E1000_PSSR_DOWNSHIFT_SHIFT;
  4.4175 +    }
  4.4176 +    return E1000_SUCCESS;
  4.4177 +}
  4.4178 +
  4.4179 +/*****************************************************************************
  4.4180 + *
  4.4181 + * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
  4.4182 + * gigabit link is achieved to improve link quality.
  4.4183 + *
  4.4184 + * hw: Struct containing variables accessed by shared code
  4.4185 + *
  4.4186 + * returns: - E1000_ERR_PHY if fail to read/write the PHY
  4.4187 + *            E1000_SUCCESS at any other case.
  4.4188 + *
  4.4189 + ****************************************************************************/
  4.4190 +
  4.4191 +int32_t
  4.4192 +e1000_config_dsp_after_link_change(struct e1000_hw *hw,
  4.4193 +                                   boolean_t link_up)
  4.4194 +{
  4.4195 +    int32_t ret_val;
  4.4196 +    uint16_t phy_data, speed, duplex, i;
  4.4197 +    uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
  4.4198 +                                        {IGP01E1000_PHY_AGC_PARAM_A,
  4.4199 +                                        IGP01E1000_PHY_AGC_PARAM_B,
  4.4200 +                                        IGP01E1000_PHY_AGC_PARAM_C,
  4.4201 +                                        IGP01E1000_PHY_AGC_PARAM_D};
  4.4202 +    uint16_t min_length, max_length;
  4.4203 +
  4.4204 +    DEBUGFUNC("e1000_config_dsp_after_link_change");
  4.4205 +
  4.4206 +    if(hw->phy_type != e1000_phy_igp)
  4.4207 +        return E1000_SUCCESS;
  4.4208 +
  4.4209 +    if(link_up) {
  4.4210 +        if((ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex))) {
  4.4211 +            DEBUGOUT("Error getting link speed and duplex\n");
  4.4212 +            return ret_val;
  4.4213 +        }
  4.4214 +
  4.4215 +        if(speed == SPEED_1000) {
  4.4216 +
  4.4217 +            e1000_get_cable_length(hw, &min_length, &max_length);
  4.4218 +
  4.4219 +            if((hw->dsp_config_state == e1000_dsp_config_enabled) &&
  4.4220 +                min_length >= e1000_igp_cable_length_50) {
  4.4221 +
  4.4222 +                for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
  4.4223 +                    if((ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
  4.4224 +                                                     &phy_data)))
  4.4225 +                        return ret_val;
  4.4226 +
  4.4227 +                    phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
  4.4228 +
  4.4229 +                    if((ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
  4.4230 +                                                      phy_data)))
  4.4231 +                        return ret_val;
  4.4232 +                }
  4.4233 +                hw->dsp_config_state = e1000_dsp_config_activated;
  4.4234 +            }
  4.4235 +
  4.4236 +            if((hw->ffe_config_state == e1000_ffe_config_enabled) &&
  4.4237 +               (min_length < e1000_igp_cable_length_50)) {
  4.4238 +
  4.4239 +                uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
  4.4240 +                uint32_t idle_errs = 0;
  4.4241 +
  4.4242 +                /* clear previous idle error counts */
  4.4243 +                if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
  4.4244 +                                                 &phy_data)))
  4.4245 +                    return ret_val;
  4.4246 +
  4.4247 +                for(i = 0; i < ffe_idle_err_timeout; i++) {
  4.4248 +                    usec_delay(1000);
  4.4249 +                    if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
  4.4250 +                                                     &phy_data)))
  4.4251 +                        return ret_val;
  4.4252 +
  4.4253 +                    idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
  4.4254 +                    if(idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
  4.4255 +                        hw->ffe_config_state = e1000_ffe_config_active;
  4.4256 +
  4.4257 +                        if((ret_val = e1000_write_phy_reg(hw,
  4.4258 +                                    IGP01E1000_PHY_DSP_FFE,
  4.4259 +                                    IGP01E1000_PHY_DSP_FFE_CM_CP)))
  4.4260 +                            return ret_val;
  4.4261 +                        break;
  4.4262 +                    }
  4.4263 +
  4.4264 +                    if(idle_errs)
  4.4265 +                        ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
  4.4266 +                }
  4.4267 +            }
  4.4268 +        }
  4.4269 +    } else {
  4.4270 +        if(hw->dsp_config_state == e1000_dsp_config_activated) {
  4.4271 +            if((ret_val = e1000_write_phy_reg(hw, 0x0000,
  4.4272 +                IGP01E1000_IEEE_FORCE_GIGA)))
  4.4273 +                return ret_val;
  4.4274 +            for(i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
  4.4275 +                if((ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
  4.4276 +                                                 &phy_data)))
  4.4277 +                    return ret_val;
  4.4278 +
  4.4279 +                phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
  4.4280 +                phy_data |=  IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
  4.4281 +
  4.4282 +                if((ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i],
  4.4283 +                                                  phy_data)))
  4.4284 +                    return ret_val;
  4.4285 +            }
  4.4286 +
  4.4287 +            if((ret_val = e1000_write_phy_reg(hw, 0x0000,
  4.4288 +                                              IGP01E1000_IEEE_RESTART_AUTONEG)))
  4.4289 +                return ret_val;
  4.4290 +
  4.4291 +            hw->dsp_config_state = e1000_dsp_config_enabled;
  4.4292 +        }
  4.4293 +
  4.4294 +        if(hw->ffe_config_state == e1000_ffe_config_active) {
  4.4295 +            if((ret_val = e1000_write_phy_reg(hw, 0x0000,
  4.4296 +                                              IGP01E1000_IEEE_FORCE_GIGA)))
  4.4297 +                return ret_val;
  4.4298 +            if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
  4.4299 +                                              IGP01E1000_PHY_DSP_FFE_DEFAULT)))
  4.4300 +                return ret_val;
  4.4301 +
  4.4302 +            if((ret_val = e1000_write_phy_reg(hw, 0x0000,
  4.4303 +                                              IGP01E1000_IEEE_RESTART_AUTONEG)))
  4.4304 +                return ret_val;
  4.4305 +        hw->ffe_config_state = e1000_ffe_config_enabled;
  4.4306 +        }
  4.4307 +    }
  4.4308 +    return E1000_SUCCESS;
  4.4309 +}
  4.4310 +
  4.4311 +/***************************************************************************
  4.4312 + *
  4.4313 + * Workaround for the 82547 long TTL on noisy 100HD hubs.
  4.4314 + *
  4.4315 + * This function, specific to 82547 hardware only, needs to be called every
  4.4316 + * second.  It checks if a parallel detect fault has occurred.  If a fault
  4.4317 + * occurred, disable/enable the DSP reset mechanism up to 5 times (once per
  4.4318 + * second).  If link is established, stop the workaround and ensure the DSP
  4.4319 + * reset is enabled.
  4.4320 + *
  4.4321 + * hw: Struct containing variables accessed by shared code
  4.4322 + *
  4.4323 + * returns: - E1000_ERR_PHY if fail to read/write the PHY
  4.4324 + *            E1000_SUCCESS in any other case
  4.4325 + *
  4.4326 + ****************************************************************************/
  4.4327 +int32_t
  4.4328 +e1000_igp_ttl_workaround(struct e1000_hw *hw)
  4.4329 +{
  4.4330 +    int32_t ret_val;
  4.4331 +    uint16_t phy_data = 0;
  4.4332 +    uint16_t dsp_value = DSP_RESET_ENABLE;
  4.4333 +
  4.4334 +    if(((hw->mac_type != e1000_82541) && (hw->mac_type != e1000_82547)) ||
  4.4335 +       (!hw->ttl_wa_activation)) {
  4.4336 +        return E1000_SUCCESS;
  4.4337 +    }
  4.4338 +
  4.4339 +    /* Check for link first */
  4.4340 +    if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
  4.4341 +        return ret_val;
  4.4342 +
  4.4343 +    if(phy_data & MII_SR_LINK_STATUS) {
  4.4344 +        /* If link is established during the workaround, the DSP mechanism must
  4.4345 +         * be enabled. */
  4.4346 +        if(hw->dsp_reset_counter) {
  4.4347 +            hw->dsp_reset_counter = 0;
  4.4348 +            dsp_value = DSP_RESET_ENABLE;
  4.4349 +        } else
  4.4350 +            return E1000_SUCCESS;
  4.4351 +    } else {
  4.4352 +        if(hw->dsp_reset_counter == 0) {
  4.4353 +            /* Workaround not activated, check if it needs activation */
  4.4354 +            if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data)))
  4.4355 +                return ret_val;
  4.4356 +            /* Activate the workaround if there was a parallel detect fault */
  4.4357 +            if(phy_data & NWAY_ER_PAR_DETECT_FAULT)
  4.4358 +                hw->dsp_reset_counter++;
  4.4359 +            else
  4.4360 +                return E1000_SUCCESS;
  4.4361 +        }
  4.4362 +
  4.4363 +        if(hw->dsp_reset_counter) {
  4.4364 +            /* After 5 times, stop the workaround */
  4.4365 +            if(hw->dsp_reset_counter > E1000_MAX_DSP_RESETS) {
  4.4366 +                hw->dsp_reset_counter = 0;
  4.4367 +                dsp_value = DSP_RESET_ENABLE;
  4.4368 +            } else {
  4.4369 +                dsp_value = (hw->dsp_reset_counter & 1) ? DSP_RESET_DISABLE :
  4.4370 +                            DSP_RESET_ENABLE;
  4.4371 +                hw->dsp_reset_counter++;
  4.4372 +            }
  4.4373 +        }
  4.4374 +    }
  4.4375 +
  4.4376 +    if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_RESET, dsp_value)))
  4.4377 +        return ret_val;
  4.4378 +
  4.4379 +    return E1000_SUCCESS;
  4.4380 +}
  4.4381 +
  4.4382 +/*****************************************************************************
  4.4383 + *
  4.4384 + * This function sets the lplu state according to the active flag.  When
  4.4385 + * activating lplu this function also disables smart speed and vise versa.
  4.4386 + * lplu will not be activated unless the device autonegotiation advertisment
  4.4387 + * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
  4.4388 + * hw: Struct containing variables accessed by shared code
  4.4389 + * active - true to enable lplu false to disable lplu.
  4.4390 + *
  4.4391 + * returns: - E1000_ERR_PHY if fail to read/write the PHY
  4.4392 + *            E1000_SUCCESS at any other case.
  4.4393 + *
  4.4394 + ****************************************************************************/
  4.4395 +
  4.4396 +int32_t
  4.4397 +e1000_set_d3_lplu_state(struct e1000_hw *hw,
  4.4398 +                        boolean_t active)
  4.4399 +{
  4.4400 +    int32_t ret_val;
  4.4401 +    uint16_t phy_data;
  4.4402 +    DEBUGFUNC("e1000_set_d3_lplu_state");
  4.4403 +
  4.4404 +    if(!((hw->mac_type == e1000_82541_rev_2) ||
  4.4405 +         (hw->mac_type == e1000_82547_rev_2)))
  4.4406 +        return E1000_SUCCESS;
  4.4407 +
  4.4408 +    /* During driver activity LPLU should not be used or it will attain link
  4.4409 +     * from the lowest speeds starting from 10Mbps. The capability is used for
  4.4410 +     * Dx transitions and states */
  4.4411 +    if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data)))
  4.4412 +        return ret_val;
  4.4413 +
  4.4414 +    if(!active) {
  4.4415 +        phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
  4.4416 +        if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data)))
  4.4417 +            return ret_val;
  4.4418 +
  4.4419 +        /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
  4.4420 +         * Dx states where the power conservation is most important.  During
  4.4421 +         * driver activity we should enable SmartSpeed, so performance is
  4.4422 +         * maintained. */
  4.4423 +        if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
  4.4424 +                                         &phy_data)))
  4.4425 +            return ret_val;
  4.4426 +
  4.4427 +        phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
  4.4428 +        if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
  4.4429 +                                          phy_data)))
  4.4430 +            return ret_val;
  4.4431 +
  4.4432 +    } else if((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
  4.4433 +              (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
  4.4434 +              (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
  4.4435 +
  4.4436 +        phy_data |= IGP01E1000_GMII_FLEX_SPD;
  4.4437 +        if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data)))
  4.4438 +            return ret_val;
  4.4439 +
  4.4440 +        /* When LPLU is enabled we should disable SmartSpeed */
  4.4441 +        if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
  4.4442 +                                         &phy_data)))
  4.4443 +            return ret_val;
  4.4444 +
  4.4445 +        phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  4.4446 +        if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
  4.4447 +                                          phy_data)))
  4.4448 +            return ret_val;
  4.4449 +
  4.4450 +    }
  4.4451 +    return E1000_SUCCESS;
  4.4452 +}
  4.4453 +
  4.4454 +/******************************************************************************
  4.4455 + * Change VCO speed register to improve Bit Error Rate performance of SERDES.
  4.4456 + *
  4.4457 + * hw - Struct containing variables accessed by shared code
  4.4458 + *****************************************************************************/
  4.4459 +static int32_t
  4.4460 +e1000_set_vco_speed(struct e1000_hw *hw)
  4.4461 +{
  4.4462 +    int32_t  ret_val;
  4.4463 +    uint16_t default_page = 0;
  4.4464 +    uint16_t phy_data;
  4.4465 +
  4.4466 +    DEBUGFUNC("e1000_set_vco_speed");
  4.4467 +
  4.4468 +    switch(hw->mac_type) {
  4.4469 +    case e1000_82545_rev_3:
  4.4470 +    case e1000_82546_rev_3:
  4.4471 +       break;
  4.4472 +    default:
  4.4473 +        return E1000_SUCCESS;
  4.4474 +    }
  4.4475 +
  4.4476 +    /* Set PHY register 30, page 5, bit 8 to 0 */
  4.4477 +
  4.4478 +    if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
  4.4479 +                                     &default_page)))
  4.4480 +        return ret_val;
  4.4481 +
  4.4482 +    if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005)))
  4.4483 +        return ret_val;
  4.4484 +
  4.4485 +    if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data)))
  4.4486 +        return ret_val;
  4.4487 +
  4.4488 +    phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
  4.4489 +    if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data)))
  4.4490 +        return ret_val;
  4.4491 +
  4.4492 +    /* Set PHY register 30, page 4, bit 11 to 1 */
  4.4493 +
  4.4494 +    if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004)))
  4.4495 +        return ret_val;
  4.4496 +
  4.4497 +    if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data)))
  4.4498 +        return ret_val;
  4.4499 +
  4.4500 +    phy_data |= M88E1000_PHY_VCO_REG_BIT11;
  4.4501 +    if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data)))
  4.4502 +        return ret_val;
  4.4503 +
  4.4504 +    if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
  4.4505 +                                      default_page)))
  4.4506 +        return ret_val;
  4.4507 +
  4.4508 +    return E1000_SUCCESS;
  4.4509 +}
  4.4510 +