ia64/xen-unstable

changeset 15152:33c3dbc8ab3d

[IA64] Remove GLOBAL_VHPT

It was always defined.

Signed-off-by: Tristan Gingold <tgingold@free.fr>
author Alex Williamson <alex.williamson@hp.com>
date Thu May 31 11:40:14 2007 -0600 (2007-05-31)
parents 7476a0ea8ee4
children 148b6fc8f29b
files xen/arch/ia64/xen/fw_emul.c xen/arch/ia64/xen/ivt.S xen/arch/ia64/xen/vcpu.c xen/include/asm-ia64/config.h
line diff
     1.1 --- a/xen/arch/ia64/xen/fw_emul.c	Thu May 31 11:37:38 2007 -0600
     1.2 +++ b/xen/arch/ia64/xen/fw_emul.c	Thu May 31 11:40:14 2007 -0600
     1.3 @@ -559,13 +559,8 @@ xen_pal_emulator(unsigned long index, u6
     1.4  				   .hash_tag_id = 0x30,
     1.5  				   .max_dtr_entry = NDTRS - 1,
     1.6  				   .max_itr_entry = NITRS - 1,
     1.7 -#ifdef VHPT_GLOBAL
     1.8  				   .max_unique_tcs = 3,
     1.9  				   .num_tc_levels = 2
    1.10 -#else
    1.11 -				   .max_unique_tcs = 2,
    1.12 -				   .num_tc_levels = 1
    1.13 -#endif
    1.14  				 }};
    1.15  			pal_vm_info_2_u_t v2;
    1.16  			v2.pvi2_val = 0;
    1.17 @@ -583,7 +578,6 @@ xen_pal_emulator(unsigned long index, u6
    1.18  			                          (pal_tc_info_u_t *)&r9, &r10);
    1.19  			break;
    1.20  		}
    1.21 -#ifdef VHPT_GLOBAL
    1.22  		if (in1 == 0 && in2 == 2) {
    1.23  			/* Level 1: VHPT  */
    1.24  			const pal_tc_info_u_t v =
    1.25 @@ -599,16 +593,8 @@ xen_pal_emulator(unsigned long index, u6
    1.26  			r10 = PAGE_SIZE;
    1.27  			status = PAL_STATUS_SUCCESS;
    1.28  		}
    1.29 -#endif
    1.30 -	        else if (
    1.31 -#ifdef VHPT_GLOBAL 
    1.32 -	                in1 == 1 /* Level 2. */
    1.33 -#else
    1.34 -			in1 == 0 /* Level 1. */
    1.35 -#endif
    1.36 -			 && (in2 == 1 || in2 == 2))
    1.37 -		{
    1.38 -			/* itlb/dtlb, 1 entry.  */
    1.39 +	        else if (in1 == 1 && (in2 == 1 || in2 == 2)) {
    1.40 +			/* Level 2: itlb/dtlb, 1 entry.  */
    1.41  			const pal_tc_info_u_t v =
    1.42  				{ .pal_tc_info_s = {.num_sets = 1,
    1.43  						    .associativity = 1,
     2.1 --- a/xen/arch/ia64/xen/ivt.S	Thu May 31 11:37:38 2007 -0600
     2.2 +++ b/xen/arch/ia64/xen/ivt.S	Thu May 31 11:40:14 2007 -0600
     2.3 @@ -126,48 +126,8 @@ ENTRY(itlb_miss)
     2.4  	;;
     2.5  	mov pr = r31, 0x1ffff
     2.6  	;;							
     2.7 -#ifdef VHPT_GLOBAL
     2.8  	br.cond.sptk fast_tlb_miss_reflect
     2.9  	;;
    2.10 -#endif
    2.11 -	/*
    2.12 -	 * The ITLB handler accesses the L3 PTE via the virtually mapped linear
    2.13 -	 * page table.  If a nested TLB miss occurs, we switch into physical
    2.14 -	 * mode, walk the page table, and then re-execute the L3 PTE read
    2.15 -	 * and go on normally after that.
    2.16 -	 */
    2.17 -	mov r16=cr.ifa				// get virtual address
    2.18 -	mov r29=b0				// save b0
    2.19 -	mov r31=pr				// save predicates
    2.20 -.itlb_fault:
    2.21 -	mov r17=cr.iha				// get virtual address of L3 PTE
    2.22 -	movl r30=1f				// load nested fault 
    2.23 -						//   continuation point
    2.24 -	;;
    2.25 -1:	ld8 r18=[r17]				// read L3 PTE
    2.26 -	;;
    2.27 -	mov b0=r29
    2.28 -	tbit.z p6,p0=r18,_PAGE_P_BIT		// page present bit cleared?
    2.29 -(p6)	br.cond.spnt page_fault
    2.30 -	;;
    2.31 -	itc.i r18
    2.32 -	;;
    2.33 -#ifdef CONFIG_SMP
    2.34 -	/*
    2.35 -	 * Tell the assemblers dependency-violation checker that the above
    2.36 -	 * "itc" instructions cannot possibly affect the following loads:
    2.37 -	 */
    2.38 -	dv_serialize_data
    2.39 -
    2.40 -	ld8 r19=[r17]			// read L3 PTE again and see if same
    2.41 -	mov r20=PAGE_SHIFT<<2		// setup page size for purge
    2.42 -	;;
    2.43 -	cmp.ne p7,p0=r18,r19
    2.44 -	;;
    2.45 -(p7)	ptc.l r16,r20
    2.46 -#endif
    2.47 -	mov pr=r31,-1
    2.48 -	rfi
    2.49  END(itlb_miss)
    2.50  
    2.51  	.org ia64_ivt+0x0800
    2.52 @@ -242,12 +202,8 @@ 1:
    2.53  
    2.54  2:
    2.55  #endif	
    2.56 -#ifdef VHPT_GLOBAL
    2.57 -//	br.cond.sptk page_fault
    2.58  	br.cond.sptk fast_tlb_miss_reflect
    2.59  	;;
    2.60 -#endif
    2.61 -	mov r29=b0				// save b0
    2.62  dtlb_fault:
    2.63  	mov r17=cr.iha				// get virtual address of L3 PTE
    2.64  	movl r30=1f				// load nested fault 
     3.1 --- a/xen/arch/ia64/xen/vcpu.c	Thu May 31 11:37:38 2007 -0600
     3.2 +++ b/xen/arch/ia64/xen/vcpu.c	Thu May 31 11:40:14 2007 -0600
     3.3 @@ -2222,7 +2222,6 @@ vcpu_itc_no_srlz(VCPU * vcpu, u64 IorD, 
     3.4  	ia64_itc(IorD, vaddr, pte, ps);	// FIXME: look for bigger mappings
     3.5  	ia64_set_psr(psr);
     3.6  	// ia64_srlz_i(); // no srls req'd, will rfi later
     3.7 -#ifdef VHPT_GLOBAL
     3.8  	if (vcpu->domain == dom0 && ((vaddr >> 61) == 7)) {
     3.9  		// FIXME: this is dangerous... vhpt_flush_address ensures these
    3.10  		// addresses never get flushed.  More work needed if this
    3.11 @@ -2237,7 +2236,6 @@ vcpu_itc_no_srlz(VCPU * vcpu, u64 IorD, 
    3.12  	// PAGE_SIZE mapping in the vhpt for now, else purging is complicated
    3.13  	else
    3.14  		vhpt_insert(vaddr, pte, PAGE_SHIFT << 2);
    3.15 -#endif
    3.16  }
    3.17  
    3.18  IA64FAULT vcpu_itc_d(VCPU * vcpu, u64 pte, u64 itir, u64 ifa)
     4.1 --- a/xen/include/asm-ia64/config.h	Thu May 31 11:37:38 2007 -0600
     4.2 +++ b/xen/include/asm-ia64/config.h	Thu May 31 11:40:14 2007 -0600
     4.3 @@ -1,8 +1,6 @@
     4.4  #ifndef	_IA64_CONFIG_H_
     4.5  #define _IA64_CONFIG_H_
     4.6  
     4.7 -#define VHPT_GLOBAL
     4.8 -
     4.9  #undef DEBUG_PFMON
    4.10  
    4.11  // manufactured from component pieces