1.1 --- a/xen/arch/x86/hvm/vioapic.c	Fri Nov 10 10:30:38 2006 +0000
     1.2 +++ b/xen/arch/x86/hvm/vioapic.c	Fri Nov 10 10:31:29 2006 +0000
     1.3 @@ -504,6 +504,7 @@ void vioapic_set_xen_irq(struct domain *
     1.4  void vioapic_set_irq(struct domain *d, int irq, int level)
     1.5  {
     1.6      struct vioapic *vioapic = domain_vioapic(d);
     1.7 +    uint32_t bit;
     1.8  
     1.9      HVM_DBG_LOG(DBG_LEVEL_IOAPIC, "ioapic_set_irq "
    1.10                  "irq %x level %x\n", irq, level);
    1.11 @@ -528,22 +529,19 @@ void vioapic_set_irq(struct domain *d, i
    1.12                  vioapic->redirtbl[irq].fields.mask,
    1.13                  vioapic->redirtbl[irq].fields.dest_id);
    1.14  
    1.15 -    if ( (irq >= 0) && (irq < VIOAPIC_NUM_PINS) )
    1.16 +    bit = 1 << irq;
    1.17 +    if ( vioapic->redirtbl[irq].fields.trig_mode == VIOAPIC_LEVEL_TRIG )
    1.18      {
    1.19 -        uint32_t bit = 1 << irq;
    1.20 -        if ( vioapic->redirtbl[irq].fields.trig_mode == VIOAPIC_LEVEL_TRIG )
    1.21 -        {
    1.22 -            if ( level )
    1.23 -                vioapic->irr |= bit;
    1.24 -            else
    1.25 -                vioapic->irr &= ~bit;
    1.26 -        }
    1.27 +        if ( level )
    1.28 +            vioapic->irr |= bit;
    1.29          else
    1.30 -        {
    1.31 -            if ( level )
    1.32 -                /* XXX No irr clear for edge interrupt */
    1.33 -                vioapic->irr |= bit;
    1.34 -        }
    1.35 +            vioapic->irr &= ~bit;
    1.36 +    }
    1.37 +    else
    1.38 +    {
    1.39 +        if ( level )
    1.40 +            /* XXX No irr clear for edge interrupt */
    1.41 +            vioapic->irr |= bit;
    1.42      }
    1.43  
    1.44      service_ioapic(vioapic);