1.1 --- a/xen/arch/x86/cpu/mcheck/mce_intel.c	Tue Mar 31 13:11:56 2009 +0100
     1.2 +++ b/xen/arch/x86/cpu/mcheck/mce_intel.c	Tue Mar 31 13:12:35 2009 +0100
     1.3 @@ -117,6 +117,16 @@ static void intel_init_thermal(struct cp
     1.4  }
     1.5  #endif /* CONFIG_X86_MCE_THERMAL */
     1.6  
     1.7 +static inline void intel_get_extended_msr(struct mcinfo_extended *ext, u32 msr)
     1.8 +{
     1.9 +    if ( ext->mc_msrs < ARRAY_SIZE(ext->mc_msr)
    1.10 +         && msr < MSR_IA32_MCG_EAX + nr_intel_ext_msrs ) {
    1.11 +        ext->mc_msr[ext->mc_msrs].reg = msr;
    1.12 +        rdmsrl(msr, ext->mc_msr[ext->mc_msrs].value);
    1.13 +        ++ext->mc_msrs;
    1.14 +    }
    1.15 +}
    1.16 +
    1.17  static enum mca_extinfo
    1.18  intel_get_extended_msrs(struct mc_info *mci, uint16_t bank, uint64_t status)
    1.19  {
    1.20 @@ -129,30 +139,29 @@ intel_get_extended_msrs(struct mc_info *
    1.21      memset(&mc_ext, 0, sizeof(struct mcinfo_extended));
    1.22      mc_ext.common.type = MC_TYPE_EXTENDED;
    1.23      mc_ext.common.size = sizeof(mc_ext);
    1.24 -    mc_ext.mc_msrs = 10;
    1.25 -
    1.26 -    mc_ext.mc_msr[0].reg = MSR_IA32_MCG_EAX;
    1.27 -    rdmsrl(MSR_IA32_MCG_EAX, mc_ext.mc_msr[0].value);
    1.28 -    mc_ext.mc_msr[1].reg = MSR_IA32_MCG_EBX;
    1.29 -    rdmsrl(MSR_IA32_MCG_EBX, mc_ext.mc_msr[1].value);
    1.30 -    mc_ext.mc_msr[2].reg = MSR_IA32_MCG_ECX;
    1.31 -    rdmsrl(MSR_IA32_MCG_ECX, mc_ext.mc_msr[2].value);
    1.32  
    1.33 -    mc_ext.mc_msr[3].reg = MSR_IA32_MCG_EDX;
    1.34 -    rdmsrl(MSR_IA32_MCG_EDX, mc_ext.mc_msr[3].value);
    1.35 -    mc_ext.mc_msr[4].reg = MSR_IA32_MCG_ESI;
    1.36 -    rdmsrl(MSR_IA32_MCG_ESI, mc_ext.mc_msr[4].value);
    1.37 -    mc_ext.mc_msr[5].reg = MSR_IA32_MCG_EDI;
    1.38 -    rdmsrl(MSR_IA32_MCG_EDI, mc_ext.mc_msr[5].value);
    1.39 +    intel_get_extended_msr(&mc_ext, MSR_IA32_MCG_EAX);
    1.40 +    intel_get_extended_msr(&mc_ext, MSR_IA32_MCG_EBX);
    1.41 +    intel_get_extended_msr(&mc_ext, MSR_IA32_MCG_ECX);
    1.42 +    intel_get_extended_msr(&mc_ext, MSR_IA32_MCG_EDX);
    1.43 +    intel_get_extended_msr(&mc_ext, MSR_IA32_MCG_ESI);
    1.44 +    intel_get_extended_msr(&mc_ext, MSR_IA32_MCG_EDI);
    1.45 +    intel_get_extended_msr(&mc_ext, MSR_IA32_MCG_EBP);
    1.46 +    intel_get_extended_msr(&mc_ext, MSR_IA32_MCG_ESP);
    1.47 +    intel_get_extended_msr(&mc_ext, MSR_IA32_MCG_EFLAGS);
    1.48 +    intel_get_extended_msr(&mc_ext, MSR_IA32_MCG_EIP);
    1.49 +    intel_get_extended_msr(&mc_ext, MSR_IA32_MCG_MISC);
    1.50  
    1.51 -    mc_ext.mc_msr[6].reg = MSR_IA32_MCG_EBP;
    1.52 -    rdmsrl(MSR_IA32_MCG_EBP, mc_ext.mc_msr[6].value);
    1.53 -    mc_ext.mc_msr[7].reg = MSR_IA32_MCG_ESP;
    1.54 -    rdmsrl(MSR_IA32_MCG_ESP, mc_ext.mc_msr[7].value);
    1.55 -    mc_ext.mc_msr[8].reg = MSR_IA32_MCG_EFLAGS;
    1.56 -    rdmsrl(MSR_IA32_MCG_EFLAGS, mc_ext.mc_msr[8].value);
    1.57 -    mc_ext.mc_msr[9].reg = MSR_IA32_MCG_EIP;
    1.58 -    rdmsrl(MSR_IA32_MCG_EIP, mc_ext.mc_msr[9].value);
    1.59 +#ifdef __x86_64__
    1.60 +    intel_get_extended_msr(&mc_ext, MSR_IA32_MCG_R8);
    1.61 +    intel_get_extended_msr(&mc_ext, MSR_IA32_MCG_R9);
    1.62 +    intel_get_extended_msr(&mc_ext, MSR_IA32_MCG_R10);
    1.63 +    intel_get_extended_msr(&mc_ext, MSR_IA32_MCG_R11);
    1.64 +    intel_get_extended_msr(&mc_ext, MSR_IA32_MCG_R12);
    1.65 +    intel_get_extended_msr(&mc_ext, MSR_IA32_MCG_R13);
    1.66 +    intel_get_extended_msr(&mc_ext, MSR_IA32_MCG_R14);
    1.67 +    intel_get_extended_msr(&mc_ext, MSR_IA32_MCG_R15);
    1.68 +#endif
    1.69  
    1.70      x86_mcinfo_add(mci, &mc_ext);
    1.71  

     2.1 --- a/xen/include/asm-x86/msr-index.h	Tue Mar 31 13:11:56 2009 +0100
     2.2 +++ b/xen/include/asm-x86/msr-index.h	Tue Mar 31 13:12:35 2009 +0100
     2.3 @@ -326,7 +326,15 @@
     2.4  #define MSR_IA32_MCG_ESP		0x00000187
     2.5  #define MSR_IA32_MCG_EFLAGS		0x00000188
     2.6  #define MSR_IA32_MCG_EIP		0x00000189
     2.7 -#define MSR_IA32_MCG_RESERVED		0x0000018a
     2.8 +#define MSR_IA32_MCG_MISC		0x0000018a
     2.9 +#define MSR_IA32_MCG_R8			0x00000190
    2.10 +#define MSR_IA32_MCG_R9			0x00000191
    2.11 +#define MSR_IA32_MCG_R10		0x00000192
    2.12 +#define MSR_IA32_MCG_R11		0x00000193
    2.13 +#define MSR_IA32_MCG_R12		0x00000194
    2.14 +#define MSR_IA32_MCG_R13		0x00000195
    2.15 +#define MSR_IA32_MCG_R14		0x00000196
    2.16 +#define MSR_IA32_MCG_R15		0x00000197
    2.17  
    2.18  /* Pentium IV performance counter MSRs */
    2.19  #define MSR_P4_BPU_PERFCTR0		0x00000300

     3.1 --- a/xen/include/public/arch-x86/xen-mca.h	Tue Mar 31 13:11:56 2009 +0100
     3.2 +++ b/xen/include/public/arch-x86/xen-mca.h	Tue Mar 31 13:12:35 2009 +0100
     3.3 @@ -166,11 +166,11 @@ struct mcinfo_extended {
     3.4  
     3.5      uint32_t mc_msrs; /* Number of msr with valid values. */
     3.6      /*
     3.7 -     * Currently Intel extended MSR (32/64) including all gp registers
     3.8 -     * and E(R)DI, E(R)BP, E(R)SP, E(R)FLAGS, E(R)IP, E(R)MISC, only 10
     3.9 -     * of them might be useful. So expend this array to 10.
    3.10 -    */
    3.11 -    struct mcinfo_msr mc_msr[10];
    3.12 +     * Currently Intel extended MSR (32/64) include all gp registers
    3.13 +     * and E(R)FLAGS, E(R)IP, E(R)MISC, up to 11/19 of them might be
    3.14 +     * useful at present. So expand this array to 16/32 to leave room.
    3.15 +     */
    3.16 +    struct mcinfo_msr mc_msr[sizeof(void *) * 4];
    3.17  };
    3.18  
    3.19  /* Recovery Action flags. Giving recovery result information to DOM0 */