ia64/xen-unstable

view linux-2.6-xen-sparse/arch/ia64/xen/xenivt.S @ 9296:f85bb99187bf

Update interface documentation to include sched_op_new hypercall
and clean up the style a bit. Also clean up the sched_op_new
description in the sched.h public header.

Signed-off-by: Keir Fraser <keir@xensource.com>
author kaf24@firebug.cl.cam.ac.uk
date Wed Mar 15 19:19:22 2006 +0100 (2006-03-15)
parents 3b9c2c410b14
children bbfbb9e09b55
line source
1 /*
2 * arch/ia64/xen/ivt.S
3 *
4 * Copyright (C) 2005 Hewlett-Packard Co
5 * Dan Magenheimer <dan.magenheimer@hp.com>
6 */
7 /*
8 * This file defines the interruption vector table used by the CPU.
9 * It does not include one entry per possible cause of interruption.
10 *
11 * The first 20 entries of the table contain 64 bundles each while the
12 * remaining 48 entries contain only 16 bundles each.
13 *
14 * The 64 bundles are used to allow inlining the whole handler for critical
15 * interruptions like TLB misses.
16 *
17 * For each entry, the comment is as follows:
18 *
19 * // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
20 * entry offset ----/ / / / /
21 * entry number ---------/ / / /
22 * size of the entry -------------/ / /
23 * vector name -------------------------------------/ /
24 * interruptions triggering this vector ----------------------/
25 *
26 * The table is 32KB in size and must be aligned on 32KB boundary.
27 * (The CPU ignores the 15 lower bits of the address)
28 *
29 * Table is based upon EAS2.6 (Oct 1999)
30 */
32 #include <linux/config.h>
34 #include <asm/asmmacro.h>
35 #include <asm/break.h>
36 #include <asm/ia32.h>
37 #include <asm/kregs.h>
38 #include <asm/asm-offsets.h>
39 #include <asm/pgtable.h>
40 #include <asm/processor.h>
41 #include <asm/ptrace.h>
42 #include <asm/system.h>
43 #include <asm/thread_info.h>
44 #include <asm/unistd.h>
45 #include <asm/errno.h>
47 #ifdef CONFIG_XEN
48 #define ia64_ivt xen_ivt
49 #endif
51 #if 1
52 # define PSR_DEFAULT_BITS psr.ac
53 #else
54 # define PSR_DEFAULT_BITS 0
55 #endif
57 #if 0
58 /*
59 * This lets you track the last eight faults that occurred on the CPU. Make sure ar.k2 isn't
60 * needed for something else before enabling this...
61 */
62 # define DBG_FAULT(i) mov r16=ar.k2;; shl r16=r16,8;; add r16=(i),r16;;mov ar.k2=r16
63 #else
64 # define DBG_FAULT(i)
65 #endif
67 #define MINSTATE_VIRT /* needed by minstate.h */
68 #include "xenminstate.h"
70 #define FAULT(n) \
71 mov r31=pr; \
72 mov r19=n;; /* prepare to save predicates */ \
73 br.sptk.many dispatch_to_fault_handler
75 .section .text.ivt,"ax"
77 .align 32768 // align on 32KB boundary
78 .global ia64_ivt
79 ia64_ivt:
80 /////////////////////////////////////////////////////////////////////////////////////////
81 // 0x0000 Entry 0 (size 64 bundles) VHPT Translation (8,20,47)
82 ENTRY(vhpt_miss)
83 DBG_FAULT(0)
84 /*
85 * The VHPT vector is invoked when the TLB entry for the virtual page table
86 * is missing. This happens only as a result of a previous
87 * (the "original") TLB miss, which may either be caused by an instruction
88 * fetch or a data access (or non-access).
89 *
90 * What we do here is normal TLB miss handing for the _original_ miss, followed
91 * by inserting the TLB entry for the virtual page table page that the VHPT
92 * walker was attempting to access. The latter gets inserted as long
93 * as both L1 and L2 have valid mappings for the faulting address.
94 * The TLB entry for the original miss gets inserted only if
95 * the L3 entry indicates that the page is present.
96 *
97 * do_page_fault gets invoked in the following cases:
98 * - the faulting virtual address uses unimplemented address bits
99 * - the faulting virtual address has no L1, L2, or L3 mapping
100 */
101 #ifdef CONFIG_XEN
102 movl r16=XSI_IFA
103 ;;
104 ld8 r16=[r16]
105 #ifdef CONFIG_HUGETLB_PAGE
106 movl r18=PAGE_SHIFT
107 movl r25=XSI_ITIR
108 ;;
109 ld8 r25=[r25]
110 #endif
111 ;;
112 #else
113 mov r16=cr.ifa // get address that caused the TLB miss
114 #ifdef CONFIG_HUGETLB_PAGE
115 movl r18=PAGE_SHIFT
116 mov r25=cr.itir
117 #endif
118 #endif
119 ;;
120 #ifdef CONFIG_XEN
121 XEN_HYPER_RSM_PSR_DT;
122 #else
123 rsm psr.dt // use physical addressing for data
124 #endif
125 mov r31=pr // save the predicate registers
126 mov r19=IA64_KR(PT_BASE) // get page table base address
127 shl r21=r16,3 // shift bit 60 into sign bit
128 shr.u r17=r16,61 // get the region number into r17
129 ;;
130 shr r22=r21,3
131 #ifdef CONFIG_HUGETLB_PAGE
132 extr.u r26=r25,2,6
133 ;;
134 cmp.ne p8,p0=r18,r26
135 sub r27=r26,r18
136 ;;
137 (p8) dep r25=r18,r25,2,6
138 (p8) shr r22=r22,r27
139 #endif
140 ;;
141 cmp.eq p6,p7=5,r17 // is IFA pointing into to region 5?
142 shr.u r18=r22,PGDIR_SHIFT // get bits 33-63 of the faulting address
143 ;;
144 (p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place
146 srlz.d
147 LOAD_PHYSICAL(p6, r19, swapper_pg_dir) // region 5 is rooted at swapper_pg_dir
149 .pred.rel "mutex", p6, p7
150 (p6) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT
151 (p7) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT-3
152 ;;
153 (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=PTA + IFA(33,42)*8
154 (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=PTA + (((IFA(61,63) << 7) | IFA(33,39))*8)
155 cmp.eq p7,p6=0,r21 // unused address bits all zeroes?
156 shr.u r18=r22,PMD_SHIFT // shift L2 index into position
157 ;;
158 ld8 r17=[r17] // fetch the L1 entry (may be 0)
159 ;;
160 (p7) cmp.eq p6,p7=r17,r0 // was L1 entry NULL?
161 dep r17=r18,r17,3,(PAGE_SHIFT-3) // compute address of L2 page table entry
162 ;;
163 (p7) ld8 r20=[r17] // fetch the L2 entry (may be 0)
164 shr.u r19=r22,PAGE_SHIFT // shift L3 index into position
165 ;;
166 (p7) cmp.eq.or.andcm p6,p7=r20,r0 // was L2 entry NULL?
167 dep r21=r19,r20,3,(PAGE_SHIFT-3) // compute address of L3 page table entry
168 ;;
169 #ifdef CONFIG_XEN
170 (p7) ld8 r18=[r21] // read the L3 PTE
171 movl r19=XSI_ISR
172 ;;
173 ld8 r19=[r19]
174 ;;
175 (p7) tbit.z p6,p7=r18,_PAGE_P_BIT // page present bit cleared?
176 movl r22=XSI_IHA
177 ;;
178 ld8 r22=[r22]
179 ;;
180 #else
181 (p7) ld8 r18=[r21] // read the L3 PTE
182 mov r19=cr.isr // cr.isr bit 0 tells us if this is an insn miss
183 ;;
184 (p7) tbit.z p6,p7=r18,_PAGE_P_BIT // page present bit cleared?
185 mov r22=cr.iha // get the VHPT address that caused the TLB miss
186 ;; // avoid RAW on p7
187 #endif
188 (p7) tbit.nz.unc p10,p11=r19,32 // is it an instruction TLB miss?
189 dep r23=0,r20,0,PAGE_SHIFT // clear low bits to get page address
190 ;;
191 #ifdef CONFIG_XEN
192 mov r24=r8
193 mov r8=r18
194 ;;
195 (p10) XEN_HYPER_ITC_D
196 ;;
197 (p11) XEN_HYPER_ITC_I
198 ;;
199 mov r8=r24
200 ;;
201 (p6) br.cond.spnt.many page_fault // handle bad address/page not present (page fault)
202 ;;
203 movl r24=XSI_IFA
204 ;;
205 st8 [r24]=r22
206 ;;
207 #else
208 (p10) itc.i r18 // insert the instruction TLB entry
209 (p11) itc.d r18 // insert the data TLB entry
210 (p6) br.cond.spnt.many page_fault // handle bad address/page not present (page fault)
211 mov cr.ifa=r22
212 #endif
214 #ifdef CONFIG_HUGETLB_PAGE
215 (p8) mov cr.itir=r25 // change to default page-size for VHPT
216 #endif
218 /*
219 * Now compute and insert the TLB entry for the virtual page table. We never
220 * execute in a page table page so there is no need to set the exception deferral
221 * bit.
222 */
223 adds r24=__DIRTY_BITS_NO_ED|_PAGE_PL_0|_PAGE_AR_RW,r23
224 ;;
225 #ifdef CONFIG_XEN
226 (p7) mov r25=r8
227 (p7) mov r8=r24
228 ;;
229 (p7) XEN_HYPER_ITC_D
230 ;;
231 (p7) mov r8=r25
232 ;;
233 #else
234 (p7) itc.d r24
235 #endif
236 ;;
237 #ifdef CONFIG_SMP
238 /*
239 * Tell the assemblers dependency-violation checker that the above "itc" instructions
240 * cannot possibly affect the following loads:
241 */
242 dv_serialize_data
244 /*
245 * Re-check L2 and L3 pagetable. If they changed, we may have received a ptc.g
246 * between reading the pagetable and the "itc". If so, flush the entry we
247 * inserted and retry.
248 */
249 ld8 r25=[r21] // read L3 PTE again
250 ld8 r26=[r17] // read L2 entry again
251 ;;
252 cmp.ne p6,p7=r26,r20 // did L2 entry change
253 mov r27=PAGE_SHIFT<<2
254 ;;
255 (p6) ptc.l r22,r27 // purge PTE page translation
256 (p7) cmp.ne.or.andcm p6,p7=r25,r18 // did L3 PTE change
257 ;;
258 (p6) ptc.l r16,r27 // purge translation
259 #endif
261 mov pr=r31,-1 // restore predicate registers
262 #ifdef CONFIG_XEN
263 XEN_HYPER_RFI;
264 #else
265 rfi
266 #endif
267 END(vhpt_miss)
269 .org ia64_ivt+0x400
270 /////////////////////////////////////////////////////////////////////////////////////////
271 // 0x0400 Entry 1 (size 64 bundles) ITLB (21)
272 ENTRY(itlb_miss)
273 DBG_FAULT(1)
274 /*
275 * The ITLB handler accesses the L3 PTE via the virtually mapped linear
276 * page table. If a nested TLB miss occurs, we switch into physical
277 * mode, walk the page table, and then re-execute the L3 PTE read
278 * and go on normally after that.
279 */
280 #ifdef CONFIG_XEN
281 movl r16=XSI_IFA
282 ;;
283 ld8 r16=[r16]
284 #else
285 mov r16=cr.ifa // get virtual address
286 #endif
287 mov r29=b0 // save b0
288 mov r31=pr // save predicates
289 .itlb_fault:
290 #ifdef CONFIG_XEN
291 movl r17=XSI_IHA
292 ;;
293 ld8 r17=[r17] // get virtual address of L3 PTE
294 #else
295 mov r17=cr.iha // get virtual address of L3 PTE
296 #endif
297 movl r30=1f // load nested fault continuation point
298 ;;
299 1: ld8 r18=[r17] // read L3 PTE
300 ;;
301 mov b0=r29
302 tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared?
303 (p6) br.cond.spnt page_fault
304 ;;
305 #ifdef CONFIG_XEN
306 mov r19=r8
307 mov r8=r18
308 ;;
309 XEN_HYPER_ITC_I
310 ;;
311 mov r8=r19
312 #else
313 itc.i r18
314 #endif
315 ;;
316 #ifdef CONFIG_SMP
317 /*
318 * Tell the assemblers dependency-violation checker that the above "itc" instructions
319 * cannot possibly affect the following loads:
320 */
321 dv_serialize_data
323 ld8 r19=[r17] // read L3 PTE again and see if same
324 mov r20=PAGE_SHIFT<<2 // setup page size for purge
325 ;;
326 cmp.ne p7,p0=r18,r19
327 ;;
328 (p7) ptc.l r16,r20
329 #endif
330 mov pr=r31,-1
331 #ifdef CONFIG_XEN
332 XEN_HYPER_RFI;
333 #else
334 rfi
335 #endif
336 END(itlb_miss)
338 .org ia64_ivt+0x0800
339 /////////////////////////////////////////////////////////////////////////////////////////
340 // 0x0800 Entry 2 (size 64 bundles) DTLB (9,48)
341 ENTRY(dtlb_miss)
342 DBG_FAULT(2)
343 /*
344 * The DTLB handler accesses the L3 PTE via the virtually mapped linear
345 * page table. If a nested TLB miss occurs, we switch into physical
346 * mode, walk the page table, and then re-execute the L3 PTE read
347 * and go on normally after that.
348 */
349 #ifdef CONFIG_XEN
350 movl r16=XSI_IFA
351 ;;
352 ld8 r16=[r16]
353 #else
354 mov r16=cr.ifa // get virtual address
355 #endif
356 mov r29=b0 // save b0
357 mov r31=pr // save predicates
358 dtlb_fault:
359 #ifdef CONFIG_XEN
360 movl r17=XSI_IHA
361 ;;
362 ld8 r17=[r17] // get virtual address of L3 PTE
363 #else
364 mov r17=cr.iha // get virtual address of L3 PTE
365 #endif
366 movl r30=1f // load nested fault continuation point
367 ;;
368 1: ld8 r18=[r17] // read L3 PTE
369 ;;
370 mov b0=r29
371 tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared?
372 (p6) br.cond.spnt page_fault
373 ;;
374 #ifdef CONFIG_XEN
375 mov r19=r8
376 mov r8=r18
377 ;;
378 XEN_HYPER_ITC_D
379 ;;
380 mov r8=r19
381 ;;
382 #else
383 itc.d r18
384 #endif
385 ;;
386 #ifdef CONFIG_SMP
387 /*
388 * Tell the assemblers dependency-violation checker that the above "itc" instructions
389 * cannot possibly affect the following loads:
390 */
391 dv_serialize_data
393 ld8 r19=[r17] // read L3 PTE again and see if same
394 mov r20=PAGE_SHIFT<<2 // setup page size for purge
395 ;;
396 cmp.ne p7,p0=r18,r19
397 ;;
398 (p7) ptc.l r16,r20
399 #endif
400 mov pr=r31,-1
401 #ifdef CONFIG_XEN
402 XEN_HYPER_RFI;
403 #else
404 rfi
405 #endif
406 END(dtlb_miss)
408 .org ia64_ivt+0x0c00
409 /////////////////////////////////////////////////////////////////////////////////////////
410 // 0x0c00 Entry 3 (size 64 bundles) Alt ITLB (19)
411 ENTRY(alt_itlb_miss)
412 DBG_FAULT(3)
413 #ifdef CONFIG_XEN
414 movl r31=XSI_IPSR
415 ;;
416 ld8 r21=[r31],XSI_IFA-XSI_IPSR // get ipsr, point to ifa
417 movl r17=PAGE_KERNEL
418 ;;
419 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
420 ;;
421 ld8 r16=[r31] // get ifa
422 mov r31=pr
423 ;;
424 #else
425 mov r16=cr.ifa // get address that caused the TLB miss
426 movl r17=PAGE_KERNEL
427 mov r21=cr.ipsr
428 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
429 mov r31=pr
430 ;;
431 #endif
432 #ifdef CONFIG_DISABLE_VHPT
433 shr.u r22=r16,61 // get the region number into r21
434 ;;
435 cmp.gt p8,p0=6,r22 // user mode
436 ;;
437 #ifndef CONFIG_XEN
438 (p8) thash r17=r16
439 ;;
440 (p8) mov cr.iha=r17
441 #endif
442 (p8) mov r29=b0 // save b0
443 (p8) br.cond.dptk .itlb_fault
444 #endif
445 extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl
446 and r19=r19,r16 // clear ed, reserved bits, and PTE control bits
447 shr.u r18=r16,57 // move address bit 61 to bit 4
448 ;;
449 andcm r18=0x10,r18 // bit 4=~address-bit(61)
450 cmp.ne p8,p0=r0,r23 // psr.cpl != 0?
451 or r19=r17,r19 // insert PTE control bits into r19
452 ;;
453 or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6
454 (p8) br.cond.spnt page_fault
455 ;;
456 #ifdef CONFIG_XEN
457 mov r18=r8
458 mov r8=r19
459 ;;
460 XEN_HYPER_ITC_I
461 ;;
462 mov r8=r18
463 ;;
464 mov pr=r31,-1
465 ;;
466 XEN_HYPER_RFI;
467 #else
468 itc.i r19 // insert the TLB entry
469 mov pr=r31,-1
470 rfi
471 #endif
472 END(alt_itlb_miss)
474 .org ia64_ivt+0x1000
475 /////////////////////////////////////////////////////////////////////////////////////////
476 // 0x1000 Entry 4 (size 64 bundles) Alt DTLB (7,46)
477 ENTRY(alt_dtlb_miss)
478 DBG_FAULT(4)
479 #ifdef CONFIG_XEN
480 movl r31=XSI_IPSR
481 ;;
482 ld8 r21=[r31],XSI_ISR-XSI_IPSR // get ipsr, point to isr
483 movl r17=PAGE_KERNEL
484 ;;
485 ld8 r20=[r31],XSI_IFA-XSI_ISR // get isr, point to ifa
486 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
487 ;;
488 ld8 r16=[r31] // get ifa
489 mov r31=pr
490 ;;
491 #else
492 mov r16=cr.ifa // get address that caused the TLB miss
493 movl r17=PAGE_KERNEL
494 mov r20=cr.isr
495 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
496 mov r21=cr.ipsr
497 mov r31=pr
498 ;;
499 #endif
500 #ifdef CONFIG_DISABLE_VHPT
501 shr.u r22=r16,61 // get the region number into r21
502 ;;
503 cmp.gt p8,p0=6,r22 // access to region 0-5
504 ;;
505 #ifndef CONFIG_XEN
506 (p8) thash r17=r16
507 ;;
508 (p8) mov cr.iha=r17
509 #endif
510 (p8) mov r29=b0 // save b0
511 (p8) br.cond.dptk dtlb_fault
512 #endif
513 extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl
514 and r22=IA64_ISR_CODE_MASK,r20 // get the isr.code field
515 tbit.nz p6,p7=r20,IA64_ISR_SP_BIT // is speculation bit on?
516 shr.u r18=r16,57 // move address bit 61 to bit 4
517 and r19=r19,r16 // clear ed, reserved bits, and PTE control bits
518 tbit.nz p9,p0=r20,IA64_ISR_NA_BIT // is non-access bit on?
519 ;;
520 andcm r18=0x10,r18 // bit 4=~address-bit(61)
521 cmp.ne p8,p0=r0,r23
522 (p9) cmp.eq.or.andcm p6,p7=IA64_ISR_CODE_LFETCH,r22 // check isr.code field
523 (p8) br.cond.spnt page_fault
525 dep r21=-1,r21,IA64_PSR_ED_BIT,1
526 or r19=r19,r17 // insert PTE control bits into r19
527 ;;
528 or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6
529 (p6) mov cr.ipsr=r21
530 ;;
531 #ifdef CONFIG_XEN
532 (p7) mov r18=r8
533 (p7) mov r8=r19
534 ;;
535 (p7) XEN_HYPER_ITC_D
536 ;;
537 (p7) mov r8=r18
538 ;;
539 mov pr=r31,-1
540 ;;
541 XEN_HYPER_RFI;
542 #else
543 (p7) itc.d r19 // insert the TLB entry
544 mov pr=r31,-1
545 rfi
546 #endif
547 END(alt_dtlb_miss)
549 .org ia64_ivt+0x1400
550 /////////////////////////////////////////////////////////////////////////////////////////
551 // 0x1400 Entry 5 (size 64 bundles) Data nested TLB (6,45)
552 ENTRY(nested_dtlb_miss)
553 /*
554 * In the absence of kernel bugs, we get here when the virtually mapped linear
555 * page table is accessed non-speculatively (e.g., in the Dirty-bit, Instruction
556 * Access-bit, or Data Access-bit faults). If the DTLB entry for the virtual page
557 * table is missing, a nested TLB miss fault is triggered and control is
558 * transferred to this point. When this happens, we lookup the pte for the
559 * faulting address by walking the page table in physical mode and return to the
560 * continuation point passed in register r30 (or call page_fault if the address is
561 * not mapped).
562 *
563 * Input: r16: faulting address
564 * r29: saved b0
565 * r30: continuation address
566 * r31: saved pr
567 *
568 * Output: r17: physical address of L3 PTE of faulting address
569 * r29: saved b0
570 * r30: continuation address
571 * r31: saved pr
572 *
573 * Clobbered: b0, r18, r19, r21, psr.dt (cleared)
574 */
575 #ifdef CONFIG_XEN
576 XEN_HYPER_RSM_PSR_DT;
577 #else
578 rsm psr.dt // switch to using physical data addressing
579 #endif
580 mov r19=IA64_KR(PT_BASE) // get the page table base address
581 shl r21=r16,3 // shift bit 60 into sign bit
582 ;;
583 shr.u r17=r16,61 // get the region number into r17
584 ;;
585 cmp.eq p6,p7=5,r17 // is faulting address in region 5?
586 shr.u r18=r16,PGDIR_SHIFT // get bits 33-63 of faulting address
587 ;;
588 (p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place
590 srlz.d
591 LOAD_PHYSICAL(p6, r19, swapper_pg_dir) // region 5 is rooted at swapper_pg_dir
593 .pred.rel "mutex", p6, p7
594 (p6) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT
595 (p7) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT-3
596 ;;
597 (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=PTA + IFA(33,42)*8
598 (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=PTA + (((IFA(61,63) << 7) | IFA(33,39))*8)
599 cmp.eq p7,p6=0,r21 // unused address bits all zeroes?
600 shr.u r18=r16,PMD_SHIFT // shift L2 index into position
601 ;;
602 ld8 r17=[r17] // fetch the L1 entry (may be 0)
603 ;;
604 (p7) cmp.eq p6,p7=r17,r0 // was L1 entry NULL?
605 dep r17=r18,r17,3,(PAGE_SHIFT-3) // compute address of L2 page table entry
606 ;;
607 (p7) ld8 r17=[r17] // fetch the L2 entry (may be 0)
608 shr.u r19=r16,PAGE_SHIFT // shift L3 index into position
609 ;;
610 (p7) cmp.eq.or.andcm p6,p7=r17,r0 // was L2 entry NULL?
611 dep r17=r19,r17,3,(PAGE_SHIFT-3) // compute address of L3 page table entry
612 (p6) br.cond.spnt page_fault
613 mov b0=r30
614 br.sptk.many b0 // return to continuation point
615 END(nested_dtlb_miss)
617 .org ia64_ivt+0x1800
618 /////////////////////////////////////////////////////////////////////////////////////////
619 // 0x1800 Entry 6 (size 64 bundles) Instruction Key Miss (24)
620 ENTRY(ikey_miss)
621 DBG_FAULT(6)
622 FAULT(6)
623 END(ikey_miss)
625 //-----------------------------------------------------------------------------------
626 // call do_page_fault (predicates are in r31, psr.dt may be off, r16 is faulting address)
627 ENTRY(page_fault)
628 #ifdef CONFIG_XEN
629 XEN_HYPER_SSM_PSR_DT;
630 #else
631 ssm psr.dt
632 ;;
633 srlz.i
634 #endif
635 ;;
636 SAVE_MIN_WITH_COVER
637 alloc r15=ar.pfs,0,0,3,0
638 #ifdef CONFIG_XEN
639 movl r3=XSI_ISR
640 ;;
641 ld8 out1=[r3],XSI_IFA-XSI_ISR // get vcr.isr, point to ifa
642 ;;
643 ld8 out0=[r3] // get vcr.ifa
644 mov r14=1
645 ;;
646 add r3=XSI_PSR_IC-XSI_IFA, r3 // point to vpsr.ic
647 ;;
648 st4 [r3]=r14 // vpsr.ic = 1
649 adds r3=8,r2 // set up second base pointer
650 ;;
651 #else
652 mov out0=cr.ifa
653 mov out1=cr.isr
654 adds r3=8,r2 // set up second base pointer
655 ;;
656 ssm psr.ic | PSR_DEFAULT_BITS
657 ;;
658 srlz.i // guarantee that interruption collectin is on
659 ;;
660 #endif
661 #ifdef CONFIG_XEN
662 br.cond.sptk.many xen_page_fault
663 ;;
664 done_xen_page_fault:
665 #endif
666 (p15) ssm psr.i // restore psr.i
667 movl r14=ia64_leave_kernel
668 ;;
669 SAVE_REST
670 mov rp=r14
671 ;;
672 adds out2=16,r12 // out2 = pointer to pt_regs
673 br.call.sptk.many b6=ia64_do_page_fault // ignore return address
674 END(page_fault)
676 .org ia64_ivt+0x1c00
677 /////////////////////////////////////////////////////////////////////////////////////////
678 // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
679 ENTRY(dkey_miss)
680 DBG_FAULT(7)
681 FAULT(7)
682 #ifdef CONFIG_XEN
683 // Leaving this code inline above results in an IVT section overflow
684 // There is no particular reason for this code to be here...
685 xen_page_fault:
686 (p15) movl r3=XSI_PSR_I
687 ;;
688 (p15) st4 [r3]=r14,XSI_PEND-XSI_PSR_I // if (p15) vpsr.i = 1
689 mov r14=r0
690 ;;
691 (p15) ld4 r14=[r3] // if (pending_interrupts)
692 adds r3=8,r2 // re-set up second base pointer
693 ;;
694 (p15) cmp.ne p15,p0=r14,r0
695 ;;
696 br.cond.sptk.many done_xen_page_fault
697 ;;
698 #endif
699 END(dkey_miss)
701 .org ia64_ivt+0x2000
702 /////////////////////////////////////////////////////////////////////////////////////////
703 // 0x2000 Entry 8 (size 64 bundles) Dirty-bit (54)
704 ENTRY(dirty_bit)
705 DBG_FAULT(8)
706 /*
707 * What we do here is to simply turn on the dirty bit in the PTE. We need to
708 * update both the page-table and the TLB entry. To efficiently access the PTE,
709 * we address it through the virtual page table. Most likely, the TLB entry for
710 * the relevant virtual page table page is still present in the TLB so we can
711 * normally do this without additional TLB misses. In case the necessary virtual
712 * page table TLB entry isn't present, we take a nested TLB miss hit where we look
713 * up the physical address of the L3 PTE and then continue at label 1 below.
714 */
715 #ifdef CONFIG_XEN
716 movl r16=XSI_IFA
717 ;;
718 ld8 r16=[r16]
719 ;;
720 #else
721 mov r16=cr.ifa // get the address that caused the fault
722 #endif
723 movl r30=1f // load continuation point in case of nested fault
724 ;;
725 #ifdef CONFIG_XEN
726 #if 1
727 mov r18=r8;
728 mov r8=r16;
729 XEN_HYPER_THASH;;
730 mov r17=r8;
731 mov r8=r18;;
732 #else
733 tak r17=r80 // "privified" thash
734 #endif
735 #else
736 thash r17=r16 // compute virtual address of L3 PTE
737 #endif
738 mov r29=b0 // save b0 in case of nested fault
739 mov r31=pr // save pr
740 #ifdef CONFIG_SMP
741 mov r28=ar.ccv // save ar.ccv
742 ;;
743 1: ld8 r18=[r17]
744 ;; // avoid RAW on r18
745 mov ar.ccv=r18 // set compare value for cmpxchg
746 or r25=_PAGE_D|_PAGE_A,r18 // set the dirty and accessed bits
747 ;;
748 cmpxchg8.acq r26=[r17],r25,ar.ccv
749 mov r24=PAGE_SHIFT<<2
750 ;;
751 cmp.eq p6,p7=r26,r18
752 ;;
753 (p6) itc.d r25 // install updated PTE
754 ;;
755 /*
756 * Tell the assemblers dependency-violation checker that the above "itc" instructions
757 * cannot possibly affect the following loads:
758 */
759 dv_serialize_data
761 ld8 r18=[r17] // read PTE again
762 ;;
763 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
764 ;;
765 (p7) ptc.l r16,r24
766 mov b0=r29 // restore b0
767 mov ar.ccv=r28
768 #else
769 ;;
770 1: ld8 r18=[r17]
771 ;; // avoid RAW on r18
772 or r18=_PAGE_D|_PAGE_A,r18 // set the dirty and accessed bits
773 mov b0=r29 // restore b0
774 ;;
775 st8 [r17]=r18 // store back updated PTE
776 itc.d r18 // install updated PTE
777 #endif
778 mov pr=r31,-1 // restore pr
779 #ifdef CONFIG_XEN
780 XEN_HYPER_RFI;
781 #else
782 rfi
783 #endif
784 END(dirty_bit)
786 .org ia64_ivt+0x2400
787 /////////////////////////////////////////////////////////////////////////////////////////
788 // 0x2400 Entry 9 (size 64 bundles) Instruction Access-bit (27)
789 ENTRY(iaccess_bit)
790 DBG_FAULT(9)
791 // Like Entry 8, except for instruction access
792 #ifdef CONFIG_XEN
793 movl r16=XSI_IFA
794 ;;
795 ld8 r16=[r16]
796 ;;
797 #else
798 mov r16=cr.ifa // get the address that caused the fault
799 #endif
800 movl r30=1f // load continuation point in case of nested fault
801 mov r31=pr // save predicates
802 #ifdef CONFIG_ITANIUM
803 /*
804 * Erratum 10 (IFA may contain incorrect address) has "NoFix" status.
805 */
806 mov r17=cr.ipsr
807 ;;
808 mov r18=cr.iip
809 tbit.z p6,p0=r17,IA64_PSR_IS_BIT // IA64 instruction set?
810 ;;
811 (p6) mov r16=r18 // if so, use cr.iip instead of cr.ifa
812 #endif /* CONFIG_ITANIUM */
813 ;;
814 #ifdef CONFIG_XEN
815 #if 1
816 mov r18=r8;
817 mov r8=r16;
818 XEN_HYPER_THASH;;
819 mov r17=r8;
820 mov r8=r18;;
821 #else
822 tak r17=r80 // "privified" thash
823 #endif
824 #else
825 thash r17=r16 // compute virtual address of L3 PTE
826 #endif
827 mov r29=b0 // save b0 in case of nested fault)
828 #ifdef CONFIG_SMP
829 mov r28=ar.ccv // save ar.ccv
830 ;;
831 1: ld8 r18=[r17]
832 ;;
833 mov ar.ccv=r18 // set compare value for cmpxchg
834 or r25=_PAGE_A,r18 // set the accessed bit
835 ;;
836 cmpxchg8.acq r26=[r17],r25,ar.ccv
837 mov r24=PAGE_SHIFT<<2
838 ;;
839 cmp.eq p6,p7=r26,r18
840 ;;
841 #ifdef CONFIG_XEN
842 mov r26=r8
843 mov r8=r25
844 ;;
845 (p6) XEN_HYPER_ITC_I
846 ;;
847 mov r8=r26
848 ;;
849 #else
850 (p6) itc.i r25 // install updated PTE
851 #endif
852 ;;
853 /*
854 * Tell the assemblers dependency-violation checker that the above "itc" instructions
855 * cannot possibly affect the following loads:
856 */
857 dv_serialize_data
859 ld8 r18=[r17] // read PTE again
860 ;;
861 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
862 ;;
863 (p7) ptc.l r16,r24
864 mov b0=r29 // restore b0
865 mov ar.ccv=r28
866 #else /* !CONFIG_SMP */
867 ;;
868 1: ld8 r18=[r17]
869 ;;
870 or r18=_PAGE_A,r18 // set the accessed bit
871 mov b0=r29 // restore b0
872 ;;
873 st8 [r17]=r18 // store back updated PTE
874 itc.i r18 // install updated PTE
875 #endif /* !CONFIG_SMP */
876 mov pr=r31,-1
877 #ifdef CONFIG_XEN
878 XEN_HYPER_RFI;
879 #else
880 rfi
881 #endif
882 END(iaccess_bit)
884 .org ia64_ivt+0x2800
885 /////////////////////////////////////////////////////////////////////////////////////////
886 // 0x2800 Entry 10 (size 64 bundles) Data Access-bit (15,55)
887 ENTRY(daccess_bit)
888 DBG_FAULT(10)
889 // Like Entry 8, except for data access
890 #ifdef CONFIG_XEN
891 movl r16=XSI_IFA
892 ;;
893 ld8 r16=[r16]
894 ;;
895 #else
896 mov r16=cr.ifa // get the address that caused the fault
897 #endif
898 movl r30=1f // load continuation point in case of nested fault
899 ;;
900 #ifdef CONFIG_XEN
901 #if 1
902 mov r18=r8;
903 mov r8=r16;
904 XEN_HYPER_THASH;;
905 mov r17=r8;
906 mov r8=r18;;
907 #else
908 tak r17=r80 // "privified" thash
909 #endif
910 #else
911 thash r17=r16 // compute virtual address of L3 PTE
912 #endif
913 mov r31=pr
914 mov r29=b0 // save b0 in case of nested fault)
915 #ifdef CONFIG_SMP
916 mov r28=ar.ccv // save ar.ccv
917 ;;
918 1: ld8 r18=[r17]
919 ;; // avoid RAW on r18
920 mov ar.ccv=r18 // set compare value for cmpxchg
921 or r25=_PAGE_A,r18 // set the dirty bit
922 ;;
923 cmpxchg8.acq r26=[r17],r25,ar.ccv
924 mov r24=PAGE_SHIFT<<2
925 ;;
926 cmp.eq p6,p7=r26,r18
927 ;;
928 #ifdef CONFIG_XEN
929 mov r26=r8
930 mov r8=r25
931 ;;
932 (p6) XEN_HYPER_ITC_D
933 ;;
934 mov r8=r26
935 ;;
936 #else
937 (p6) itc.d r25 // install updated PTE
938 #endif
939 /*
940 * Tell the assemblers dependency-violation checker that the above "itc" instructions
941 * cannot possibly affect the following loads:
942 */
943 dv_serialize_data
944 ;;
945 ld8 r18=[r17] // read PTE again
946 ;;
947 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
948 ;;
949 (p7) ptc.l r16,r24
950 mov ar.ccv=r28
951 #else
952 ;;
953 1: ld8 r18=[r17]
954 ;; // avoid RAW on r18
955 or r18=_PAGE_A,r18 // set the accessed bit
956 ;;
957 st8 [r17]=r18 // store back updated PTE
958 itc.d r18 // install updated PTE
959 #endif
960 mov b0=r29 // restore b0
961 mov pr=r31,-1
962 #ifdef CONFIG_XEN
963 XEN_HYPER_RFI;
964 #else
965 rfi
966 #endif
967 END(daccess_bit)
969 .org ia64_ivt+0x2c00
970 /////////////////////////////////////////////////////////////////////////////////////////
971 // 0x2c00 Entry 11 (size 64 bundles) Break instruction (33)
972 ENTRY(break_fault)
973 /*
974 * The streamlined system call entry/exit paths only save/restore the initial part
975 * of pt_regs. This implies that the callers of system-calls must adhere to the
976 * normal procedure calling conventions.
977 *
978 * Registers to be saved & restored:
979 * CR registers: cr.ipsr, cr.iip, cr.ifs
980 * AR registers: ar.unat, ar.pfs, ar.rsc, ar.rnat, ar.bspstore, ar.fpsr
981 * others: pr, b0, b6, loadrs, r1, r11, r12, r13, r15
982 * Registers to be restored only:
983 * r8-r11: output value from the system call.
984 *
985 * During system call exit, scratch registers (including r15) are modified/cleared
986 * to prevent leaking bits from kernel to user level.
987 */
988 DBG_FAULT(11)
989 mov r16=IA64_KR(CURRENT) // r16 = current task; 12 cycle read lat.
990 #ifdef CONFIG_XEN
991 movl r31=XSI_IPSR
992 ;;
993 ld8 r29=[r31],XSI_IIP-XSI_IPSR // get ipsr, point to iip
994 mov r18=__IA64_BREAK_SYSCALL
995 mov r21=ar.fpsr
996 ;;
997 ld8 r28=[r31],XSI_IIM-XSI_IIP // get iip, point to iim
998 mov r19=b6
999 mov r25=ar.unat
1000 ;;
1001 ld8 r17=[r31] // get iim
1002 mov r27=ar.rsc
1003 mov r26=ar.pfs
1004 ;;
1005 #else
1006 mov r17=cr.iim
1007 mov r18=__IA64_BREAK_SYSCALL
1008 mov r21=ar.fpsr
1009 mov r29=cr.ipsr
1010 mov r19=b6
1011 mov r25=ar.unat
1012 mov r27=ar.rsc
1013 mov r26=ar.pfs
1014 mov r28=cr.iip
1015 #endif
1016 mov r31=pr // prepare to save predicates
1017 mov r20=r1
1018 ;;
1019 adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16
1020 cmp.eq p0,p7=r18,r17 // is this a system call? (p7 <- false, if so)
1021 (p7) br.cond.spnt non_syscall
1022 ;;
1023 ld1 r17=[r16] // load current->thread.on_ustack flag
1024 st1 [r16]=r0 // clear current->thread.on_ustack flag
1025 add r1=-IA64_TASK_THREAD_ON_USTACK_OFFSET,r16 // set r1 for MINSTATE_START_SAVE_MIN_VIRT
1026 ;;
1027 invala
1029 /* adjust return address so we skip over the break instruction: */
1031 extr.u r8=r29,41,2 // extract ei field from cr.ipsr
1032 ;;
1033 cmp.eq p6,p7=2,r8 // isr.ei==2?
1034 mov r2=r1 // setup r2 for ia64_syscall_setup
1035 ;;
1036 (p6) mov r8=0 // clear ei to 0
1037 (p6) adds r28=16,r28 // switch cr.iip to next bundle cr.ipsr.ei wrapped
1038 (p7) adds r8=1,r8 // increment ei to next slot
1039 ;;
1040 cmp.eq pKStk,pUStk=r0,r17 // are we in kernel mode already?
1041 dep r29=r8,r29,41,2 // insert new ei into cr.ipsr
1042 ;;
1044 // switch from user to kernel RBS:
1045 MINSTATE_START_SAVE_MIN_VIRT
1046 br.call.sptk.many b7=ia64_syscall_setup
1047 ;;
1048 #ifdef CONFIG_XEN
1049 mov r2=b0; br.call.sptk b0=xen_bsw1;; mov b0=r2;;
1050 #else
1051 MINSTATE_END_SAVE_MIN_VIRT // switch to bank 1
1052 #endif
1053 #ifdef CONFIG_XEN
1054 movl r3=XSI_PSR_IC
1055 mov r16=1
1056 ;;
1057 #if 1
1058 st4 [r3]=r16,XSI_PSR_I-XSI_PSR_IC // vpsr.ic = 1
1059 ;;
1060 (p15) st4 [r3]=r16,XSI_PEND-XSI_PSR_I // if (p15) vpsr.i = 1
1061 mov r16=r0
1062 ;;
1063 (p15) ld4 r16=[r3] // if (pending_interrupts)
1064 ;;
1065 cmp.ne p6,p0=r16,r0
1066 ;;
1067 (p6) ssm psr.i // do a real ssm psr.i
1068 ;;
1069 #else
1070 // st4 [r3]=r16,XSI_PSR_I-XSI_PSR_IC // vpsr.ic = 1
1071 adds r3=XSI_PSR_I-XSI_PSR_IC,r3 // SKIP vpsr.ic = 1
1072 ;;
1073 (p15) st4 [r3]=r16,XSI_PEND-XSI_PSR_I // if (p15) vpsr.i = 1
1074 mov r16=r0
1075 ;;
1076 (p15) ld4 r16=[r3] // if (pending_interrupts)
1077 ;;
1078 cmp.ne p6,p0=r16,r0
1079 ;;
1080 //(p6) ssm psr.i // do a real ssm psr.i
1081 //(p6) XEN_HYPER_SSM_I;
1082 (p6) break 0x7;
1083 ;;
1084 #endif
1085 mov r3=NR_syscalls - 1
1086 ;;
1087 #else
1088 ssm psr.ic | PSR_DEFAULT_BITS
1089 ;;
1090 srlz.i // guarantee that interruption collection is on
1091 mov r3=NR_syscalls - 1
1092 ;;
1093 (p15) ssm psr.i // restore psr.i
1094 #endif
1095 // p10==true means out registers are more than 8 or r15's Nat is true
1096 (p10) br.cond.spnt.many ia64_ret_from_syscall
1097 ;;
1098 movl r16=sys_call_table
1100 adds r15=-1024,r15 // r15 contains the syscall number---subtract 1024
1101 movl r2=ia64_ret_from_syscall
1102 ;;
1103 shladd r20=r15,3,r16 // r20 = sys_call_table + 8*(syscall-1024)
1104 cmp.leu p6,p7=r15,r3 // (syscall > 0 && syscall < 1024 + NR_syscalls) ?
1105 mov rp=r2 // set the real return addr
1106 ;;
1107 (p6) ld8 r20=[r20] // load address of syscall entry point
1108 (p7) movl r20=sys_ni_syscall
1110 add r2=TI_FLAGS+IA64_TASK_SIZE,r13
1111 ;;
1112 ld4 r2=[r2] // r2 = current_thread_info()->flags
1113 ;;
1114 and r2=_TIF_SYSCALL_TRACEAUDIT,r2 // mask trace or audit
1115 ;;
1116 cmp.eq p8,p0=r2,r0
1117 mov b6=r20
1118 ;;
1119 (p8) br.call.sptk.many b6=b6 // ignore this return addr
1120 br.cond.sptk ia64_trace_syscall
1121 // NOT REACHED
1122 END(break_fault)
1124 .org ia64_ivt+0x3000
1125 /////////////////////////////////////////////////////////////////////////////////////////
1126 // 0x3000 Entry 12 (size 64 bundles) External Interrupt (4)
1127 ENTRY(interrupt)
1128 DBG_FAULT(12)
1129 mov r31=pr // prepare to save predicates
1130 ;;
1131 SAVE_MIN_WITH_COVER // uses r31; defines r2 and r3
1132 #ifdef CONFIG_XEN
1133 movl r3=XSI_PSR_IC
1134 mov r14=1
1135 ;;
1136 st4 [r3]=r14
1137 #else
1138 ssm psr.ic | PSR_DEFAULT_BITS
1139 #endif
1140 ;;
1141 adds r3=8,r2 // set up second base pointer for SAVE_REST
1142 srlz.i // ensure everybody knows psr.ic is back on
1143 ;;
1144 SAVE_REST
1145 ;;
1146 alloc r14=ar.pfs,0,0,2,0 // must be first in an insn group
1147 #ifdef CONFIG_XEN
1148 ;;
1149 br.call.sptk.many rp=xen_get_ivr
1150 ;;
1151 mov out0=r8 // pass cr.ivr as first arg
1152 #else
1153 mov out0=cr.ivr // pass cr.ivr as first arg
1154 #endif
1155 add out1=16,sp // pass pointer to pt_regs as second arg
1156 ;;
1157 srlz.d // make sure we see the effect of cr.ivr
1158 movl r14=ia64_leave_kernel
1159 ;;
1160 mov rp=r14
1161 br.call.sptk.many b6=ia64_handle_irq
1162 END(interrupt)
1164 .org ia64_ivt+0x3400
1165 /////////////////////////////////////////////////////////////////////////////////////////
1166 // 0x3400 Entry 13 (size 64 bundles) Reserved
1167 DBG_FAULT(13)
1168 FAULT(13)
1170 .org ia64_ivt+0x3800
1171 /////////////////////////////////////////////////////////////////////////////////////////
1172 // 0x3800 Entry 14 (size 64 bundles) Reserved
1173 DBG_FAULT(14)
1174 FAULT(14)
1176 /*
1177 * There is no particular reason for this code to be here, other than that
1178 * there happens to be space here that would go unused otherwise. If this
1179 * fault ever gets "unreserved", simply moved the following code to a more
1180 * suitable spot...
1182 * ia64_syscall_setup() is a separate subroutine so that it can
1183 * allocate stacked registers so it can safely demine any
1184 * potential NaT values from the input registers.
1186 * On entry:
1187 * - executing on bank 0 or bank 1 register set (doesn't matter)
1188 * - r1: stack pointer
1189 * - r2: current task pointer
1190 * - r3: preserved
1191 * - r11: original contents (saved ar.pfs to be saved)
1192 * - r12: original contents (sp to be saved)
1193 * - r13: original contents (tp to be saved)
1194 * - r15: original contents (syscall # to be saved)
1195 * - r18: saved bsp (after switching to kernel stack)
1196 * - r19: saved b6
1197 * - r20: saved r1 (gp)
1198 * - r21: saved ar.fpsr
1199 * - r22: kernel's register backing store base (krbs_base)
1200 * - r23: saved ar.bspstore
1201 * - r24: saved ar.rnat
1202 * - r25: saved ar.unat
1203 * - r26: saved ar.pfs
1204 * - r27: saved ar.rsc
1205 * - r28: saved cr.iip
1206 * - r29: saved cr.ipsr
1207 * - r31: saved pr
1208 * - b0: original contents (to be saved)
1209 * On exit:
1210 * - executing on bank 1 registers
1211 * - psr.ic enabled, interrupts restored
1212 * - p10: TRUE if syscall is invoked with more than 8 out
1213 * registers or r15's Nat is true
1214 * - r1: kernel's gp
1215 * - r3: preserved (same as on entry)
1216 * - r8: -EINVAL if p10 is true
1217 * - r12: points to kernel stack
1218 * - r13: points to current task
1219 * - p15: TRUE if interrupts need to be re-enabled
1220 * - ar.fpsr: set to kernel settings
1221 */
1222 #ifndef CONFIG_XEN
1223 GLOBAL_ENTRY(ia64_syscall_setup)
1224 #if PT(B6) != 0
1225 # error This code assumes that b6 is the first field in pt_regs.
1226 #endif
1227 st8 [r1]=r19 // save b6
1228 add r16=PT(CR_IPSR),r1 // initialize first base pointer
1229 add r17=PT(R11),r1 // initialize second base pointer
1230 ;;
1231 alloc r19=ar.pfs,8,0,0,0 // ensure in0-in7 are writable
1232 st8 [r16]=r29,PT(AR_PFS)-PT(CR_IPSR) // save cr.ipsr
1233 tnat.nz p8,p0=in0
1235 st8.spill [r17]=r11,PT(CR_IIP)-PT(R11) // save r11
1236 tnat.nz p9,p0=in1
1237 (pKStk) mov r18=r0 // make sure r18 isn't NaT
1238 ;;
1240 st8 [r16]=r26,PT(CR_IFS)-PT(AR_PFS) // save ar.pfs
1241 st8 [r17]=r28,PT(AR_UNAT)-PT(CR_IIP) // save cr.iip
1242 mov r28=b0 // save b0 (2 cyc)
1243 ;;
1245 st8 [r17]=r25,PT(AR_RSC)-PT(AR_UNAT) // save ar.unat
1246 dep r19=0,r19,38,26 // clear all bits but 0..37 [I0]
1247 (p8) mov in0=-1
1248 ;;
1250 st8 [r16]=r19,PT(AR_RNAT)-PT(CR_IFS) // store ar.pfs.pfm in cr.ifs
1251 extr.u r11=r19,7,7 // I0 // get sol of ar.pfs
1252 and r8=0x7f,r19 // A // get sof of ar.pfs
1254 st8 [r17]=r27,PT(AR_BSPSTORE)-PT(AR_RSC)// save ar.rsc
1255 tbit.nz p15,p0=r29,IA64_PSR_I_BIT // I0
1256 (p9) mov in1=-1
1257 ;;
1259 (pUStk) sub r18=r18,r22 // r18=RSE.ndirty*8
1260 tnat.nz p10,p0=in2
1261 add r11=8,r11
1262 ;;
1263 (pKStk) adds r16=PT(PR)-PT(AR_RNAT),r16 // skip over ar_rnat field
1264 (pKStk) adds r17=PT(B0)-PT(AR_BSPSTORE),r17 // skip over ar_bspstore field
1265 tnat.nz p11,p0=in3
1266 ;;
1267 (p10) mov in2=-1
1268 tnat.nz p12,p0=in4 // [I0]
1269 (p11) mov in3=-1
1270 ;;
1271 (pUStk) st8 [r16]=r24,PT(PR)-PT(AR_RNAT) // save ar.rnat
1272 (pUStk) st8 [r17]=r23,PT(B0)-PT(AR_BSPSTORE) // save ar.bspstore
1273 shl r18=r18,16 // compute ar.rsc to be used for "loadrs"
1274 ;;
1275 st8 [r16]=r31,PT(LOADRS)-PT(PR) // save predicates
1276 st8 [r17]=r28,PT(R1)-PT(B0) // save b0
1277 tnat.nz p13,p0=in5 // [I0]
1278 ;;
1279 st8 [r16]=r18,PT(R12)-PT(LOADRS) // save ar.rsc value for "loadrs"
1280 st8.spill [r17]=r20,PT(R13)-PT(R1) // save original r1
1281 (p12) mov in4=-1
1282 ;;
1284 .mem.offset 0,0; st8.spill [r16]=r12,PT(AR_FPSR)-PT(R12) // save r12
1285 .mem.offset 8,0; st8.spill [r17]=r13,PT(R15)-PT(R13) // save r13
1286 (p13) mov in5=-1
1287 ;;
1288 st8 [r16]=r21,PT(R8)-PT(AR_FPSR) // save ar.fpsr
1289 tnat.nz p14,p0=in6
1290 cmp.lt p10,p9=r11,r8 // frame size can't be more than local+8
1291 ;;
1292 stf8 [r16]=f1 // ensure pt_regs.r8 != 0 (see handle_syscall_error)
1293 (p9) tnat.nz p10,p0=r15
1294 adds r12=-16,r1 // switch to kernel memory stack (with 16 bytes of scratch)
1296 st8.spill [r17]=r15 // save r15
1297 tnat.nz p8,p0=in7
1298 nop.i 0
1300 mov r13=r2 // establish `current'
1301 movl r1=__gp // establish kernel global pointer
1302 ;;
1303 (p14) mov in6=-1
1304 (p8) mov in7=-1
1305 nop.i 0
1307 cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0
1308 movl r17=FPSR_DEFAULT
1309 ;;
1310 mov.m ar.fpsr=r17 // set ar.fpsr to kernel default value
1311 (p10) mov r8=-EINVAL
1312 br.ret.sptk.many b7
1313 END(ia64_syscall_setup)
1314 #endif
1316 .org ia64_ivt+0x3c00
1317 /////////////////////////////////////////////////////////////////////////////////////////
1318 // 0x3c00 Entry 15 (size 64 bundles) Reserved
1319 DBG_FAULT(15)
1320 FAULT(15)
1322 /*
1323 * Squatting in this space ...
1325 * This special case dispatcher for illegal operation faults allows preserved
1326 * registers to be modified through a callback function (asm only) that is handed
1327 * back from the fault handler in r8. Up to three arguments can be passed to the
1328 * callback function by returning an aggregate with the callback as its first
1329 * element, followed by the arguments.
1330 */
1331 ENTRY(dispatch_illegal_op_fault)
1332 SAVE_MIN_WITH_COVER
1333 ssm psr.ic | PSR_DEFAULT_BITS
1334 ;;
1335 srlz.i // guarantee that interruption collection is on
1336 ;;
1337 (p15) ssm psr.i // restore psr.i
1338 adds r3=8,r2 // set up second base pointer for SAVE_REST
1339 ;;
1340 alloc r14=ar.pfs,0,0,1,0 // must be first in insn group
1341 mov out0=ar.ec
1342 ;;
1343 SAVE_REST
1344 ;;
1345 br.call.sptk.many rp=ia64_illegal_op_fault
1346 .ret0: ;;
1347 alloc r14=ar.pfs,0,0,3,0 // must be first in insn group
1348 mov out0=r9
1349 mov out1=r10
1350 mov out2=r11
1351 movl r15=ia64_leave_kernel
1352 ;;
1353 mov rp=r15
1354 mov b6=r8
1355 ;;
1356 cmp.ne p6,p0=0,r8
1357 (p6) br.call.dpnt.many b6=b6 // call returns to ia64_leave_kernel
1358 br.sptk.many ia64_leave_kernel
1359 END(dispatch_illegal_op_fault)
1361 .org ia64_ivt+0x4000
1362 /////////////////////////////////////////////////////////////////////////////////////////
1363 // 0x4000 Entry 16 (size 64 bundles) Reserved
1364 DBG_FAULT(16)
1365 FAULT(16)
1367 .org ia64_ivt+0x4400
1368 /////////////////////////////////////////////////////////////////////////////////////////
1369 // 0x4400 Entry 17 (size 64 bundles) Reserved
1370 DBG_FAULT(17)
1371 FAULT(17)
1373 ENTRY(non_syscall)
1374 SAVE_MIN_WITH_COVER
1376 // There is no particular reason for this code to be here, other than that
1377 // there happens to be space here that would go unused otherwise. If this
1378 // fault ever gets "unreserved", simply moved the following code to a more
1379 // suitable spot...
1381 alloc r14=ar.pfs,0,0,2,0
1382 mov out0=cr.iim
1383 add out1=16,sp
1384 adds r3=8,r2 // set up second base pointer for SAVE_REST
1386 ssm psr.ic | PSR_DEFAULT_BITS
1387 ;;
1388 srlz.i // guarantee that interruption collection is on
1389 ;;
1390 (p15) ssm psr.i // restore psr.i
1391 movl r15=ia64_leave_kernel
1392 ;;
1393 SAVE_REST
1394 mov rp=r15
1395 ;;
1396 br.call.sptk.many b6=ia64_bad_break // avoid WAW on CFM and ignore return addr
1397 END(non_syscall)
1399 .org ia64_ivt+0x4800
1400 /////////////////////////////////////////////////////////////////////////////////////////
1401 // 0x4800 Entry 18 (size 64 bundles) Reserved
1402 DBG_FAULT(18)
1403 FAULT(18)
1405 /*
1406 * There is no particular reason for this code to be here, other than that
1407 * there happens to be space here that would go unused otherwise. If this
1408 * fault ever gets "unreserved", simply moved the following code to a more
1409 * suitable spot...
1410 */
1412 ENTRY(dispatch_unaligned_handler)
1413 SAVE_MIN_WITH_COVER
1414 ;;
1415 alloc r14=ar.pfs,0,0,2,0 // now it's safe (must be first in insn group!)
1416 mov out0=cr.ifa
1417 adds out1=16,sp
1419 ssm psr.ic | PSR_DEFAULT_BITS
1420 ;;
1421 srlz.i // guarantee that interruption collection is on
1422 ;;
1423 (p15) ssm psr.i // restore psr.i
1424 adds r3=8,r2 // set up second base pointer
1425 ;;
1426 SAVE_REST
1427 movl r14=ia64_leave_kernel
1428 ;;
1429 mov rp=r14
1430 br.sptk.many ia64_prepare_handle_unaligned
1431 END(dispatch_unaligned_handler)
1433 .org ia64_ivt+0x4c00
1434 /////////////////////////////////////////////////////////////////////////////////////////
1435 // 0x4c00 Entry 19 (size 64 bundles) Reserved
1436 DBG_FAULT(19)
1437 FAULT(19)
1439 /*
1440 * There is no particular reason for this code to be here, other than that
1441 * there happens to be space here that would go unused otherwise. If this
1442 * fault ever gets "unreserved", simply moved the following code to a more
1443 * suitable spot...
1444 */
1446 ENTRY(dispatch_to_fault_handler)
1447 /*
1448 * Input:
1449 * psr.ic: off
1450 * r19: fault vector number (e.g., 24 for General Exception)
1451 * r31: contains saved predicates (pr)
1452 */
1453 SAVE_MIN_WITH_COVER_R19
1454 alloc r14=ar.pfs,0,0,5,0
1455 mov out0=r15
1456 #ifdef CONFIG_XEN
1457 movl out1=XSI_ISR
1458 ;;
1459 adds out2=XSI_IFA-XSI_ISR,out1
1460 adds out3=XSI_IIM-XSI_ISR,out1
1461 adds out4=XSI_ITIR-XSI_ISR,out1
1462 ;;
1463 ld8 out1=[out1]
1464 ld8 out2=[out2]
1465 ld8 out3=[out4]
1466 ld8 out4=[out4]
1467 ;;
1468 #else
1469 mov out1=cr.isr
1470 mov out2=cr.ifa
1471 mov out3=cr.iim
1472 mov out4=cr.itir
1473 ;;
1474 #endif
1475 ssm psr.ic | PSR_DEFAULT_BITS
1476 ;;
1477 srlz.i // guarantee that interruption collection is on
1478 ;;
1479 (p15) ssm psr.i // restore psr.i
1480 adds r3=8,r2 // set up second base pointer for SAVE_REST
1481 ;;
1482 SAVE_REST
1483 movl r14=ia64_leave_kernel
1484 ;;
1485 mov rp=r14
1486 br.call.sptk.many b6=ia64_fault
1487 END(dispatch_to_fault_handler)
1489 //
1490 // --- End of long entries, Beginning of short entries
1491 //
1493 .org ia64_ivt+0x5000
1494 /////////////////////////////////////////////////////////////////////////////////////////
1495 // 0x5000 Entry 20 (size 16 bundles) Page Not Present (10,22,49)
1496 ENTRY(page_not_present)
1497 DBG_FAULT(20)
1498 mov r16=cr.ifa
1499 rsm psr.dt
1500 /*
1501 * The Linux page fault handler doesn't expect non-present pages to be in
1502 * the TLB. Flush the existing entry now, so we meet that expectation.
1503 */
1504 mov r17=PAGE_SHIFT<<2
1505 ;;
1506 ptc.l r16,r17
1507 ;;
1508 mov r31=pr
1509 srlz.d
1510 br.sptk.many page_fault
1511 END(page_not_present)
1513 .org ia64_ivt+0x5100
1514 /////////////////////////////////////////////////////////////////////////////////////////
1515 // 0x5100 Entry 21 (size 16 bundles) Key Permission (13,25,52)
1516 ENTRY(key_permission)
1517 DBG_FAULT(21)
1518 mov r16=cr.ifa
1519 rsm psr.dt
1520 mov r31=pr
1521 ;;
1522 srlz.d
1523 br.sptk.many page_fault
1524 END(key_permission)
1526 .org ia64_ivt+0x5200
1527 /////////////////////////////////////////////////////////////////////////////////////////
1528 // 0x5200 Entry 22 (size 16 bundles) Instruction Access Rights (26)
1529 ENTRY(iaccess_rights)
1530 DBG_FAULT(22)
1531 mov r16=cr.ifa
1532 rsm psr.dt
1533 mov r31=pr
1534 ;;
1535 srlz.d
1536 br.sptk.many page_fault
1537 END(iaccess_rights)
1539 .org ia64_ivt+0x5300
1540 /////////////////////////////////////////////////////////////////////////////////////////
1541 // 0x5300 Entry 23 (size 16 bundles) Data Access Rights (14,53)
1542 ENTRY(daccess_rights)
1543 DBG_FAULT(23)
1544 #ifdef CONFIG_XEN
1545 movl r16=XSI_IFA
1546 ;;
1547 ld8 r16=[r16]
1548 ;;
1549 XEN_HYPER_RSM_PSR_DT;
1550 #else
1551 mov r16=cr.ifa
1552 rsm psr.dt
1553 #endif
1554 mov r31=pr
1555 ;;
1556 srlz.d
1557 br.sptk.many page_fault
1558 END(daccess_rights)
1560 .org ia64_ivt+0x5400
1561 /////////////////////////////////////////////////////////////////////////////////////////
1562 // 0x5400 Entry 24 (size 16 bundles) General Exception (5,32,34,36,38,39)
1563 ENTRY(general_exception)
1564 DBG_FAULT(24)
1565 mov r16=cr.isr
1566 mov r31=pr
1567 ;;
1568 cmp4.eq p6,p0=0,r16
1569 (p6) br.sptk.many dispatch_illegal_op_fault
1570 ;;
1571 mov r19=24 // fault number
1572 br.sptk.many dispatch_to_fault_handler
1573 END(general_exception)
1575 .org ia64_ivt+0x5500
1576 /////////////////////////////////////////////////////////////////////////////////////////
1577 // 0x5500 Entry 25 (size 16 bundles) Disabled FP-Register (35)
1578 ENTRY(disabled_fp_reg)
1579 DBG_FAULT(25)
1580 rsm psr.dfh // ensure we can access fph
1581 ;;
1582 srlz.d
1583 mov r31=pr
1584 mov r19=25
1585 br.sptk.many dispatch_to_fault_handler
1586 END(disabled_fp_reg)
1588 .org ia64_ivt+0x5600
1589 /////////////////////////////////////////////////////////////////////////////////////////
1590 // 0x5600 Entry 26 (size 16 bundles) Nat Consumption (11,23,37,50)
1591 ENTRY(nat_consumption)
1592 DBG_FAULT(26)
1593 FAULT(26)
1594 END(nat_consumption)
1596 .org ia64_ivt+0x5700
1597 /////////////////////////////////////////////////////////////////////////////////////////
1598 // 0x5700 Entry 27 (size 16 bundles) Speculation (40)
1599 ENTRY(speculation_vector)
1600 DBG_FAULT(27)
1601 /*
1602 * A [f]chk.[as] instruction needs to take the branch to the recovery code but
1603 * this part of the architecture is not implemented in hardware on some CPUs, such
1604 * as Itanium. Thus, in general we need to emulate the behavior. IIM contains
1605 * the relative target (not yet sign extended). So after sign extending it we
1606 * simply add it to IIP. We also need to reset the EI field of the IPSR to zero,
1607 * i.e., the slot to restart into.
1609 * cr.imm contains zero_ext(imm21)
1610 */
1611 mov r18=cr.iim
1612 ;;
1613 mov r17=cr.iip
1614 shl r18=r18,43 // put sign bit in position (43=64-21)
1615 ;;
1617 mov r16=cr.ipsr
1618 shr r18=r18,39 // sign extend (39=43-4)
1619 ;;
1621 add r17=r17,r18 // now add the offset
1622 ;;
1623 mov cr.iip=r17
1624 dep r16=0,r16,41,2 // clear EI
1625 ;;
1627 mov cr.ipsr=r16
1628 ;;
1630 #ifdef CONFIG_XEN
1631 XEN_HYPER_RFI;
1632 #else
1633 rfi
1634 #endif
1635 END(speculation_vector)
1637 .org ia64_ivt+0x5800
1638 /////////////////////////////////////////////////////////////////////////////////////////
1639 // 0x5800 Entry 28 (size 16 bundles) Reserved
1640 DBG_FAULT(28)
1641 FAULT(28)
1643 .org ia64_ivt+0x5900
1644 /////////////////////////////////////////////////////////////////////////////////////////
1645 // 0x5900 Entry 29 (size 16 bundles) Debug (16,28,56)
1646 ENTRY(debug_vector)
1647 DBG_FAULT(29)
1648 FAULT(29)
1649 END(debug_vector)
1651 .org ia64_ivt+0x5a00
1652 /////////////////////////////////////////////////////////////////////////////////////////
1653 // 0x5a00 Entry 30 (size 16 bundles) Unaligned Reference (57)
1654 ENTRY(unaligned_access)
1655 DBG_FAULT(30)
1656 mov r16=cr.ipsr
1657 mov r31=pr // prepare to save predicates
1658 ;;
1659 br.sptk.many dispatch_unaligned_handler
1660 END(unaligned_access)
1662 .org ia64_ivt+0x5b00
1663 /////////////////////////////////////////////////////////////////////////////////////////
1664 // 0x5b00 Entry 31 (size 16 bundles) Unsupported Data Reference (57)
1665 ENTRY(unsupported_data_reference)
1666 DBG_FAULT(31)
1667 FAULT(31)
1668 END(unsupported_data_reference)
1670 .org ia64_ivt+0x5c00
1671 /////////////////////////////////////////////////////////////////////////////////////////
1672 // 0x5c00 Entry 32 (size 16 bundles) Floating-Point Fault (64)
1673 ENTRY(floating_point_fault)
1674 DBG_FAULT(32)
1675 FAULT(32)
1676 END(floating_point_fault)
1678 .org ia64_ivt+0x5d00
1679 /////////////////////////////////////////////////////////////////////////////////////////
1680 // 0x5d00 Entry 33 (size 16 bundles) Floating Point Trap (66)
1681 ENTRY(floating_point_trap)
1682 DBG_FAULT(33)
1683 FAULT(33)
1684 END(floating_point_trap)
1686 .org ia64_ivt+0x5e00
1687 /////////////////////////////////////////////////////////////////////////////////////////
1688 // 0x5e00 Entry 34 (size 16 bundles) Lower Privilege Transfer Trap (66)
1689 ENTRY(lower_privilege_trap)
1690 DBG_FAULT(34)
1691 FAULT(34)
1692 END(lower_privilege_trap)
1694 .org ia64_ivt+0x5f00
1695 /////////////////////////////////////////////////////////////////////////////////////////
1696 // 0x5f00 Entry 35 (size 16 bundles) Taken Branch Trap (68)
1697 ENTRY(taken_branch_trap)
1698 DBG_FAULT(35)
1699 FAULT(35)
1700 END(taken_branch_trap)
1702 .org ia64_ivt+0x6000
1703 /////////////////////////////////////////////////////////////////////////////////////////
1704 // 0x6000 Entry 36 (size 16 bundles) Single Step Trap (69)
1705 ENTRY(single_step_trap)
1706 DBG_FAULT(36)
1707 FAULT(36)
1708 END(single_step_trap)
1710 .org ia64_ivt+0x6100
1711 /////////////////////////////////////////////////////////////////////////////////////////
1712 // 0x6100 Entry 37 (size 16 bundles) Reserved
1713 DBG_FAULT(37)
1714 FAULT(37)
1716 .org ia64_ivt+0x6200
1717 /////////////////////////////////////////////////////////////////////////////////////////
1718 // 0x6200 Entry 38 (size 16 bundles) Reserved
1719 DBG_FAULT(38)
1720 FAULT(38)
1722 .org ia64_ivt+0x6300
1723 /////////////////////////////////////////////////////////////////////////////////////////
1724 // 0x6300 Entry 39 (size 16 bundles) Reserved
1725 DBG_FAULT(39)
1726 FAULT(39)
1728 .org ia64_ivt+0x6400
1729 /////////////////////////////////////////////////////////////////////////////////////////
1730 // 0x6400 Entry 40 (size 16 bundles) Reserved
1731 DBG_FAULT(40)
1732 FAULT(40)
1734 .org ia64_ivt+0x6500
1735 /////////////////////////////////////////////////////////////////////////////////////////
1736 // 0x6500 Entry 41 (size 16 bundles) Reserved
1737 DBG_FAULT(41)
1738 FAULT(41)
1740 .org ia64_ivt+0x6600
1741 /////////////////////////////////////////////////////////////////////////////////////////
1742 // 0x6600 Entry 42 (size 16 bundles) Reserved
1743 DBG_FAULT(42)
1744 FAULT(42)
1746 .org ia64_ivt+0x6700
1747 /////////////////////////////////////////////////////////////////////////////////////////
1748 // 0x6700 Entry 43 (size 16 bundles) Reserved
1749 DBG_FAULT(43)
1750 FAULT(43)
1752 .org ia64_ivt+0x6800
1753 /////////////////////////////////////////////////////////////////////////////////////////
1754 // 0x6800 Entry 44 (size 16 bundles) Reserved
1755 DBG_FAULT(44)
1756 FAULT(44)
1758 .org ia64_ivt+0x6900
1759 /////////////////////////////////////////////////////////////////////////////////////////
1760 // 0x6900 Entry 45 (size 16 bundles) IA-32 Exeception (17,18,29,41,42,43,44,58,60,61,62,72,73,75,76,77)
1761 ENTRY(ia32_exception)
1762 DBG_FAULT(45)
1763 FAULT(45)
1764 END(ia32_exception)
1766 .org ia64_ivt+0x6a00
1767 /////////////////////////////////////////////////////////////////////////////////////////
1768 // 0x6a00 Entry 46 (size 16 bundles) IA-32 Intercept (30,31,59,70,71)
1769 ENTRY(ia32_intercept)
1770 DBG_FAULT(46)
1771 #ifdef CONFIG_IA32_SUPPORT
1772 mov r31=pr
1773 mov r16=cr.isr
1774 ;;
1775 extr.u r17=r16,16,8 // get ISR.code
1776 mov r18=ar.eflag
1777 mov r19=cr.iim // old eflag value
1778 ;;
1779 cmp.ne p6,p0=2,r17
1780 (p6) br.cond.spnt 1f // not a system flag fault
1781 xor r16=r18,r19
1782 ;;
1783 extr.u r17=r16,18,1 // get the eflags.ac bit
1784 ;;
1785 cmp.eq p6,p0=0,r17
1786 (p6) br.cond.spnt 1f // eflags.ac bit didn't change
1787 ;;
1788 mov pr=r31,-1 // restore predicate registers
1789 #ifdef CONFIG_XEN
1790 XEN_HYPER_RFI;
1791 #else
1792 rfi
1793 #endif
1795 1:
1796 #endif // CONFIG_IA32_SUPPORT
1797 FAULT(46)
1798 END(ia32_intercept)
1800 .org ia64_ivt+0x6b00
1801 /////////////////////////////////////////////////////////////////////////////////////////
1802 // 0x6b00 Entry 47 (size 16 bundles) IA-32 Interrupt (74)
1803 ENTRY(ia32_interrupt)
1804 DBG_FAULT(47)
1805 #ifdef CONFIG_IA32_SUPPORT
1806 mov r31=pr
1807 br.sptk.many dispatch_to_ia32_handler
1808 #else
1809 FAULT(47)
1810 #endif
1811 END(ia32_interrupt)
1813 .org ia64_ivt+0x6c00
1814 /////////////////////////////////////////////////////////////////////////////////////////
1815 // 0x6c00 Entry 48 (size 16 bundles) Reserved
1816 DBG_FAULT(48)
1817 FAULT(48)
1819 .org ia64_ivt+0x6d00
1820 /////////////////////////////////////////////////////////////////////////////////////////
1821 // 0x6d00 Entry 49 (size 16 bundles) Reserved
1822 DBG_FAULT(49)
1823 FAULT(49)
1825 .org ia64_ivt+0x6e00
1826 /////////////////////////////////////////////////////////////////////////////////////////
1827 // 0x6e00 Entry 50 (size 16 bundles) Reserved
1828 DBG_FAULT(50)
1829 FAULT(50)
1831 .org ia64_ivt+0x6f00
1832 /////////////////////////////////////////////////////////////////////////////////////////
1833 // 0x6f00 Entry 51 (size 16 bundles) Reserved
1834 DBG_FAULT(51)
1835 FAULT(51)
1837 .org ia64_ivt+0x7000
1838 /////////////////////////////////////////////////////////////////////////////////////////
1839 // 0x7000 Entry 52 (size 16 bundles) Reserved
1840 DBG_FAULT(52)
1841 FAULT(52)
1843 .org ia64_ivt+0x7100
1844 /////////////////////////////////////////////////////////////////////////////////////////
1845 // 0x7100 Entry 53 (size 16 bundles) Reserved
1846 DBG_FAULT(53)
1847 FAULT(53)
1849 .org ia64_ivt+0x7200
1850 /////////////////////////////////////////////////////////////////////////////////////////
1851 // 0x7200 Entry 54 (size 16 bundles) Reserved
1852 DBG_FAULT(54)
1853 FAULT(54)
1855 .org ia64_ivt+0x7300
1856 /////////////////////////////////////////////////////////////////////////////////////////
1857 // 0x7300 Entry 55 (size 16 bundles) Reserved
1858 DBG_FAULT(55)
1859 FAULT(55)
1861 .org ia64_ivt+0x7400
1862 /////////////////////////////////////////////////////////////////////////////////////////
1863 // 0x7400 Entry 56 (size 16 bundles) Reserved
1864 DBG_FAULT(56)
1865 FAULT(56)
1867 .org ia64_ivt+0x7500
1868 /////////////////////////////////////////////////////////////////////////////////////////
1869 // 0x7500 Entry 57 (size 16 bundles) Reserved
1870 DBG_FAULT(57)
1871 FAULT(57)
1873 .org ia64_ivt+0x7600
1874 /////////////////////////////////////////////////////////////////////////////////////////
1875 // 0x7600 Entry 58 (size 16 bundles) Reserved
1876 DBG_FAULT(58)
1877 FAULT(58)
1879 .org ia64_ivt+0x7700
1880 /////////////////////////////////////////////////////////////////////////////////////////
1881 // 0x7700 Entry 59 (size 16 bundles) Reserved
1882 DBG_FAULT(59)
1883 FAULT(59)
1885 .org ia64_ivt+0x7800
1886 /////////////////////////////////////////////////////////////////////////////////////////
1887 // 0x7800 Entry 60 (size 16 bundles) Reserved
1888 DBG_FAULT(60)
1889 FAULT(60)
1891 .org ia64_ivt+0x7900
1892 /////////////////////////////////////////////////////////////////////////////////////////
1893 // 0x7900 Entry 61 (size 16 bundles) Reserved
1894 DBG_FAULT(61)
1895 FAULT(61)
1897 .org ia64_ivt+0x7a00
1898 /////////////////////////////////////////////////////////////////////////////////////////
1899 // 0x7a00 Entry 62 (size 16 bundles) Reserved
1900 DBG_FAULT(62)
1901 FAULT(62)
1903 .org ia64_ivt+0x7b00
1904 /////////////////////////////////////////////////////////////////////////////////////////
1905 // 0x7b00 Entry 63 (size 16 bundles) Reserved
1906 DBG_FAULT(63)
1907 FAULT(63)
1909 .org ia64_ivt+0x7c00
1910 /////////////////////////////////////////////////////////////////////////////////////////
1911 // 0x7c00 Entry 64 (size 16 bundles) Reserved
1912 DBG_FAULT(64)
1913 FAULT(64)
1915 .org ia64_ivt+0x7d00
1916 /////////////////////////////////////////////////////////////////////////////////////////
1917 // 0x7d00 Entry 65 (size 16 bundles) Reserved
1918 DBG_FAULT(65)
1919 FAULT(65)
1921 .org ia64_ivt+0x7e00
1922 /////////////////////////////////////////////////////////////////////////////////////////
1923 // 0x7e00 Entry 66 (size 16 bundles) Reserved
1924 DBG_FAULT(66)
1925 FAULT(66)
1927 #ifdef CONFIG_XEN
1928 /*
1929 * There is no particular reason for this code to be here, other than that
1930 * there happens to be space here that would go unused otherwise. If this
1931 * fault ever gets "unreserved", simply moved the following code to a more
1932 * suitable spot...
1933 */
1935 GLOBAL_ENTRY(xen_bsw1)
1936 /* FIXME: THIS CODE IS NOT NaT SAFE! */
1937 movl r30=XSI_BANKNUM;
1938 mov r31=1;;
1939 st4 [r30]=r31;
1940 movl r30=XSI_BANK1_R16;
1941 movl r31=XSI_BANK1_R16+8;;
1942 ld8 r16=[r30],16; ld8 r17=[r31],16;;
1943 ld8 r18=[r30],16; ld8 r19=[r31],16;;
1944 ld8 r20=[r30],16; ld8 r21=[r31],16;;
1945 ld8 r22=[r30],16; ld8 r23=[r31],16;;
1946 ld8 r24=[r30],16; ld8 r25=[r31],16;;
1947 ld8 r26=[r30],16; ld8 r27=[r31],16;;
1948 ld8 r28=[r30],16; ld8 r29=[r31],16;;
1949 ld8 r30=[r30]; ld8 r31=[r31];;
1950 br.ret.sptk.many b0
1951 #endif
1953 .org ia64_ivt+0x7f00
1954 /////////////////////////////////////////////////////////////////////////////////////////
1955 // 0x7f00 Entry 67 (size 16 bundles) Reserved
1956 DBG_FAULT(67)
1957 FAULT(67)
1959 #ifdef CONFIG_IA32_SUPPORT
1961 /*
1962 * There is no particular reason for this code to be here, other than that
1963 * there happens to be space here that would go unused otherwise. If this
1964 * fault ever gets "unreserved", simply moved the following code to a more
1965 * suitable spot...
1966 */
1968 // IA32 interrupt entry point
1970 ENTRY(dispatch_to_ia32_handler)
1971 SAVE_MIN
1972 ;;
1973 mov r14=cr.isr
1974 ssm psr.ic | PSR_DEFAULT_BITS
1975 ;;
1976 srlz.i // guarantee that interruption collection is on
1977 ;;
1978 (p15) ssm psr.i
1979 adds r3=8,r2 // Base pointer for SAVE_REST
1980 ;;
1981 SAVE_REST
1982 ;;
1983 mov r15=0x80
1984 shr r14=r14,16 // Get interrupt number
1985 ;;
1986 cmp.ne p6,p0=r14,r15
1987 (p6) br.call.dpnt.many b6=non_ia32_syscall
1989 adds r14=IA64_PT_REGS_R8_OFFSET + 16,sp // 16 byte hole per SW conventions
1990 adds r15=IA64_PT_REGS_R1_OFFSET + 16,sp
1991 ;;
1992 cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0
1993 ld8 r8=[r14] // get r8
1994 ;;
1995 st8 [r15]=r8 // save original EAX in r1 (IA32 procs don't use the GP)
1996 ;;
1997 alloc r15=ar.pfs,0,0,6,0 // must first in an insn group
1998 ;;
1999 ld4 r8=[r14],8 // r8 == eax (syscall number)
2000 mov r15=IA32_NR_syscalls
2001 ;;
2002 cmp.ltu.unc p6,p7=r8,r15
2003 ld4 out1=[r14],8 // r9 == ecx
2004 ;;
2005 ld4 out2=[r14],8 // r10 == edx
2006 ;;
2007 ld4 out0=[r14] // r11 == ebx
2008 adds r14=(IA64_PT_REGS_R13_OFFSET) + 16,sp
2009 ;;
2010 ld4 out5=[r14],PT(R14)-PT(R13) // r13 == ebp
2011 ;;
2012 ld4 out3=[r14],PT(R15)-PT(R14) // r14 == esi
2013 adds r2=TI_FLAGS+IA64_TASK_SIZE,r13
2014 ;;
2015 ld4 out4=[r14] // r15 == edi
2016 movl r16=ia32_syscall_table
2017 ;;
2018 (p6) shladd r16=r8,3,r16 // force ni_syscall if not valid syscall number
2019 ld4 r2=[r2] // r2 = current_thread_info()->flags
2020 ;;
2021 ld8 r16=[r16]
2022 and r2=_TIF_SYSCALL_TRACEAUDIT,r2 // mask trace or audit
2023 ;;
2024 mov b6=r16
2025 movl r15=ia32_ret_from_syscall
2026 cmp.eq p8,p0=r2,r0
2027 ;;
2028 mov rp=r15
2029 (p8) br.call.sptk.many b6=b6
2030 br.cond.sptk ia32_trace_syscall
2032 non_ia32_syscall:
2033 alloc r15=ar.pfs,0,0,2,0
2034 mov out0=r14 // interrupt #
2035 add out1=16,sp // pointer to pt_regs
2036 ;; // avoid WAW on CFM
2037 br.call.sptk.many rp=ia32_bad_interrupt
2038 .ret1: movl r15=ia64_leave_kernel
2039 ;;
2040 mov rp=r15
2041 br.ret.sptk.many rp
2042 END(dispatch_to_ia32_handler)
2044 #endif /* CONFIG_IA32_SUPPORT */