ia64/xen-unstable

view linux-2.6-xen-sparse/include/asm-xen/asm-i386/processor.h @ 8534:da7873110bbb

Tiny bootstrap cleanup.

Signed-off-by: Keir Fraser <keir@xensource.com>
author kaf24@firebug.cl.cam.ac.uk
date Mon Jan 09 19:46:46 2006 +0100 (2006-01-09)
parents 06d84bf87159
children
line source
1 /*
2 * include/asm-i386/processor.h
3 *
4 * Copyright (C) 1994 Linus Torvalds
5 */
7 #ifndef __ASM_I386_PROCESSOR_H
8 #define __ASM_I386_PROCESSOR_H
10 #include <asm/vm86.h>
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/page.h>
14 #include <asm/types.h>
15 #include <asm/sigcontext.h>
16 #include <asm/cpufeature.h>
17 #include <asm/msr.h>
18 #include <asm/system.h>
19 #include <linux/cache.h>
20 #include <linux/config.h>
21 #include <linux/threads.h>
22 #include <asm/percpu.h>
24 /* flag for disabling the tsc */
25 extern int tsc_disable;
27 struct desc_struct {
28 unsigned long a,b;
29 };
31 #define desc_empty(desc) \
32 (!((desc)->a + (desc)->b))
34 #define desc_equal(desc1, desc2) \
35 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
36 /*
37 * Default implementation of macro that returns current
38 * instruction pointer ("program counter").
39 */
40 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
42 /*
43 * CPU type and hardware bug flags. Kept separately for each CPU.
44 * Members of this structure are referenced in head.S, so think twice
45 * before touching them. [mj]
46 */
48 struct cpuinfo_x86 {
49 __u8 x86; /* CPU family */
50 __u8 x86_vendor; /* CPU vendor */
51 __u8 x86_model;
52 __u8 x86_mask;
53 char wp_works_ok; /* It doesn't on 386's */
54 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
55 char hard_math;
56 char rfu;
57 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
58 unsigned long x86_capability[NCAPINTS];
59 char x86_vendor_id[16];
60 char x86_model_id[64];
61 int x86_cache_size; /* in KB - valid for CPUS which support this
62 call */
63 int x86_cache_alignment; /* In bytes */
64 int fdiv_bug;
65 int f00f_bug;
66 int coma_bug;
67 unsigned long loops_per_jiffy;
68 unsigned char x86_num_cores;
69 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
71 #define X86_VENDOR_INTEL 0
72 #define X86_VENDOR_CYRIX 1
73 #define X86_VENDOR_AMD 2
74 #define X86_VENDOR_UMC 3
75 #define X86_VENDOR_NEXGEN 4
76 #define X86_VENDOR_CENTAUR 5
77 #define X86_VENDOR_RISE 6
78 #define X86_VENDOR_TRANSMETA 7
79 #define X86_VENDOR_NSC 8
80 #define X86_VENDOR_NUM 9
81 #define X86_VENDOR_UNKNOWN 0xff
83 /*
84 * capabilities of CPUs
85 */
87 extern struct cpuinfo_x86 boot_cpu_data;
88 extern struct cpuinfo_x86 new_cpu_data;
89 extern struct tss_struct doublefault_tss;
90 DECLARE_PER_CPU(struct tss_struct, init_tss);
91 DECLARE_PER_CPU(pgd_t *, cur_pgd);
93 #ifdef CONFIG_SMP
94 extern struct cpuinfo_x86 cpu_data[];
95 #define current_cpu_data cpu_data[smp_processor_id()]
96 #else
97 #define cpu_data (&boot_cpu_data)
98 #define current_cpu_data boot_cpu_data
99 #endif
101 extern int phys_proc_id[NR_CPUS];
102 extern int cpu_core_id[NR_CPUS];
103 extern char ignore_fpu_irq;
105 extern void identify_cpu(struct cpuinfo_x86 *);
106 extern void print_cpu_info(struct cpuinfo_x86 *);
107 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
109 #ifdef CONFIG_X86_HT
110 extern void detect_ht(struct cpuinfo_x86 *c);
111 #else
112 static inline void detect_ht(struct cpuinfo_x86 *c) {}
113 #endif
115 /*
116 * EFLAGS bits
117 */
118 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
119 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
120 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
121 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
122 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
123 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
124 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
125 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
126 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
127 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
128 #define X86_EFLAGS_NT 0x00004000 /* Nested Task */
129 #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
130 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
131 #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
132 #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
133 #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
134 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
136 /*
137 * Generic CPUID function
138 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
139 * resulting in stale register contents being returned.
140 */
141 static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
142 {
143 __asm__("cpuid"
144 : "=a" (*eax),
145 "=b" (*ebx),
146 "=c" (*ecx),
147 "=d" (*edx)
148 : "0" (op), "c"(0));
149 }
151 /* Some CPUID calls want 'count' to be placed in ecx */
152 static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
153 int *edx)
154 {
155 __asm__("cpuid"
156 : "=a" (*eax),
157 "=b" (*ebx),
158 "=c" (*ecx),
159 "=d" (*edx)
160 : "0" (op), "c" (count));
161 }
163 /*
164 * CPUID functions returning a single datum
165 */
166 static inline unsigned int cpuid_eax(unsigned int op)
167 {
168 unsigned int eax;
170 __asm__("cpuid"
171 : "=a" (eax)
172 : "0" (op)
173 : "bx", "cx", "dx");
174 return eax;
175 }
176 static inline unsigned int cpuid_ebx(unsigned int op)
177 {
178 unsigned int eax, ebx;
180 __asm__("cpuid"
181 : "=a" (eax), "=b" (ebx)
182 : "0" (op)
183 : "cx", "dx" );
184 return ebx;
185 }
186 static inline unsigned int cpuid_ecx(unsigned int op)
187 {
188 unsigned int eax, ecx;
190 __asm__("cpuid"
191 : "=a" (eax), "=c" (ecx)
192 : "0" (op)
193 : "bx", "dx" );
194 return ecx;
195 }
196 static inline unsigned int cpuid_edx(unsigned int op)
197 {
198 unsigned int eax, edx;
200 __asm__("cpuid"
201 : "=a" (eax), "=d" (edx)
202 : "0" (op)
203 : "bx", "cx");
204 return edx;
205 }
207 #define load_cr3(pgdir) do { \
208 xen_pt_switch(__pa(pgdir)); \
209 per_cpu(cur_pgd, smp_processor_id()) = pgdir; \
210 } while (/* CONSTCOND */0)
213 /*
214 * Intel CPU features in CR4
215 */
216 #define X86_CR4_VME 0x0001 /* enable vm86 extensions */
217 #define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
218 #define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
219 #define X86_CR4_DE 0x0008 /* enable debugging extensions */
220 #define X86_CR4_PSE 0x0010 /* enable page size extensions */
221 #define X86_CR4_PAE 0x0020 /* enable physical address extensions */
222 #define X86_CR4_MCE 0x0040 /* Machine check enable */
223 #define X86_CR4_PGE 0x0080 /* enable global pages */
224 #define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
225 #define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
226 #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
228 /*
229 * Save the cr4 feature set we're using (ie
230 * Pentium 4MB enable and PPro Global page
231 * enable), so that any CPU's that boot up
232 * after us can get the correct flags.
233 */
234 extern unsigned long mmu_cr4_features;
236 static inline void set_in_cr4 (unsigned long mask)
237 {
238 mmu_cr4_features |= mask;
239 switch (mask) {
240 case X86_CR4_OSFXSR:
241 case X86_CR4_OSXMMEXCPT:
242 break;
243 default:
244 do {
245 const char *msg = "Xen unsupported cr4 update\n";
246 (void)HYPERVISOR_console_io(
247 CONSOLEIO_write, __builtin_strlen(msg),
248 (char *)msg);
249 BUG();
250 } while (0);
251 }
252 }
254 static inline void clear_in_cr4 (unsigned long mask)
255 {
256 mmu_cr4_features &= ~mask;
257 __asm__("movl %%cr4,%%eax\n\t"
258 "andl %0,%%eax\n\t"
259 "movl %%eax,%%cr4\n"
260 : : "irg" (~mask)
261 :"ax");
262 }
264 /*
265 * NSC/Cyrix CPU configuration register indexes
266 */
268 #define CX86_PCR0 0x20
269 #define CX86_GCR 0xb8
270 #define CX86_CCR0 0xc0
271 #define CX86_CCR1 0xc1
272 #define CX86_CCR2 0xc2
273 #define CX86_CCR3 0xc3
274 #define CX86_CCR4 0xe8
275 #define CX86_CCR5 0xe9
276 #define CX86_CCR6 0xea
277 #define CX86_CCR7 0xeb
278 #define CX86_PCR1 0xf0
279 #define CX86_DIR0 0xfe
280 #define CX86_DIR1 0xff
281 #define CX86_ARR_BASE 0xc4
282 #define CX86_RCR_BASE 0xdc
284 /*
285 * NSC/Cyrix CPU indexed register access macros
286 */
288 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
290 #define setCx86(reg, data) do { \
291 outb((reg), 0x22); \
292 outb((data), 0x23); \
293 } while (0)
295 static inline void __monitor(const void *eax, unsigned long ecx,
296 unsigned long edx)
297 {
298 /* "monitor %eax,%ecx,%edx;" */
299 asm volatile(
300 ".byte 0x0f,0x01,0xc8;"
301 : :"a" (eax), "c" (ecx), "d"(edx));
302 }
304 static inline void __mwait(unsigned long eax, unsigned long ecx)
305 {
306 /* "mwait %eax,%ecx;" */
307 asm volatile(
308 ".byte 0x0f,0x01,0xc9;"
309 : :"a" (eax), "c" (ecx));
310 }
312 /* from system description table in BIOS. Mostly for MCA use, but
313 others may find it useful. */
314 extern unsigned int machine_id;
315 extern unsigned int machine_submodel_id;
316 extern unsigned int BIOS_revision;
317 extern unsigned int mca_pentium_flag;
319 /* Boot loader type from the setup header */
320 extern int bootloader_type;
322 /*
323 * User space process size: 3GB (default).
324 */
325 #define TASK_SIZE (PAGE_OFFSET)
327 /* This decides where the kernel will search for a free chunk of vm
328 * space during mmap's.
329 */
330 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
332 #define HAVE_ARCH_PICK_MMAP_LAYOUT
334 /*
335 * Size of io_bitmap.
336 */
337 #define IO_BITMAP_BITS 65536
338 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
339 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
340 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
341 #define INVALID_IO_BITMAP_OFFSET 0x8000
342 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
344 struct i387_fsave_struct {
345 long cwd;
346 long swd;
347 long twd;
348 long fip;
349 long fcs;
350 long foo;
351 long fos;
352 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
353 long status; /* software status information */
354 };
356 struct i387_fxsave_struct {
357 unsigned short cwd;
358 unsigned short swd;
359 unsigned short twd;
360 unsigned short fop;
361 long fip;
362 long fcs;
363 long foo;
364 long fos;
365 long mxcsr;
366 long mxcsr_mask;
367 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
368 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
369 long padding[56];
370 } __attribute__ ((aligned (16)));
372 struct i387_soft_struct {
373 long cwd;
374 long swd;
375 long twd;
376 long fip;
377 long fcs;
378 long foo;
379 long fos;
380 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
381 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
382 struct info *info;
383 unsigned long entry_eip;
384 };
386 union i387_union {
387 struct i387_fsave_struct fsave;
388 struct i387_fxsave_struct fxsave;
389 struct i387_soft_struct soft;
390 };
392 typedef struct {
393 unsigned long seg;
394 } mm_segment_t;
396 struct thread_struct;
398 struct tss_struct {
399 unsigned short back_link,__blh;
400 unsigned long esp0;
401 unsigned short ss0,__ss0h;
402 unsigned long esp1;
403 unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
404 unsigned long esp2;
405 unsigned short ss2,__ss2h;
406 unsigned long __cr3;
407 unsigned long eip;
408 unsigned long eflags;
409 unsigned long eax,ecx,edx,ebx;
410 unsigned long esp;
411 unsigned long ebp;
412 unsigned long esi;
413 unsigned long edi;
414 unsigned short es, __esh;
415 unsigned short cs, __csh;
416 unsigned short ss, __ssh;
417 unsigned short ds, __dsh;
418 unsigned short fs, __fsh;
419 unsigned short gs, __gsh;
420 unsigned short ldt, __ldth;
421 unsigned short trace, io_bitmap_base;
422 /*
423 * The extra 1 is there because the CPU will access an
424 * additional byte beyond the end of the IO permission
425 * bitmap. The extra byte must be all 1 bits, and must
426 * be within the limit.
427 */
428 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
429 /*
430 * Cache the current maximum and the last task that used the bitmap:
431 */
432 unsigned long io_bitmap_max;
433 struct thread_struct *io_bitmap_owner;
434 /*
435 * pads the TSS to be cacheline-aligned (size is 0x100)
436 */
437 unsigned long __cacheline_filler[35];
438 /*
439 * .. and then another 0x100 bytes for emergency kernel stack
440 */
441 unsigned long stack[64];
442 } __attribute__((packed));
444 #define ARCH_MIN_TASKALIGN 16
446 struct thread_struct {
447 /* cached TLS descriptors. */
448 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
449 unsigned long esp0;
450 unsigned long sysenter_cs;
451 unsigned long eip;
452 unsigned long esp;
453 unsigned long fs;
454 unsigned long gs;
455 unsigned int io_pl;
456 /* Hardware debugging registers */
457 unsigned long debugreg[8]; /* %%db0-7 debug registers */
458 /* fault info */
459 unsigned long cr2, trap_no, error_code;
460 /* floating point info */
461 union i387_union i387;
462 /* virtual 86 mode info */
463 struct vm86_struct __user * vm86_info;
464 unsigned long screen_bitmap;
465 unsigned long v86flags, v86mask, saved_esp0;
466 unsigned int saved_fs, saved_gs;
467 /* IO permissions */
468 unsigned long *io_bitmap_ptr;
469 /* max allowed port in the bitmap, in bytes: */
470 unsigned long io_bitmap_max;
471 };
473 #define INIT_THREAD { \
474 .vm86_info = NULL, \
475 .sysenter_cs = __KERNEL_CS, \
476 .io_bitmap_ptr = NULL, \
477 }
479 /*
480 * Note that the .io_bitmap member must be extra-big. This is because
481 * the CPU will access an additional byte beyond the end of the IO
482 * permission bitmap. The extra byte must be all 1 bits, and must
483 * be within the limit.
484 */
485 #define INIT_TSS { \
486 .esp0 = sizeof(init_stack) + (long)&init_stack, \
487 .ss0 = __KERNEL_DS, \
488 .ss1 = __KERNEL_CS, \
489 .ldt = GDT_ENTRY_LDT, \
490 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
491 .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
492 }
494 static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread)
495 {
496 tss->esp0 = thread->esp0;
497 /* This can only happen when SEP is enabled, no need to test "SEP"arately */
498 if (unlikely(tss->ss1 != thread->sysenter_cs)) {
499 tss->ss1 = thread->sysenter_cs;
500 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
501 }
502 HYPERVISOR_stack_switch(tss->ss0, tss->esp0);
503 }
505 #define start_thread(regs, new_eip, new_esp) do { \
506 __asm__("movl %0,%%fs ; movl %0,%%gs": :"r" (0)); \
507 set_fs(USER_DS); \
508 regs->xds = __USER_DS; \
509 regs->xes = __USER_DS; \
510 regs->xss = __USER_DS; \
511 regs->xcs = __USER_CS; \
512 regs->eip = new_eip; \
513 regs->esp = new_esp; \
514 } while (0)
516 /*
517 * This special macro can be used to load a debugging register
518 */
519 #define loaddebug(thread,register) \
520 HYPERVISOR_set_debugreg((register), \
521 ((thread)->debugreg[register]))
523 /* Forward declaration, a strange C thing */
524 struct task_struct;
525 struct mm_struct;
527 /* Free all resources held by a thread. */
528 extern void release_thread(struct task_struct *);
530 /* Prepare to copy thread state - unlazy all lazy status */
531 extern void prepare_to_copy(struct task_struct *tsk);
533 /*
534 * create a kernel thread without removing it from tasklists
535 */
536 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
538 extern unsigned long thread_saved_pc(struct task_struct *tsk);
539 void show_trace(struct task_struct *task, unsigned long *stack);
541 unsigned long get_wchan(struct task_struct *p);
543 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
544 #define KSTK_TOP(info) \
545 ({ \
546 unsigned long *__ptr = (unsigned long *)(info); \
547 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
548 })
550 #define task_pt_regs(task) \
551 ({ \
552 struct pt_regs *__regs__; \
553 __regs__ = (struct pt_regs *)KSTK_TOP((task)->thread_info); \
554 __regs__ - 1; \
555 })
557 #define KSTK_EIP(task) (task_pt_regs(task)->eip)
558 #define KSTK_ESP(task) (task_pt_regs(task)->esp)
561 struct microcode_header {
562 unsigned int hdrver;
563 unsigned int rev;
564 unsigned int date;
565 unsigned int sig;
566 unsigned int cksum;
567 unsigned int ldrver;
568 unsigned int pf;
569 unsigned int datasize;
570 unsigned int totalsize;
571 unsigned int reserved[3];
572 };
574 struct microcode {
575 struct microcode_header hdr;
576 unsigned int bits[0];
577 };
579 typedef struct microcode microcode_t;
580 typedef struct microcode_header microcode_header_t;
582 /* microcode format is extended from prescott processors */
583 struct extended_signature {
584 unsigned int sig;
585 unsigned int pf;
586 unsigned int cksum;
587 };
589 struct extended_sigtable {
590 unsigned int count;
591 unsigned int cksum;
592 unsigned int reserved[3];
593 struct extended_signature sigs[0];
594 };
595 /* '6' because it used to be for P6 only (but now covers Pentium 4 as well) */
596 #define MICROCODE_IOCFREE _IO('6',0)
598 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
599 static inline void rep_nop(void)
600 {
601 __asm__ __volatile__("rep;nop": : :"memory");
602 }
604 #define cpu_relax() rep_nop()
606 /* generic versions from gas */
607 #define GENERIC_NOP1 ".byte 0x90\n"
608 #define GENERIC_NOP2 ".byte 0x89,0xf6\n"
609 #define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
610 #define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
611 #define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
612 #define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
613 #define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
614 #define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
616 /* Opteron nops */
617 #define K8_NOP1 GENERIC_NOP1
618 #define K8_NOP2 ".byte 0x66,0x90\n"
619 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
620 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
621 #define K8_NOP5 K8_NOP3 K8_NOP2
622 #define K8_NOP6 K8_NOP3 K8_NOP3
623 #define K8_NOP7 K8_NOP4 K8_NOP3
624 #define K8_NOP8 K8_NOP4 K8_NOP4
626 /* K7 nops */
627 /* uses eax dependencies (arbitary choice) */
628 #define K7_NOP1 GENERIC_NOP1
629 #define K7_NOP2 ".byte 0x8b,0xc0\n"
630 #define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
631 #define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
632 #define K7_NOP5 K7_NOP4 ASM_NOP1
633 #define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
634 #define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
635 #define K7_NOP8 K7_NOP7 ASM_NOP1
637 #ifdef CONFIG_MK8
638 #define ASM_NOP1 K8_NOP1
639 #define ASM_NOP2 K8_NOP2
640 #define ASM_NOP3 K8_NOP3
641 #define ASM_NOP4 K8_NOP4
642 #define ASM_NOP5 K8_NOP5
643 #define ASM_NOP6 K8_NOP6
644 #define ASM_NOP7 K8_NOP7
645 #define ASM_NOP8 K8_NOP8
646 #elif defined(CONFIG_MK7)
647 #define ASM_NOP1 K7_NOP1
648 #define ASM_NOP2 K7_NOP2
649 #define ASM_NOP3 K7_NOP3
650 #define ASM_NOP4 K7_NOP4
651 #define ASM_NOP5 K7_NOP5
652 #define ASM_NOP6 K7_NOP6
653 #define ASM_NOP7 K7_NOP7
654 #define ASM_NOP8 K7_NOP8
655 #else
656 #define ASM_NOP1 GENERIC_NOP1
657 #define ASM_NOP2 GENERIC_NOP2
658 #define ASM_NOP3 GENERIC_NOP3
659 #define ASM_NOP4 GENERIC_NOP4
660 #define ASM_NOP5 GENERIC_NOP5
661 #define ASM_NOP6 GENERIC_NOP6
662 #define ASM_NOP7 GENERIC_NOP7
663 #define ASM_NOP8 GENERIC_NOP8
664 #endif
666 #define ASM_NOP_MAX 8
668 /* Prefetch instructions for Pentium III and AMD Athlon */
669 /* It's not worth to care about 3dnow! prefetches for the K6
670 because they are microcoded there and very slow.
671 However we don't do prefetches for pre XP Athlons currently
672 That should be fixed. */
673 #define ARCH_HAS_PREFETCH
674 extern inline void prefetch(const void *x)
675 {
676 alternative_input(ASM_NOP4,
677 "prefetchnta (%1)",
678 X86_FEATURE_XMM,
679 "r" (x));
680 }
682 #define ARCH_HAS_PREFETCH
683 #define ARCH_HAS_PREFETCHW
684 #define ARCH_HAS_SPINLOCK_PREFETCH
686 /* 3dnow! prefetch to get an exclusive cache line. Useful for
687 spinlocks to avoid one state transition in the cache coherency protocol. */
688 extern inline void prefetchw(const void *x)
689 {
690 alternative_input(ASM_NOP4,
691 "prefetchw (%1)",
692 X86_FEATURE_3DNOW,
693 "r" (x));
694 }
695 #define spin_lock_prefetch(x) prefetchw(x)
697 extern void select_idle_routine(const struct cpuinfo_x86 *c);
699 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
701 extern unsigned long boot_option_idle_override;
703 #endif /* __ASM_I386_PROCESSOR_H */