ia64/xen-unstable

view xen/include/asm-ia64/vmx_mm_def.h @ 5704:9b73afea874e

Certain types of event channel are now auto-bound to vcpu0 by Xen.
Make sure that xenolinux agrees with this.
author sos22@douglas.cl.cam.ac.uk
date Fri Jul 08 15:35:43 2005 +0000 (2005-07-08)
parents c91f74efda05
children 67ea7868089b
line source
1 /* -*- Mode:C; c-basic-offset:4; tab-width:4; indent-tabs-mode:nil -*- */
2 /*
3 * vmx_mm_def.h:
4 * Copyright (c) 2004, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
17 * Place - Suite 330, Boston, MA 02111-1307 USA.
18 *
19 * Kun Tian (Kevin Tian) (kevin.tian@intel.com)
20 */
21 #ifndef _MM_DEF_H_
22 #define _MM_DEF_H_
25 /* VHPT size 4M */
26 //#define VHPT_SIZE_PS 22
27 //#define VHPT_SIZE (1 << VHPT_SIZE_PS)
28 #define ARCH_PAGE_SHIFT 12
29 #define ARCH_PAGE_SIZE PSIZE(ARCH_PAGE_SHIFT)
30 #define INVALID_MFN (-1)
32 #define MAX_PHYS_ADDR_BITS 50
33 #define PMASK(size) (~((size) - 1))
34 #define PSIZE(size) (1UL<<(size))
35 //#define PAGE_SIZE_4K PSIZE(12)
36 #define POFFSET(vaddr, ps) ((vaddr) & (PSIZE(ps) - 1))
37 #define PPN_2_PA(ppn) ((ppn)<<12)
38 #define CLEARLSB(ppn, nbits) ((((uint64_t)ppn) >> (nbits)) << (nbits))
39 #define PAGEALIGN(va, ps) (va & ~(PSIZE(ps)-1))
41 #define TLB_AR_R 0
42 #define TLB_AR_RX 1
43 #define TLB_AR_RW 2
44 #define TLB_AR_RWX 3
45 #define TLB_AR_R_RW 4
46 #define TLB_AR_RX_RWX 5
47 #define TLB_AR_RWX_RW 6
48 #define TLB_AR_XP 7
50 #define IA64_ISR_CODE_MASK0 0xf
51 #define IA64_UNIMPL_DADDR_FAULT 0x30
52 #define IA64_UNIMPL_IADDR_TRAP 0x10
53 #define IA64_RESERVED_REG_FAULT 0x30
54 #define IA64_REG_NAT_CONSUMPTION_FAULT 0x10
55 #define IA64_NAT_CONSUMPTION_FAULT 0x20
56 #define IA64_PRIV_OP_FAULT 0x10
58 #define DEFER_NONE 0
59 #define DEFER_ALWAYS 0x1
60 #define DEFER_DM 0x100 /* bit 8 */
61 #define DEFER_DP 0X200 /* bit 9 */
62 #define DEFER_DK 0x400 /* bit 10 */
63 #define DEFER_DX 0x800 /* bit 11 */
64 #define DEFER_DR 0x1000 /* bit 12 */
65 #define DEFER_DA 0x2000 /* bit 13 */
66 #define DEFER_DD 0x4000 /* bit 14 */
68 #define ACCESS_RIGHT(a) ((a) & (ACCESS_FETCHADD - 1))
70 #define ACCESS_READ 0x1
71 #define ACCESS_WRITE 0x2
72 #define ACCESS_EXECUTE 0x4
73 #define ACCESS_XP0 0x8
74 #define ACCESS_XP1 0x10
75 #define ACCESS_XP2 0x20
76 #define ACCESS_FETCHADD 0x40
77 #define ACCESS_XCHG 0x80
78 #define ACCESS_CMPXCHG 0x100
80 #define ACCESS_SIZE_1 0x10000
81 #define ACCESS_SIZE_2 0x20000
82 #define ACCESS_SIZE_4 0x40000
83 #define ACCESS_SIZE_8 0x80000
84 #define ACCESS_SIZE_10 0x100000
85 #define ACCESS_SIZE_16 0x200000
87 #define STLB_TC 0
88 #define STLB_TR 1
90 #define VMM_RR_MASK 0xfffff
91 #define VMM_RR_SHIFT 20
93 #define IA64_RR_SHIFT 61
95 #define PHYS_PAGE_SHIFT PPN_SHIFT
97 #define STLB_SZ_SHIFT 8 // 256
98 #define STLB_SIZE (1UL<<STLB_SZ_SHIFT)
99 #define STLB_PPS_SHIFT 12
100 #define STLB_PPS (1UL<<STLB_PPS_SHIFT)
101 #define GUEST_TRNUM 8
103 /* Virtual address memory attributes encoding */
104 #define VA_MATTR_WB 0x0
105 #define VA_MATTR_UC 0x4
106 #define VA_MATTR_UCE 0x5
107 #define VA_MATTR_WC 0x6
108 #define VA_MATTR_NATPAGE 0x7
110 #define VRN_MASK 0xe000000000000000L
111 #define PTA_BASE_MASK 0x3fffffffffffL
112 #define PTA_BASE_SHIFT 15
113 #define VHPT_OFFSET_MASK 0x7fff
115 #define BITS_SHIFT_256MB 28
116 #define SIZE_256MB (1UL<<BITS_SHIFT_256MB)
117 #define TLB_GR_RV_BITS ((1UL<<1) | (3UL<<50))
118 #define HPA_MAPPING_ATTRIBUTE 0x61 //ED:0;AR:0;PL:0;D:1;A:1;P:1
119 #define VPN_2_VRN(vpn) ((vpn << PPN_SHIFT) >> IA64_VRN_SHIFT)
121 typedef enum { INSTRUCTION, DATA, REGISTER } miss_type;
123 //typedef enum { MVHPT, STLB } vtlb_loc_type_t;
124 typedef enum { DATA_REF, NA_REF, INST_REF, RSE_REF } vhpt_ref_t;
126 typedef enum {
127 PIB_MMIO=0,
128 VGA_BUFF,
129 CHIPSET_IO,
130 LOW_MMIO,
131 LEGACY_IO,
132 IO_SAPIC,
133 NOT_IO
134 } mmio_type_t;
136 typedef struct mmio_list {
137 mmio_type_t iot;
138 u64 start; // start address of this memory IO block
139 u64 end; // end address (include this one)
140 } mmio_list_t;
142 static __inline__ uint64_t
143 bits_v(uint64_t v, uint32_t bs, uint32_t be)
144 {
145 uint64_t result;
146 __asm __volatile("shl %0=%1, %2;; shr.u %0=%0, %3;;"
147 : "=r" (result): "r"(v), "r"(63-be), "r" (bs+63-be) );
148 }
150 #define bits(val, bs, be) \
151 ({ \
152 u64 ret; \
153 \
154 __asm __volatile("extr.u %0=%1, %2, %3" \
155 : "=r" (ret): "r"(val), \
156 "M" ((bs)), \
157 "M" ((be) - (bs) + 1) ); \
158 ret; \
159 })
161 /*
162 * clear bits (pos, len) from v.
163 *
164 */
165 #define clearbits(v, pos, len) \
166 ({ \
167 u64 ret; \
168 \
169 __asm __volatile("dep.z %0=%1, %2, %3" \
170 : "=r" (ret): "r"(v), \
171 "M" ((pos)), \
172 "M" ((len))); \
173 ret; \
174 })
176 #endif