ia64/xen-unstable

view xen/drivers/char/ns16550.c @ 18887:3db54d2aa8bd

powernow: implement struct cpufreq_driver.verify

Without this, under rare conditions hypervisor crashes are possible
due to this method being called without checking against NULL.

Signed-off-by: Jan Beulich <jbeulich@novell.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Dec 05 15:22:21 2008 +0000 (2008-12-05)
parents cb289056b523
children
line source
1 /******************************************************************************
2 * ns16550.c
3 *
4 * Driver for 16550-series UARTs. This driver is to be kept within Xen as
5 * it permits debugging of seriously-toasted machines (e.g., in situations
6 * where a device driver within a guest OS would be inaccessible).
7 *
8 * Copyright (c) 2003-2005, K A Fraser
9 */
11 #include <xen/config.h>
12 #include <xen/console.h>
13 #include <xen/init.h>
14 #include <xen/irq.h>
15 #include <xen/sched.h>
16 #include <xen/serial.h>
17 #include <xen/iocap.h>
18 #include <asm/io.h>
20 /*
21 * Configure serial port with a string:
22 * <baud>[/<clock_hz>][,DPS[,<io-base>[,<irq>]]].
23 * The tail of the string can be omitted if platform defaults are sufficient.
24 * If the baud rate is pre-configured, perhaps by a bootloader, then 'auto'
25 * can be specified in place of a numeric baud rate. Polled mode is specified
26 * by requesting irq 0.
27 */
28 static char opt_com1[30] = "", opt_com2[30] = "";
29 string_param("com1", opt_com1);
30 string_param("com2", opt_com2);
32 static struct ns16550 {
33 int baud, clock_hz, data_bits, parity, stop_bits, irq;
34 unsigned long io_base; /* I/O port or memory-mapped I/O address. */
35 char *remapped_io_base; /* Remapped virtual address of mmap I/O. */
36 /* UART with IRQ line: interrupt-driven I/O. */
37 struct irqaction irqaction;
38 /* UART with no IRQ line: periodically-polled I/O. */
39 struct timer timer;
40 unsigned int timeout_ms;
41 } ns16550_com[2] = { { 0 } };
43 /* Register offsets */
44 #define RBR 0x00 /* receive buffer */
45 #define THR 0x00 /* transmit holding */
46 #define IER 0x01 /* interrupt enable */
47 #define IIR 0x02 /* interrupt identity */
48 #define FCR 0x02 /* FIFO control */
49 #define LCR 0x03 /* line control */
50 #define MCR 0x04 /* Modem control */
51 #define LSR 0x05 /* line status */
52 #define MSR 0x06 /* Modem status */
53 #define DLL 0x00 /* divisor latch (ls) (DLAB=1) */
54 #define DLM 0x01 /* divisor latch (ms) (DLAB=1) */
56 /* Interrupt Enable Register */
57 #define IER_ERDAI 0x01 /* rx data recv'd */
58 #define IER_ETHREI 0x02 /* tx reg. empty */
59 #define IER_ELSI 0x04 /* rx line status */
60 #define IER_EMSI 0x08 /* MODEM status */
62 /* Interrupt Identification Register */
63 #define IIR_NOINT 0x01 /* no interrupt pending */
64 #define IIR_IMASK 0x06 /* interrupt identity: */
65 #define IIR_LSI 0x06 /* - rx line status */
66 #define IIR_RDAI 0x04 /* - rx data recv'd */
67 #define IIR_THREI 0x02 /* - tx reg. empty */
68 #define IIR_MSI 0x00 /* - MODEM status */
70 /* FIFO Control Register */
71 #define FCR_ENABLE 0x01 /* enable FIFO */
72 #define FCR_CLRX 0x02 /* clear Rx FIFO */
73 #define FCR_CLTX 0x04 /* clear Tx FIFO */
74 #define FCR_DMA 0x10 /* enter DMA mode */
75 #define FCR_TRG1 0x00 /* Rx FIFO trig lev 1 */
76 #define FCR_TRG4 0x40 /* Rx FIFO trig lev 4 */
77 #define FCR_TRG8 0x80 /* Rx FIFO trig lev 8 */
78 #define FCR_TRG14 0xc0 /* Rx FIFO trig lev 14 */
80 /* Line Control Register */
81 #define LCR_DLAB 0x80 /* Divisor Latch Access */
83 /* Modem Control Register */
84 #define MCR_DTR 0x01 /* Data Terminal Ready */
85 #define MCR_RTS 0x02 /* Request to Send */
86 #define MCR_OUT2 0x08 /* OUT2: interrupt mask */
87 #define MCR_LOOP 0x10 /* Enable loopback test mode */
89 /* Line Status Register */
90 #define LSR_DR 0x01 /* Data ready */
91 #define LSR_OE 0x02 /* Overrun */
92 #define LSR_PE 0x04 /* Parity error */
93 #define LSR_FE 0x08 /* Framing error */
94 #define LSR_BI 0x10 /* Break */
95 #define LSR_THRE 0x20 /* Xmit hold reg empty */
96 #define LSR_TEMT 0x40 /* Xmitter empty */
97 #define LSR_ERR 0x80 /* Error */
99 /* These parity settings can be ORed directly into the LCR. */
100 #define PARITY_NONE (0<<3)
101 #define PARITY_ODD (1<<3)
102 #define PARITY_EVEN (3<<3)
103 #define PARITY_MARK (5<<3)
104 #define PARITY_SPACE (7<<3)
106 /* Frequency of external clock source. This definition assumes PC platform. */
107 #define UART_CLOCK_HZ 1843200
109 static char ns_read_reg(struct ns16550 *uart, int reg)
110 {
111 if ( uart->remapped_io_base == NULL )
112 return inb(uart->io_base + reg);
113 return readb(uart->remapped_io_base + reg);
114 }
116 static void ns_write_reg(struct ns16550 *uart, int reg, char c)
117 {
118 if ( uart->remapped_io_base == NULL )
119 return outb(c, uart->io_base + reg);
120 writeb(c, uart->remapped_io_base + reg);
121 }
123 static void ns16550_interrupt(
124 int irq, void *dev_id, struct cpu_user_regs *regs)
125 {
126 struct serial_port *port = dev_id;
127 struct ns16550 *uart = port->uart;
129 while ( !(ns_read_reg(uart, IIR) & IIR_NOINT) )
130 {
131 char lsr = ns_read_reg(uart, LSR);
132 if ( lsr & LSR_THRE )
133 serial_tx_interrupt(port, regs);
134 if ( lsr & LSR_DR )
135 serial_rx_interrupt(port, regs);
136 }
137 }
139 static void ns16550_poll(void *data)
140 {
141 struct serial_port *port = data;
142 struct ns16550 *uart = port->uart;
143 struct cpu_user_regs *regs = guest_cpu_user_regs();
145 while ( ns_read_reg(uart, LSR) & LSR_DR )
146 serial_rx_interrupt(port, regs);
148 if ( ns_read_reg(uart, LSR) & LSR_THRE )
149 serial_tx_interrupt(port, regs);
151 set_timer(&uart->timer, NOW() + MILLISECS(uart->timeout_ms));
152 }
154 static int ns16550_tx_empty(struct serial_port *port)
155 {
156 struct ns16550 *uart = port->uart;
157 return !!(ns_read_reg(uart, LSR) & LSR_THRE);
158 }
160 static void ns16550_putc(struct serial_port *port, char c)
161 {
162 struct ns16550 *uart = port->uart;
163 ns_write_reg(uart, THR, c);
164 }
166 static int ns16550_getc(struct serial_port *port, char *pc)
167 {
168 struct ns16550 *uart = port->uart;
170 if ( !(ns_read_reg(uart, LSR) & LSR_DR) )
171 return 0;
173 *pc = ns_read_reg(uart, RBR);
174 return 1;
175 }
177 static void __devinit ns16550_init_preirq(struct serial_port *port)
178 {
179 struct ns16550 *uart = port->uart;
180 unsigned char lcr;
181 unsigned int divisor;
183 /* I/O ports are distinguished by their size (16 bits). */
184 if ( uart->io_base >= 0x10000 )
185 uart->remapped_io_base = (char *)ioremap(uart->io_base, 8);
187 lcr = (uart->data_bits - 5) | ((uart->stop_bits - 1) << 2) | uart->parity;
189 /* No interrupts. */
190 ns_write_reg(uart, IER, 0);
192 /* Line control and baud-rate generator. */
193 ns_write_reg(uart, LCR, lcr | LCR_DLAB);
194 if ( uart->baud != BAUD_AUTO )
195 {
196 /* Baud rate specified: program it into the divisor latch. */
197 divisor = uart->clock_hz / (uart->baud << 4);
198 ns_write_reg(uart, DLL, (char)divisor);
199 ns_write_reg(uart, DLM, (char)(divisor >> 8));
200 }
201 else
202 {
203 /* Baud rate already set: read it out from the divisor latch. */
204 divisor = ns_read_reg(uart, DLL);
205 divisor |= ns_read_reg(uart, DLM) << 8;
206 uart->baud = uart->clock_hz / (divisor << 4);
207 }
208 ns_write_reg(uart, LCR, lcr);
210 /* No flow ctrl: DTR and RTS are both wedged high to keep remote happy. */
211 ns_write_reg(uart, MCR, MCR_DTR | MCR_RTS);
213 /* Enable and clear the FIFOs. Set a large trigger threshold. */
214 ns_write_reg(uart, FCR, FCR_ENABLE | FCR_CLRX | FCR_CLTX | FCR_TRG14);
216 /* Check this really is a 16550+. Otherwise we have no FIFOs. */
217 if ( (ns_read_reg(uart, IIR) & 0xc0) == 0xc0 )
218 port->tx_fifo_size = 16;
219 }
221 static void __devinit ns16550_init_postirq(struct serial_port *port)
222 {
223 struct ns16550 *uart = port->uart;
224 int rc, bits;
226 if ( uart->irq < 0 )
227 return;
229 serial_async_transmit(port);
231 if ( uart->irq == 0 )
232 {
233 /* Polled mode. Calculate time to fill RX FIFO and/or empty TX FIFO. */
234 bits = uart->data_bits + uart->stop_bits + !!uart->parity;
235 uart->timeout_ms = max_t(
236 unsigned int, 1, (bits * port->tx_fifo_size * 1000) / uart->baud);
237 init_timer(&uart->timer, ns16550_poll, port, 0);
238 set_timer(&uart->timer, NOW() + MILLISECS(uart->timeout_ms));
239 }
240 else
241 {
242 uart->irqaction.handler = ns16550_interrupt;
243 uart->irqaction.name = "ns16550";
244 uart->irqaction.dev_id = port;
245 if ( (rc = setup_irq(uart->irq, &uart->irqaction)) != 0 )
246 printk("ERROR: Failed to allocate ns16550 IRQ %d\n", uart->irq);
248 /* Master interrupt enable; also keep DTR/RTS asserted. */
249 ns_write_reg(uart, MCR, MCR_OUT2 | MCR_DTR | MCR_RTS);
251 /* Enable receive and transmit interrupts. */
252 ns_write_reg(uart, IER, IER_ERDAI | IER_ETHREI);
253 }
254 }
256 #ifdef CONFIG_X86
257 static void __init ns16550_endboot(struct serial_port *port)
258 {
259 struct ns16550 *uart = port->uart;
260 if ( ioports_deny_access(dom0, uart->io_base, uart->io_base + 7) != 0 )
261 BUG();
262 }
263 #else
264 #define ns16550_endboot NULL
265 #endif
267 static int ns16550_irq(struct serial_port *port)
268 {
269 struct ns16550 *uart = port->uart;
270 return ((uart->irq > 0) ? uart->irq : -1);
271 }
273 static struct uart_driver ns16550_driver = {
274 .init_preirq = ns16550_init_preirq,
275 .init_postirq = ns16550_init_postirq,
276 .endboot = ns16550_endboot,
277 .tx_empty = ns16550_tx_empty,
278 .putc = ns16550_putc,
279 .getc = ns16550_getc,
280 .irq = ns16550_irq
281 };
283 static int __init parse_parity_char(int c)
284 {
285 switch ( c )
286 {
287 case 'n':
288 return PARITY_NONE;
289 case 'o':
290 return PARITY_ODD;
291 case 'e':
292 return PARITY_EVEN;
293 case 'm':
294 return PARITY_MARK;
295 case 's':
296 return PARITY_SPACE;
297 }
298 return 0;
299 }
301 static int check_existence(struct ns16550 *uart)
302 {
303 unsigned char status, scratch, scratch2, scratch3;
305 /*
306 * We can't poke MMIO UARTs until they get I/O remapped later. Assume that
307 * if we're getting MMIO UARTs, the arch code knows what it's doing.
308 */
309 if ( uart->io_base >= 0x10000 )
310 return 1;
312 /*
313 * Do a simple existence test first; if we fail this,
314 * there's no point trying anything else.
315 */
316 scratch = ns_read_reg(uart, IER);
317 ns_write_reg(uart, IER, 0);
319 /*
320 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
321 * 16C754B) allow only to modify them if an EFR bit is set.
322 */
323 scratch2 = ns_read_reg(uart, IER) & 0x0f;
324 ns_write_reg(uart, IER, 0x0F);
325 scratch3 = ns_read_reg(uart, IER) & 0x0f;
326 ns_write_reg(uart, IER, scratch);
327 if ( (scratch2 != 0) || (scratch3 != 0x0F) )
328 return 0;
330 /*
331 * Check to see if a UART is really there.
332 * Use loopback test mode.
333 */
334 ns_write_reg(uart, MCR, MCR_LOOP | 0x0A);
335 status = ns_read_reg(uart, MSR) & 0xF0;
336 return (status == 0x90);
337 }
339 #define PARSE_ERR(_f, _a...) \
340 do { \
341 printk( "ERROR: " _f "\n" , ## _a ); \
342 return; \
343 } while ( 0 )
345 static void __init ns16550_parse_port_config(
346 struct ns16550 *uart, const char *conf)
347 {
348 int baud;
350 /* No user-specified configuration? */
351 if ( (conf == NULL) || (*conf == '\0') )
352 {
353 /* Some platforms may automatically probe the UART configuartion. */
354 if ( uart->baud != 0 )
355 goto config_parsed;
356 return;
357 }
359 if ( strncmp(conf, "auto", 4) == 0 )
360 {
361 uart->baud = BAUD_AUTO;
362 conf += 4;
363 }
364 else if ( (baud = simple_strtoul(conf, &conf, 10)) != 0 )
365 uart->baud = baud;
367 if ( *conf == '/')
368 {
369 conf++;
370 uart->clock_hz = simple_strtoul(conf, &conf, 0) << 4;
371 }
373 if ( *conf != ',' )
374 goto config_parsed;
375 conf++;
377 uart->data_bits = simple_strtoul(conf, &conf, 10);
379 uart->parity = parse_parity_char(*conf);
380 conf++;
382 uart->stop_bits = simple_strtoul(conf, &conf, 10);
384 if ( *conf == ',' )
385 {
386 conf++;
387 uart->io_base = simple_strtoul(conf, &conf, 0);
389 if ( *conf == ',' )
390 {
391 conf++;
392 uart->irq = simple_strtoul(conf, &conf, 10);
393 }
394 }
396 config_parsed:
397 /* Sanity checks. */
398 if ( (uart->baud != BAUD_AUTO) &&
399 ((uart->baud < 1200) || (uart->baud > 115200)) )
400 PARSE_ERR("Baud rate %d outside supported range.", uart->baud);
401 if ( (uart->data_bits < 5) || (uart->data_bits > 8) )
402 PARSE_ERR("%d data bits are unsupported.", uart->data_bits);
403 if ( (uart->stop_bits < 1) || (uart->stop_bits > 2) )
404 PARSE_ERR("%d stop bits are unsupported.", uart->stop_bits);
405 if ( uart->io_base == 0 )
406 PARSE_ERR("I/O base address must be specified.");
407 if ( !check_existence(uart) )
408 PARSE_ERR("16550-compatible serial UART not present");
410 /* Register with generic serial driver. */
411 serial_register_uart(uart - ns16550_com, &ns16550_driver, uart);
412 }
414 void __init ns16550_init(int index, struct ns16550_defaults *defaults)
415 {
416 struct ns16550 *uart;
418 if ( (index < 0) || (index > 1) )
419 return;
421 uart = &ns16550_com[index];
423 uart->baud = (defaults->baud ? :
424 console_has((index == 0) ? "com1" : "com2")
425 ? BAUD_AUTO : 0);
426 uart->clock_hz = UART_CLOCK_HZ;
427 uart->data_bits = defaults->data_bits;
428 uart->parity = parse_parity_char(defaults->parity);
429 uart->stop_bits = defaults->stop_bits;
430 uart->irq = defaults->irq;
431 uart->io_base = defaults->io_base;
433 ns16550_parse_port_config(uart, (index == 0) ? opt_com1 : opt_com2);
434 }
436 /*
437 * Local variables:
438 * mode: C
439 * c-set-style: "BSD"
440 * c-basic-offset: 4
441 * tab-width: 4
442 * indent-tabs-mode: nil
443 * End:
444 */