1.1 --- a/xen/arch/ia64/vmx/vmx_ivt.S	Mon Jun 04 14:17:54 2007 -0600
     1.2 +++ b/xen/arch/ia64/vmx/vmx_ivt.S	Wed Jun 06 09:10:52 2007 -0600
     1.3 @@ -315,9 +315,6 @@ ENTRY(vmx_alt_itlb_miss)
     1.4  vmx_alt_itlb_miss_1:
     1.5      mov r16=cr.ifa    // get address that caused the TLB miss
     1.6      ;;
     1.7 -    tbit.z p6,p7=r16,63
     1.8 -(p6)br.spnt vmx_fault_3
     1.9 -    ;;
    1.10      movl r17=PAGE_KERNEL
    1.11      mov r24=cr.ipsr
    1.12      movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
    1.13 @@ -328,8 +325,8 @@ vmx_alt_itlb_miss_1:
    1.14      and r18=0x10,r18    // bit 4=address-bit(61)
    1.15      or r19=r17,r19      // insert PTE control bits into r19
    1.16      ;;
    1.17 -    movl r20=IA64_GRANULE_SHIFT<<2
    1.18 -    or r19=r19,r18	// set bit 4 (uncached) if the access was to region 6
    1.19 +    mov r20=IA64_GRANULE_SHIFT<<2
    1.20 +    or r19=r19,r18	// set bit 4 (uncached) if the access was to UC region
    1.21      ;;
    1.22      mov cr.itir=r20
    1.23      ;;
    1.24 @@ -359,9 +356,6 @@ vmx_alt_dtlb_miss_1:
    1.25      cmp.eq p8,p0=((VIRT_FRAME_TABLE_ADDR>>56)&0xff)-0x100,r22
    1.26  (p8)br.cond.sptk frametable_miss ;;
    1.27  #endif
    1.28 -    tbit.z p6,p7=r16,63
    1.29 -(p6)br.spnt vmx_fault_4
    1.30 -    ;;
    1.31      movl r17=PAGE_KERNEL
    1.32      mov r20=cr.isr
    1.33      movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
    1.34 @@ -378,9 +372,9 @@ vmx_alt_dtlb_miss_1:
    1.35      dep r24=-1,r24,IA64_PSR_ED_BIT,1
    1.36      or r19=r19,r17				// insert PTE control bits into r19
    1.37      ;;
    1.38 -    or r19=r19,r18				// set bit 4 (uncached) if the access was to region 6
    1.39 +    or r19=r19,r18				// set bit 4 (uncached) if the access was to UC region
    1.40  (p6)mov cr.ipsr=r24
    1.41 -    movl r20=IA64_GRANULE_SHIFT<<2
    1.42 +    mov r20=IA64_GRANULE_SHIFT<<2
    1.43      ;;
    1.44      mov cr.itir=r20
    1.45      ;;