1.1 --- a/xen/arch/x86/hvm/svm/svm.c	Tue Jul 03 11:24:40 2007 +0100
     1.2 +++ b/xen/arch/x86/hvm/svm/svm.c	Tue Jul 03 11:41:25 2007 +0100
     1.3 @@ -807,9 +807,9 @@ static void svm_ctxt_switch_from(struct 
     1.4  
     1.5  #ifdef __x86_64__
     1.6      /* Resume use of ISTs now that the host TR is reinstated. */
     1.7 -    idt_tables[cpu][TRAP_double_fault].a  |= 1UL << 32; /* IST1 */
     1.8 -    idt_tables[cpu][TRAP_nmi].a           |= 2UL << 32; /* IST2 */
     1.9 -    idt_tables[cpu][TRAP_machine_check].a |= 3UL << 32; /* IST3 */
    1.10 +    idt_tables[cpu][TRAP_double_fault].a  |= IST_DF << 32;
    1.11 +    idt_tables[cpu][TRAP_nmi].a           |= IST_NMI << 32;
    1.12 +    idt_tables[cpu][TRAP_machine_check].a |= IST_MCE << 32;
    1.13  #endif
    1.14  }
    1.15  
    1.16 @@ -832,9 +832,9 @@ static void svm_ctxt_switch_to(struct vc
    1.17       * Cannot use ISTs for NMI/#MC/#DF while we are running with the guest TR.
    1.18       * But this doesn't matter: the IST is only req'd to handle SYSCALL/SYSRET.
    1.19       */
    1.20 -    idt_tables[cpu][TRAP_double_fault].a  &= ~(3UL << 32);
    1.21 -    idt_tables[cpu][TRAP_nmi].a           &= ~(3UL << 32);
    1.22 -    idt_tables[cpu][TRAP_machine_check].a &= ~(3UL << 32);
    1.23 +    idt_tables[cpu][TRAP_double_fault].a  &= ~(7UL << 32);
    1.24 +    idt_tables[cpu][TRAP_nmi].a           &= ~(7UL << 32);
    1.25 +    idt_tables[cpu][TRAP_machine_check].a &= ~(7UL << 32);
    1.26  #endif
    1.27  
    1.28      svm_restore_dr(v);

     2.1 --- a/xen/arch/x86/mm.c	Tue Jul 03 11:24:40 2007 +0100
     2.2 +++ b/xen/arch/x86/mm.c	Tue Jul 03 11:41:25 2007 +0100
     2.3 @@ -3655,8 +3655,9 @@ void memguard_unguard_range(void *p, uns
     2.4  
     2.5  void memguard_guard_stack(void *p)
     2.6  {
     2.7 -    BUILD_BUG_ON((DEBUG_STACK_SIZE + PAGE_SIZE) > STACK_SIZE);
     2.8 -    p = (void *)((unsigned long)p + STACK_SIZE - DEBUG_STACK_SIZE - PAGE_SIZE);
     2.9 +    BUILD_BUG_ON((PRIMARY_STACK_SIZE + PAGE_SIZE) > STACK_SIZE);
    2.10 +    p = (void *)((unsigned long)p + STACK_SIZE -
    2.11 +                 PRIMARY_STACK_SIZE - PAGE_SIZE);
    2.12      memguard_guard_range(p, PAGE_SIZE);
    2.13  }
    2.14  

     3.1 --- a/xen/arch/x86/setup.c	Tue Jul 03 11:24:40 2007 +0100
     3.2 +++ b/xen/arch/x86/setup.c	Tue Jul 03 11:41:25 2007 +0100
     3.3 @@ -109,7 +109,7 @@ extern void early_cpu_init(void);
     3.4  
     3.5  struct tss_struct init_tss[NR_CPUS];
     3.6  
     3.7 -char __attribute__ ((__section__(".bss.page_aligned"))) cpu0_stack[STACK_SIZE];
     3.8 +char __attribute__ ((__section__(".bss.stack_aligned"))) cpu0_stack[STACK_SIZE];
     3.9  
    3.10  struct cpuinfo_x86 boot_cpu_data = { 0, 0, 0, 0, -1, 1, 0, 0, -1 };
    3.11  

     4.1 --- a/xen/arch/x86/traps.c	Tue Jul 03 11:24:40 2007 +0100
     4.2 +++ b/xen/arch/x86/traps.c	Tue Jul 03 11:41:25 2007 +0100
     4.3 @@ -280,7 +280,7 @@ void show_stack_overflow(unsigned int cp
     4.4      unsigned long *stack, addr;
     4.5  
     4.6      esp_bottom = (esp | (STACK_SIZE - 1)) + 1;
     4.7 -    esp_top    = esp_bottom - DEBUG_STACK_SIZE;
     4.8 +    esp_top    = esp_bottom - PRIMARY_STACK_SIZE;
     4.9  
    4.10      printk("Valid stack range: %p-%p, sp=%p, tss.esp0=%p\n",
    4.11             (void *)esp_top, (void *)esp_bottom, (void *)esp,

     5.1 --- a/xen/arch/x86/x86_32/xen.lds.S	Tue Jul 03 11:24:40 2007 +0100
     5.2 +++ b/xen/arch/x86/x86_32/xen.lds.S	Tue Jul 03 11:41:25 2007 +0100
     5.3 @@ -70,12 +70,14 @@ SECTIONS
     5.4    .data.percpu : { *(.data.percpu) } :text
     5.5    __per_cpu_data_end = .;
     5.6    . = __per_cpu_start + (NR_CPUS << PERCPU_SHIFT);
     5.7 -  . = ALIGN(STACK_SIZE);
     5.8 +  . = ALIGN(PAGE_SIZE);
     5.9    __per_cpu_end = .;
    5.10  
    5.11    __bss_start = .;		/* BSS */
    5.12    .bss : {
    5.13 +	. = ALIGN(STACK_SIZE);
    5.14  	*(.bss.stack_aligned)
    5.15 +	. = ALIGN(PAGE_SIZE);
    5.16  	*(.bss.page_aligned)
    5.17  	*(.bss)
    5.18  	} :text

     6.1 --- a/xen/arch/x86/x86_64/traps.c	Tue Jul 03 11:24:40 2007 +0100
     6.2 +++ b/xen/arch/x86/x86_64/traps.c	Tue Jul 03 11:41:25 2007 +0100
     6.3 @@ -292,11 +292,11 @@ void __init percpu_traps_init(void)
     6.4  
     6.5      if ( cpu == 0 )
     6.6      {
     6.7 -        /* Specify dedicated interrupt stacks for NMIs and double faults. */
     6.8 +        /* Specify dedicated interrupt stacks for NMI, #DF, and #MC. */
     6.9          set_intr_gate(TRAP_double_fault, &double_fault);
    6.10 -        idt_table[TRAP_double_fault].a  |= 1UL << 32; /* IST1 */
    6.11 -        idt_table[TRAP_nmi].a           |= 2UL << 32; /* IST2 */
    6.12 -        idt_table[TRAP_machine_check].a |= 3UL << 32; /* IST3 */
    6.13 +        idt_table[TRAP_double_fault].a  |= IST_DF << 32;
    6.14 +        idt_table[TRAP_nmi].a           |= IST_NMI << 32;
    6.15 +        idt_table[TRAP_machine_check].a |= IST_MCE << 32;
    6.16  
    6.17          /*
    6.18           * The 32-on-64 hypercall entry vector is only accessible from ring 1.
    6.19 @@ -311,17 +311,20 @@ void __init percpu_traps_init(void)
    6.20      stack_bottom = (char *)get_stack_bottom();
    6.21      stack        = (char *)((unsigned long)stack_bottom & ~(STACK_SIZE - 1));
    6.22  
    6.23 -    /* Machine Check handler has its own per-CPU 1kB stack. */
    6.24 -    init_tss[cpu].ist[2] = (unsigned long)&stack[1024];
    6.25 +    /* IST_MAX IST pages + 1 syscall page + 1 guard page + primary stack. */
    6.26 +    BUILD_BUG_ON((IST_MAX + 2) * PAGE_SIZE + PRIMARY_STACK_SIZE > STACK_SIZE);
    6.27 +
    6.28 +    /* Machine Check handler has its own per-CPU 4kB stack. */
    6.29 +    init_tss[cpu].ist[IST_MCE] = (unsigned long)&stack[IST_MCE * PAGE_SIZE];
    6.30  
    6.31 -    /* Double-fault handler has its own per-CPU 1kB stack. */
    6.32 -    init_tss[cpu].ist[0] = (unsigned long)&stack[2048];
    6.33 +    /* Double-fault handler has its own per-CPU 4kB stack. */
    6.34 +    init_tss[cpu].ist[IST_DF] = (unsigned long)&stack[IST_DF * PAGE_SIZE];
    6.35  
    6.36 -    /* NMI handler has its own per-CPU 1kB stack. */
    6.37 -    init_tss[cpu].ist[1] = (unsigned long)&stack[3072];
    6.38 +    /* NMI handler has its own per-CPU 4kB stack. */
    6.39 +    init_tss[cpu].ist[IST_NMI] = (unsigned long)&stack[IST_NMI * PAGE_SIZE];
    6.40  
    6.41      /* Trampoline for SYSCALL entry from long mode. */
    6.42 -    stack = &stack[3072]; /* Skip the NMI and DF stacks. */
    6.43 +    stack = &stack[IST_MAX * PAGE_SIZE]; /* Skip the IST stacks. */
    6.44      wrmsr(MSR_LSTAR, (unsigned long)stack, ((unsigned long)stack>>32));
    6.45      stack += write_stack_trampoline(stack, stack_bottom, FLAT_KERNEL_CS64);
    6.46  

     7.1 --- a/xen/arch/x86/x86_64/xen.lds.S	Tue Jul 03 11:24:40 2007 +0100
     7.2 +++ b/xen/arch/x86/x86_64/xen.lds.S	Tue Jul 03 11:41:25 2007 +0100
     7.3 @@ -68,12 +68,14 @@ SECTIONS
     7.4    .data.percpu : { *(.data.percpu) } :text
     7.5    __per_cpu_data_end = .;
     7.6    . = __per_cpu_start + (NR_CPUS << PERCPU_SHIFT);
     7.7 -  . = ALIGN(STACK_SIZE);
     7.8 +  . = ALIGN(PAGE_SIZE);
     7.9    __per_cpu_end = .;
    7.10  
    7.11    __bss_start = .;		/* BSS */
    7.12    .bss : {
    7.13 +	. = ALIGN(STACK_SIZE);
    7.14  	*(.bss.stack_aligned)
    7.15 +	. = ALIGN(PAGE_SIZE);
    7.16  	*(.bss.page_aligned)
    7.17  	*(.bss)
    7.18  	} :text

     8.1 --- a/xen/include/asm-x86/config.h	Tue Jul 03 11:24:40 2007 +0100
     8.2 +++ b/xen/include/asm-x86/config.h	Tue Jul 03 11:41:25 2007 +0100
     8.3 @@ -77,11 +77,15 @@
     8.4  #define MEMORY_GUARD
     8.5  #endif
     8.6  
     8.7 +#ifdef __i386__
     8.8  #define STACK_ORDER 2
     8.9 +#else
    8.10 +#define STACK_ORDER 3
    8.11 +#endif
    8.12  #define STACK_SIZE  (PAGE_SIZE << STACK_ORDER)
    8.13  
    8.14 -/* Debug stack is restricted to 8kB by guard pages. */
    8.15 -#define DEBUG_STACK_SIZE 8192
    8.16 +/* Primary stack is restricted to 8kB by guard pages. */
    8.17 +#define PRIMARY_STACK_SIZE 8192
    8.18  
    8.19  #define CONFIG_DMA_BITSIZE 32
    8.20  

     9.1 --- a/xen/include/asm-x86/processor.h	Tue Jul 03 11:24:40 2007 +0100
     9.2 +++ b/xen/include/asm-x86/processor.h	Tue Jul 03 11:41:25 2007 +0100
     9.3 @@ -448,6 +448,13 @@ struct tss_struct {
     9.4      u8 __cacheline_filler[24];
     9.5  } __cacheline_aligned __attribute__((packed));
     9.6  
     9.7 +#ifdef __x86_64__
     9.8 +# define IST_DF  1UL
     9.9 +# define IST_NMI 2UL
    9.10 +# define IST_MCE 3UL
    9.11 +# define IST_MAX 3UL
    9.12 +#endif
    9.13 +
    9.14  #define IDT_ENTRIES 256
    9.15  extern idt_entry_t idt_table[];
    9.16  extern idt_entry_t *idt_tables[];