direct-io.hg

changeset 5979:04f35d2b143d

This patch adds necessary support for vcontext merge between
para and vti side. Per Dan's good suggestion, all the changes
are refined into ia64 specific. Accompanied with xeno patches
and a bit libxc change, xen0 + xenU can still work again.

Signed-off-by Eddie Dong <eddie.dong@intel.com>
Signed-off-by Kevin Tian <kevin.tian@intel.com>
Signed-off-by Fred Yang <fred.yang@intel.com>
author fred@localhost.localdomain
date Thu Jul 28 07:16:12 2005 -0800 (2005-07-28)
parents 8fc64b82dd35
children 34460b45204a
files xen/arch/ia64/asm-offsets.c xen/arch/ia64/asm-xsi-offsets.c xen/arch/ia64/domain.c xen/arch/ia64/process.c xen/arch/ia64/regionreg.c xen/arch/ia64/vcpu.c xen/arch/ia64/xenasm.S xen/include/asm-ia64/event.h xen/include/asm-ia64/vcpu.h xen/include/asm-ia64/vmx_vpd.h xen/include/asm-ia64/xensystem.h xen/include/public/arch-ia64.h
line diff
     1.1 --- a/xen/arch/ia64/asm-offsets.c	Thu Jul 28 01:48:15 2005 -0800
     1.2 +++ b/xen/arch/ia64/asm-offsets.c	Thu Jul 28 07:16:12 2005 -0800
     1.3 @@ -42,29 +42,34 @@ void foo(void)
     1.4  
     1.5  	BLANK();
     1.6  
     1.7 -	DEFINE(XSI_PSR_IC_OFS, offsetof(vcpu_info_t, arch.interrupt_collection_enabled));
     1.8 -	DEFINE(XSI_PSR_IC, (SHAREDINFO_ADDR+offsetof(vcpu_info_t, arch.interrupt_collection_enabled)));
     1.9 -	DEFINE(XSI_PSR_I_OFS, offsetof(vcpu_info_t, arch.interrupt_delivery_enabled));
    1.10 -	DEFINE(XSI_IIP_OFS, offsetof(vcpu_info_t, arch.iip));
    1.11 -	DEFINE(XSI_IFA_OFS, offsetof(vcpu_info_t, arch.ifa));
    1.12 -	DEFINE(XSI_ITIR_OFS, offsetof(vcpu_info_t, arch.itir));
    1.13 -	DEFINE(XSI_IPSR, (SHAREDINFO_ADDR+offsetof(vcpu_info_t, arch.ipsr)));
    1.14 -	DEFINE(XSI_IPSR_OFS, offsetof(vcpu_info_t, arch.ipsr));
    1.15 -	DEFINE(XSI_IFS_OFS, offsetof(vcpu_info_t, arch.ifs));
    1.16 -	DEFINE(XSI_ISR_OFS, offsetof(vcpu_info_t, arch.isr));
    1.17 -	DEFINE(XSI_IIM_OFS, offsetof(vcpu_info_t, arch.iim));
    1.18 -	DEFINE(XSI_BANKNUM_OFS, offsetof(vcpu_info_t, arch.banknum));
    1.19 -	DEFINE(XSI_BANK0_OFS, offsetof(vcpu_info_t, arch.bank0_regs[0]));
    1.20 -	DEFINE(XSI_BANK1_OFS, offsetof(vcpu_info_t, arch.bank1_regs[0]));
    1.21 -	DEFINE(XSI_RR0_OFS, offsetof(vcpu_info_t, arch.rrs[0]));
    1.22 -	DEFINE(XSI_METAPHYS_OFS, offsetof(vcpu_info_t, arch.metaphysical_mode));
    1.23 -	DEFINE(XSI_PRECOVER_IFS_OFS, offsetof(vcpu_info_t, arch.precover_ifs));
    1.24 -	DEFINE(XSI_INCOMPL_REG_OFS, offsetof(vcpu_info_t, arch.incomplete_regframe));
    1.25 -	DEFINE(XSI_PEND_OFS, offsetof(vcpu_info_t, arch.pending_interruption));
    1.26 -	DEFINE(XSI_RR0_OFS, offsetof(vcpu_info_t, arch.rrs[0]));
    1.27 -	DEFINE(XSI_TPR_OFS, offsetof(vcpu_info_t, arch.tpr));
    1.28 -	DEFINE(XSI_PTA_OFS, offsetof (vcpu_info_t, arch.pta));
    1.29 -	DEFINE(XSI_ITV_OFS, offsetof(vcpu_info_t, arch.itv));
    1.30 +	DEFINE(XSI_PSR_IC_OFS, offsetof(mapped_regs_t, interrupt_collection_enabled));
    1.31 +	DEFINE(XSI_PSR_IC, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, interrupt_collection_enabled)));
    1.32 +	DEFINE(XSI_PSR_I_OFS, offsetof(mapped_regs_t, interrupt_delivery_enabled));
    1.33 +	DEFINE(XSI_IIP_OFS, offsetof(mapped_regs_t, iip));
    1.34 +	DEFINE(XSI_IIP, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, iip)));
    1.35 +	DEFINE(XSI_IFA_OFS, offsetof(mapped_regs_t, ifa));
    1.36 +	DEFINE(XSI_IFA, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, ifa)));
    1.37 +	DEFINE(XSI_ITIR_OFS, offsetof(mapped_regs_t, itir));
    1.38 +	DEFINE(XSI_ITIR, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, itir)));
    1.39 +
    1.40 +	DEFINE(XSI_IPSR, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, ipsr)));
    1.41 +	DEFINE(XSI_IPSR_OFS, offsetof(mapped_regs_t, ipsr));
    1.42 +	DEFINE(XSI_IFS_OFS, offsetof(mapped_regs_t, ifs));
    1.43 +	DEFINE(XSI_IFS, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, ifs)));
    1.44 +	DEFINE(XSI_ISR_OFS, offsetof(mapped_regs_t, isr));
    1.45 +	DEFINE(XSI_IIM_OFS, offsetof(mapped_regs_t, iim));
    1.46 +	DEFINE(XSI_BANKNUM_OFS, offsetof(mapped_regs_t, banknum));
    1.47 +	DEFINE(XSI_BANK0_OFS, offsetof(mapped_regs_t, bank0_regs[0]));
    1.48 +	DEFINE(XSI_BANK1_OFS, offsetof(mapped_regs_t, bank1_regs[0]));
    1.49 +	DEFINE(XSI_RR0_OFS, offsetof(mapped_regs_t, rrs[0]));
    1.50 +	DEFINE(XSI_METAPHYS_OFS, offsetof(mapped_regs_t, metaphysical_mode));
    1.51 +	DEFINE(XSI_PRECOVER_IFS_OFS, offsetof(mapped_regs_t, precover_ifs));
    1.52 +	DEFINE(XSI_INCOMPL_REG_OFS, offsetof(mapped_regs_t, incomplete_regframe));
    1.53 +	DEFINE(XSI_PEND_OFS, offsetof(mapped_regs_t, pending_interruption));
    1.54 +	DEFINE(XSI_RR0_OFS, offsetof(mapped_regs_t, rrs[0]));
    1.55 +	DEFINE(XSI_TPR_OFS, offsetof(mapped_regs_t, tpr));
    1.56 +	DEFINE(XSI_PTA_OFS, offsetof(mapped_regs_t, pta));
    1.57 +	DEFINE(XSI_ITV_OFS, offsetof(mapped_regs_t, itv));
    1.58  	//DEFINE(IA64_TASK_BLOCKED_OFFSET,offsetof (struct task_struct, blocked));
    1.59  	//DEFINE(IA64_TASK_CLEAR_CHILD_TID_OFFSET,offsetof (struct task_struct, clear_child_tid));
    1.60  	//DEFINE(IA64_TASK_GROUP_LEADER_OFFSET, offsetof (struct task_struct, group_leader));
     2.1 --- a/xen/arch/ia64/asm-xsi-offsets.c	Thu Jul 28 01:48:15 2005 -0800
     2.2 +++ b/xen/arch/ia64/asm-xsi-offsets.c	Thu Jul 28 07:16:12 2005 -0800
     2.3 @@ -47,68 +47,64 @@
     2.4  #define OFFSET(_sym, _str, _mem) \
     2.5      DEFINE(_sym, offsetof(_str, _mem));
     2.6  
     2.7 -#ifndef CONFIG_VTI
     2.8 -#define SHARED_ARCHINFO_ADDR SHAREDINFO_ADDR
     2.9 -#endif
    2.10 -
    2.11  void foo(void)
    2.12  {
    2.13  
    2.14  	DEFINE(XSI_BASE, SHARED_ARCHINFO_ADDR);
    2.15  
    2.16 -	DEFINE(XSI_PSR_I_OFS, offsetof(arch_vcpu_info_t, interrupt_delivery_enabled));
    2.17 -	DEFINE(XSI_PSR_I, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, interrupt_delivery_enabled)));
    2.18 -	DEFINE(XSI_IPSR, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, ipsr)));
    2.19 -	DEFINE(XSI_IPSR_OFS, offsetof(arch_vcpu_info_t, ipsr));
    2.20 -	DEFINE(XSI_IIP_OFS, offsetof(arch_vcpu_info_t, iip));
    2.21 -	DEFINE(XSI_IIP, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, iip)));
    2.22 -	DEFINE(XSI_IFS_OFS, offsetof(arch_vcpu_info_t, ifs));
    2.23 -	DEFINE(XSI_IFS, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, ifs)));
    2.24 -	DEFINE(XSI_PRECOVER_IFS_OFS, offsetof(arch_vcpu_info_t, precover_ifs));
    2.25 -	DEFINE(XSI_PRECOVER_IFS, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, precover_ifs)));
    2.26 -	DEFINE(XSI_ISR_OFS, offsetof(arch_vcpu_info_t, isr));
    2.27 -	DEFINE(XSI_ISR, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, isr)));
    2.28 -	DEFINE(XSI_IFA_OFS, offsetof(arch_vcpu_info_t, ifa));
    2.29 -	DEFINE(XSI_IFA, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, ifa)));
    2.30 -	DEFINE(XSI_IIPA_OFS, offsetof(arch_vcpu_info_t, iipa));
    2.31 -	DEFINE(XSI_IIPA, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, iipa)));
    2.32 -	DEFINE(XSI_IIM_OFS, offsetof(arch_vcpu_info_t, iim));
    2.33 -	DEFINE(XSI_IIM, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, iim)));
    2.34 -	DEFINE(XSI_TPR_OFS, offsetof(arch_vcpu_info_t, tpr));
    2.35 -	DEFINE(XSI_TPR, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, tpr)));
    2.36 -	DEFINE(XSI_IHA_OFS, offsetof(arch_vcpu_info_t, iha));
    2.37 -	DEFINE(XSI_IHA, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, iha)));
    2.38 -	DEFINE(XSI_ITIR_OFS, offsetof(arch_vcpu_info_t, itir));
    2.39 -	DEFINE(XSI_ITIR, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, itir)));
    2.40 -	DEFINE(XSI_ITV_OFS, offsetof(arch_vcpu_info_t, itv));
    2.41 -	DEFINE(XSI_ITV, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, itv)));
    2.42 -	DEFINE(XSI_PTA_OFS, offsetof(arch_vcpu_info_t, pta));
    2.43 -	DEFINE(XSI_PTA, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, pta)));
    2.44 -	DEFINE(XSI_PSR_IC_OFS, offsetof(arch_vcpu_info_t, interrupt_collection_enabled));
    2.45 -	DEFINE(XSI_PSR_IC, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, interrupt_collection_enabled)));
    2.46 -	DEFINE(XSI_PEND_OFS, offsetof(arch_vcpu_info_t, pending_interruption));
    2.47 -	DEFINE(XSI_PEND, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, pending_interruption)));
    2.48 -	DEFINE(XSI_INCOMPL_REGFR_OFS, offsetof(arch_vcpu_info_t, incomplete_regframe));
    2.49 -	DEFINE(XSI_INCOMPL_REGFR, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, incomplete_regframe)));
    2.50 -	DEFINE(XSI_DELIV_MASK0_OFS, offsetof(arch_vcpu_info_t, delivery_mask[0]));
    2.51 -	DEFINE(XSI_DELIV_MASK0, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, delivery_mask[0])));
    2.52 -	DEFINE(XSI_METAPHYS_OFS, offsetof(arch_vcpu_info_t, metaphysical_mode));
    2.53 -	DEFINE(XSI_METAPHYS, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, metaphysical_mode)));
    2.54 +	DEFINE(XSI_PSR_I_OFS, offsetof(mapped_regs_t, interrupt_delivery_enabled));
    2.55 +	DEFINE(XSI_PSR_I, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, interrupt_delivery_enabled)));
    2.56 +	DEFINE(XSI_IPSR, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, ipsr)));
    2.57 +	DEFINE(XSI_IPSR_OFS, offsetof(mapped_regs_t, ipsr));
    2.58 +	DEFINE(XSI_IIP_OFS, offsetof(mapped_regs_t, iip));
    2.59 +	DEFINE(XSI_IIP, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, iip)));
    2.60 +	DEFINE(XSI_IFS_OFS, offsetof(mapped_regs_t, ifs));
    2.61 +	DEFINE(XSI_IFS, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, ifs)));
    2.62 +	DEFINE(XSI_PRECOVER_IFS_OFS, offsetof(mapped_regs_t, precover_ifs));
    2.63 +	DEFINE(XSI_PRECOVER_IFS, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, precover_ifs)));
    2.64 +	DEFINE(XSI_ISR_OFS, offsetof(mapped_regs_t, isr));
    2.65 +	DEFINE(XSI_ISR, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, isr)));
    2.66 +	DEFINE(XSI_IFA_OFS, offsetof(mapped_regs_t, ifa));
    2.67 +	DEFINE(XSI_IFA, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, ifa)));
    2.68 +	DEFINE(XSI_IIPA_OFS, offsetof(mapped_regs_t, iipa));
    2.69 +	DEFINE(XSI_IIPA, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, iipa)));
    2.70 +	DEFINE(XSI_IIM_OFS, offsetof(mapped_regs_t, iim));
    2.71 +	DEFINE(XSI_IIM, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, iim)));
    2.72 +	DEFINE(XSI_TPR_OFS, offsetof(mapped_regs_t, tpr));
    2.73 +	DEFINE(XSI_TPR, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, tpr)));
    2.74 +	DEFINE(XSI_IHA_OFS, offsetof(mapped_regs_t, iha));
    2.75 +	DEFINE(XSI_IHA, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, iha)));
    2.76 +	DEFINE(XSI_ITIR_OFS, offsetof(mapped_regs_t, itir));
    2.77 +	DEFINE(XSI_ITIR, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, itir)));
    2.78 +	DEFINE(XSI_ITV_OFS, offsetof(mapped_regs_t, itv));
    2.79 +	DEFINE(XSI_ITV, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, itv)));
    2.80 +	DEFINE(XSI_PTA_OFS, offsetof(mapped_regs_t, pta));
    2.81 +	DEFINE(XSI_PTA, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, pta)));
    2.82 +	DEFINE(XSI_PSR_IC_OFS, offsetof(mapped_regs_t, interrupt_collection_enabled));
    2.83 +	DEFINE(XSI_PSR_IC, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, interrupt_collection_enabled)));
    2.84 +	DEFINE(XSI_PEND_OFS, offsetof(mapped_regs_t, pending_interruption));
    2.85 +	DEFINE(XSI_PEND, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, pending_interruption)));
    2.86 +	DEFINE(XSI_INCOMPL_REGFR_OFS, offsetof(mapped_regs_t, incomplete_regframe));
    2.87 +	DEFINE(XSI_INCOMPL_REGFR, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, incomplete_regframe)));
    2.88 +	DEFINE(XSI_DELIV_MASK0_OFS, offsetof(mapped_regs_t, delivery_mask[0]));
    2.89 +	DEFINE(XSI_DELIV_MASK0, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, delivery_mask[0])));
    2.90 +	DEFINE(XSI_METAPHYS_OFS, offsetof(mapped_regs_t, metaphysical_mode));
    2.91 +	DEFINE(XSI_METAPHYS, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, metaphysical_mode)));
    2.92  
    2.93 -	DEFINE(XSI_BANKNUM_OFS, offsetof(arch_vcpu_info_t, banknum));
    2.94 -	DEFINE(XSI_BANKNUM, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, banknum)));
    2.95 +	DEFINE(XSI_BANKNUM_OFS, offsetof(mapped_regs_t, banknum));
    2.96 +	DEFINE(XSI_BANKNUM, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, banknum)));
    2.97  
    2.98 -	DEFINE(XSI_BANK0_R16_OFS, offsetof(arch_vcpu_info_t, bank0_regs[0]));
    2.99 -	DEFINE(XSI_BANK0_R16, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, bank0_regs[0])));
   2.100 -	DEFINE(XSI_BANK1_R16_OFS, offsetof(arch_vcpu_info_t, bank1_regs[0]));
   2.101 -	DEFINE(XSI_BANK1_R16, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, bank1_regs[0])));
   2.102 -	DEFINE(XSI_RR0_OFS, offsetof(arch_vcpu_info_t, rrs[0]));
   2.103 -	DEFINE(XSI_RR0, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, rrs[0])));
   2.104 -	DEFINE(XSI_KR0_OFS, offsetof(arch_vcpu_info_t, krs[0]));
   2.105 -	DEFINE(XSI_KR0, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, krs[0])));
   2.106 -	DEFINE(XSI_PKR0_OFS, offsetof(arch_vcpu_info_t, pkrs[0]));
   2.107 -	DEFINE(XSI_PKR0, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, pkrs[0])));
   2.108 -	DEFINE(XSI_TMP0_OFS, offsetof(arch_vcpu_info_t, tmp[0]));
   2.109 -	DEFINE(XSI_TMP0, (SHARED_ARCHINFO_ADDR+offsetof(arch_vcpu_info_t, tmp[0])));
   2.110 +	DEFINE(XSI_BANK0_R16_OFS, offsetof(mapped_regs_t, bank0_regs[0]));
   2.111 +	DEFINE(XSI_BANK0_R16, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, bank0_regs[0])));
   2.112 +	DEFINE(XSI_BANK1_R16_OFS, offsetof(mapped_regs_t, bank1_regs[0]));
   2.113 +	DEFINE(XSI_BANK1_R16, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, bank1_regs[0])));
   2.114 +	DEFINE(XSI_RR0_OFS, offsetof(mapped_regs_t, rrs[0]));
   2.115 +	DEFINE(XSI_RR0, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, rrs[0])));
   2.116 +	DEFINE(XSI_KR0_OFS, offsetof(mapped_regs_t, krs[0]));
   2.117 +	DEFINE(XSI_KR0, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, krs[0])));
   2.118 +	DEFINE(XSI_PKR0_OFS, offsetof(mapped_regs_t, pkrs[0]));
   2.119 +	DEFINE(XSI_PKR0, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, pkrs[0])));
   2.120 +	DEFINE(XSI_TMP0_OFS, offsetof(mapped_regs_t, tmp[0]));
   2.121 +	DEFINE(XSI_TMP0, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, tmp[0])));
   2.122  	
   2.123  }
     3.1 --- a/xen/arch/ia64/domain.c	Thu Jul 28 01:48:15 2005 -0800
     3.2 +++ b/xen/arch/ia64/domain.c	Thu Jul 28 07:16:12 2005 -0800
     3.3 @@ -212,6 +212,10 @@ void arch_do_createdomain(struct vcpu *v
     3.4  	 */
     3.5  
     3.6  	memset(d->shared_info, 0, PAGE_SIZE);
     3.7 +	d->shared_info->vcpu_data[v->vcpu_id].arch.privregs = 
     3.8 +			alloc_xenheap_pages(get_order(sizeof(mapped_regs_t)));
     3.9 +	printf("arch_vcpu_info=%p\n", d->shared_info->vcpu_data[0].arch.privregs);
    3.10 +	memset(d->shared_info->vcpu_data[v->vcpu_id].arch.privregs, 0, PAGE_SIZE);
    3.11  	v->vcpu_info = &d->shared_info->vcpu_data[v->vcpu_id];
    3.12  	/* Mask all events, and specific port will be unmasked
    3.13  	 * when customer subscribes to it.
    3.14 @@ -232,8 +236,8 @@ void arch_do_createdomain(struct vcpu *v
    3.15  	/* FIXME: This is identity mapped address for xenheap. 
    3.16  	 * Do we need it at all?
    3.17  	 */
    3.18 -	d->xen_vastart = 0xf000000000000000;
    3.19 -	d->xen_vaend = 0xf300000000000000;
    3.20 +	d->xen_vastart = XEN_START_ADDR;
    3.21 +	d->xen_vaend = XEN_END_ADDR;
    3.22  	d->arch.breakimm = 0x1000;
    3.23  }
    3.24  #else // CONFIG_VTI
    3.25 @@ -252,12 +256,16 @@ void arch_do_createdomain(struct vcpu *v
    3.26     		while (1);
    3.27  	}
    3.28  	memset(d->shared_info, 0, PAGE_SIZE);
    3.29 +	d->shared_info->vcpu_data[0].arch.privregs = 
    3.30 +			alloc_xenheap_pages(get_order(sizeof(mapped_regs_t)));
    3.31 +	printf("arch_vcpu_info=%p\n", d->shared_info->vcpu_data[0].arch.privregs);
    3.32 +	memset(d->shared_info->vcpu_data[0].arch.privregs, 0, PAGE_SIZE);
    3.33  	v->vcpu_info = &(d->shared_info->vcpu_data[0]);
    3.34  
    3.35 -	d->max_pages = (128*1024*1024)/PAGE_SIZE; // 128MB default // FIXME
    3.36 +	d->max_pages = (128UL*1024*1024)/PAGE_SIZE; // 128MB default // FIXME
    3.37  	if ((d->arch.metaphysical_rr0 = allocate_metaphysical_rr0()) == -1UL)
    3.38  		BUG();
    3.39 -	v->vcpu_info->arch.metaphysical_mode = 1;
    3.40 +	VCPU(v, metaphysical_mode) = 1;
    3.41  	v->arch.metaphysical_rr0 = d->arch.metaphysical_rr0;
    3.42  	v->arch.metaphysical_saved_rr0 = d->arch.metaphysical_rr0;
    3.43  #define DOMAIN_RID_BITS_DEFAULT 18
    3.44 @@ -266,9 +274,9 @@ void arch_do_createdomain(struct vcpu *v
    3.45  	v->arch.starting_rid = d->arch.starting_rid;
    3.46  	v->arch.ending_rid = d->arch.ending_rid;
    3.47  	// the following will eventually need to be negotiated dynamically
    3.48 -	d->xen_vastart = 0xf000000000000000;
    3.49 -	d->xen_vaend = 0xf300000000000000;
    3.50 -	d->shared_info_va = 0xf100000000000000;
    3.51 +	d->xen_vastart = XEN_START_ADDR;
    3.52 +	d->xen_vaend = XEN_END_ADDR;
    3.53 +	d->shared_info_va = SHAREDINFO_ADDR;
    3.54  	d->arch.breakimm = 0x1000;
    3.55  	v->arch.breakimm = d->arch.breakimm;
    3.56  
    3.57 @@ -292,7 +300,15 @@ void arch_getdomaininfo_ctxt(struct vcpu
    3.58  
    3.59  	printf("arch_getdomaininfo_ctxt\n");
    3.60  	c->regs = *regs;
    3.61 -	c->vcpu = v->vcpu_info->arch;
    3.62 +	c->vcpu.evtchn_vector = v->vcpu_info->arch.evtchn_vector;
    3.63 +#if 0
    3.64 +	if (c->vcpu.privregs && copy_to_user(c->vcpu.privregs,
    3.65 +			v->vcpu_info->arch.privregs, sizeof(mapped_regs_t))) {
    3.66 +		printk("Bad ctxt address: 0x%lx\n", c->vcpu.privregs);
    3.67 +		return -EFAULT;
    3.68 +	}
    3.69 +#endif
    3.70 +
    3.71  	c->shared = v->domain->shared_info->arch;
    3.72  }
    3.73  
    3.74 @@ -307,7 +323,13 @@ int arch_set_info_guest(struct vcpu *v, 
    3.75  	regs->cr_ipsr |= 2UL << IA64_PSR_CPL0_BIT;
    3.76  	regs->ar_rsc |= (2 << 2); /* force PL2/3 */
    3.77  
    3.78 -	v->vcpu_info->arch = c->vcpu;
    3.79 + 	v->vcpu_info->arch.evtchn_vector = c->vcpu.evtchn_vector;
    3.80 +	if ( c->vcpu.privregs && copy_from_user(v->vcpu_info->arch.privregs,
    3.81 +			   c->vcpu.privregs, sizeof(mapped_regs_t))) {
    3.82 +	    printk("Bad ctxt address in arch_set_info_guest: 0x%lx\n", c->vcpu.privregs);
    3.83 +	    return -EFAULT;
    3.84 +	}
    3.85 +
    3.86  	init_all_rr(v);
    3.87  
    3.88  	// this should be in userspace
    3.89 @@ -381,8 +403,8 @@ int arch_set_info_guest(
    3.90      new_thread(v, c->guest_iip, 0, 0);
    3.91  
    3.92  
    3.93 -    d->xen_vastart = 0xf000000000000000;
    3.94 -    d->xen_vaend = 0xf300000000000000;
    3.95 +    d->xen_vastart = XEN_START_ADDR;
    3.96 +    d->xen_vaend = XEN_END_ADDR;
    3.97      d->arch.breakimm = 0x1000 + d->domain_id;
    3.98      v->arch._thread.on_ustack = 0;
    3.99  
   3.100 @@ -395,7 +417,13 @@ int arch_set_info_guest(
   3.101  
   3.102  void arch_do_boot_vcpu(struct vcpu *v)
   3.103  {
   3.104 +	struct domain *d = v->domain;
   3.105  	printf("arch_do_boot_vcpu: not implemented\n");
   3.106 +
   3.107 +	d->shared_info->vcpu_data[v->vcpu_id].arch.privregs = 
   3.108 +			alloc_xenheap_pages(get_order(sizeof(mapped_regs_t)));
   3.109 +	printf("arch_vcpu_info=%p\n", d->shared_info->vcpu_data[v->vcpu_id].arch.privregs);
   3.110 +	memset(d->shared_info->vcpu_data[v->vcpu_id].arch.privregs, 0, PAGE_SIZE);
   3.111  	return;
   3.112  }
   3.113  
     4.1 --- a/xen/arch/ia64/process.c	Thu Jul 28 01:48:15 2005 -0800
     4.2 +++ b/xen/arch/ia64/process.c	Thu Jul 28 07:16:12 2005 -0800
     4.3 @@ -226,7 +226,7 @@ panic_domain(regs,"psr.ic off, deliverin
     4.4  #ifdef CONFIG_SMP
     4.5  #error "sharedinfo doesn't handle smp yet"
     4.6  #endif
     4.7 -	regs->r31 = &((shared_info_t *)SHAREDINFO_ADDR)->vcpu_data[0].arch;
     4.8 +	regs->r31 = &(((mapped_regs_t *)SHARED_ARCHINFO_ADDR)->ipsr);
     4.9  
    4.10  	PSCB(v,interrupt_delivery_enabled) = 0;
    4.11  	PSCB(v,interrupt_collection_enabled) = 0;
     5.1 --- a/xen/arch/ia64/regionreg.c	Thu Jul 28 01:48:15 2005 -0800
     5.2 +++ b/xen/arch/ia64/regionreg.c	Thu Jul 28 07:16:12 2005 -0800
     5.3 @@ -15,6 +15,7 @@
     5.4  #include <asm/regionreg.h>
     5.5  #include <asm/vhpt.h>
     5.6  #include <asm/vcpu.h>
     5.7 +extern void ia64_new_rr7(unsigned long rid,void *shared_info, void *shared_arch_info);
     5.8  
     5.9  
    5.10  #define	IA64_MIN_IMPL_RID_BITS	(IA64_MIN_IMPL_RID_MSB+1)
    5.11 @@ -274,7 +275,8 @@ int set_one_rr(unsigned long rr, unsigne
    5.12  		newrrv.rid = newrid;
    5.13  		newrrv.ve = VHPT_ENABLED_REGION_7;
    5.14  		newrrv.ps = IA64_GRANULE_SHIFT;
    5.15 -		ia64_new_rr7(vmMangleRID(newrrv.rrval),v->vcpu_info);
    5.16 +		ia64_new_rr7(vmMangleRID(newrrv.rrval),v->vcpu_info,
    5.17 +				v->vcpu_info->arch.privregs);
    5.18  	}
    5.19  	else {
    5.20  		newrrv.rid = newrid;
    5.21 @@ -291,7 +293,8 @@ int set_one_rr(unsigned long rr, unsigne
    5.22  	newrrv.ve = 1;  // VHPT now enabled for region 7!!
    5.23  	newrrv.ps = PAGE_SHIFT;
    5.24  	if (rreg == 0) v->arch.metaphysical_saved_rr0 = newrrv.rrval;
    5.25 -	if (rreg == 7) ia64_new_rr7(vmMangleRID(newrrv.rrval),v->vcpu_info);
    5.26 +	if (rreg == 7) ia64_new_rr7(vmMangleRID(newrrv.rrval),v->vcpu_info,
    5.27 +				v->vcpu_info->arch.privregs);
    5.28  	else set_rr(rr,newrrv.rrval);
    5.29  #endif
    5.30  	return 1;
     6.1 --- a/xen/arch/ia64/vcpu.c	Thu Jul 28 01:48:15 2005 -0800
     6.2 +++ b/xen/arch/ia64/vcpu.c	Thu Jul 28 07:16:12 2005 -0800
     6.3 @@ -1185,12 +1185,6 @@ IA64FAULT vcpu_rfi(VCPU *vcpu)
     6.4  	//if ((ifs & regs->cr_ifs & 0x8000000000000000L) && ifs != regs->cr_ifs) {
     6.5  	//if ((ifs & 0x8000000000000000L) && ifs != regs->cr_ifs) {
     6.6  	if (ifs & regs->cr_ifs & 0x8000000000000000L) {
     6.7 -#define SI_OFS(x)	((char *)(&PSCB(vcpu,x)) - (char *)(vcpu->vcpu_info))
     6.8 -if (SI_OFS(iip)!=0x10 || SI_OFS(ipsr)!=0x08 || SI_OFS(ifs)!=0x18) {
     6.9 -printf("SI_CR_IIP/IPSR/IFS_OFFSET CHANGED, SEE dorfirfi\n");
    6.10 -printf("SI_CR_IIP=0x%x,IPSR=0x%x,IFS_OFFSET=0x%x\n",SI_OFS(iip),SI_OFS(ipsr),SI_OFS(ifs));
    6.11 -while(1);
    6.12 -}
    6.13  		// TODO: validate PSCB(vcpu,iip)
    6.14  		// TODO: PSCB(vcpu,ipsr) = psr;
    6.15  		PSCB(vcpu,ipsr) = psr.i64;
     7.1 --- a/xen/arch/ia64/xenasm.S	Thu Jul 28 01:48:15 2005 -0800
     7.2 +++ b/xen/arch/ia64/xenasm.S	Thu Jul 28 07:16:12 2005 -0800
     7.3 @@ -48,10 +48,11 @@ END(platform_is_hp_ski)
     7.4  // FIXME? Note that this turns off the DB bit (debug)
     7.5  #define PSR_BITS_TO_SET	IA64_PSR_BN
     7.6  
     7.7 +//extern void ia64_new_rr7(unsigned long rid,void *shared_info, void *shared_arch_info);
     7.8  GLOBAL_ENTRY(ia64_new_rr7)
     7.9  	// not sure this unwind statement is correct...
    7.10  	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(1)
    7.11 -	alloc loc1 = ar.pfs, 2, 7, 0, 0
    7.12 +	alloc loc1 = ar.pfs, 3, 8, 0, 0
    7.13  1:	{
    7.14  	  mov r28  = in0		// copy procedure index
    7.15  	  mov r8   = ip			// save ip to compute branch
    7.16 @@ -72,6 +73,10 @@ 1:	{
    7.17  	;;
    7.18  	tpa loc5=loc5			// grab this BEFORE changing rr7
    7.19  	;;
    7.20 +	mov loc7=in2			// arch_vcpu_info_t
    7.21 +	;;
    7.22 +	tpa loc7=loc7			// grab this BEFORE changing rr7
    7.23 +	;;
    7.24  	mov loc3 = psr			// save psr
    7.25  	adds r8  = 1f-1b,r8		// calculate return address for call
    7.26  	;;
    7.27 @@ -206,6 +211,25 @@ 1:
    7.28  	;;
    7.29  	itr.d dtr[r25]=r23		// wire in new mapping...
    7.30  	;;
    7.31 +	// Map for arch_vcpu_info_t
    7.32 +	movl r22=SHARED_ARCHINFO_ADDR
    7.33 +	;;
    7.34 +	movl r25=__pgprot(__DIRTY_BITS | _PAGE_PL_2 | _PAGE_AR_RW)
    7.35 +	;;
    7.36 +	mov r21=loc7			// saved sharedinfo physical address
    7.37 +	;;
    7.38 +	or r23=r25,r21			// construct PA | page properties
    7.39 +	mov r24=PAGE_SHIFT<<2
    7.40 +	;;
    7.41 +	ptr.d	r22,r24
    7.42 +	;;
    7.43 +	mov cr.itir=r24
    7.44 +	mov cr.ifa=r22
    7.45 +	;;
    7.46 +	mov r25=IA64_TR_ARCH_INFO
    7.47 +	;;
    7.48 +	itr.d dtr[r25]=r23		// wire in new mapping...
    7.49 +	;;
    7.50  
    7.51  	// done, switch back to virtual and return
    7.52  	mov r16=loc3			// r16= original psr
    7.53 @@ -278,12 +302,9 @@ GLOBAL_ENTRY(__get_domain_bundle)
    7.54  END(__get_domain_bundle)
    7.55  
    7.56  GLOBAL_ENTRY(dorfirfi)
    7.57 -#define SI_CR_IIP_OFFSET 0x10
    7.58 -#define SI_CR_IPSR_OFFSET 0x08
    7.59 -#define SI_CR_IFS_OFFSET 0x18
    7.60 -        movl r16 = SHAREDINFO_ADDR+SI_CR_IIP_OFFSET
    7.61 -        movl r17 = SHAREDINFO_ADDR+SI_CR_IPSR_OFFSET
    7.62 -        movl r18 = SHAREDINFO_ADDR+SI_CR_IFS_OFFSET
    7.63 +        movl r16 = XSI_IIP
    7.64 +        movl r17 = XSI_IPSR
    7.65 +        movl r18 = XSI_IFS
    7.66  	;;
    7.67  	ld8 r16 = [r16]
    7.68  	ld8 r17 = [r17]
     8.1 --- a/xen/include/asm-ia64/event.h	Thu Jul 28 01:48:15 2005 -0800
     8.2 +++ b/xen/include/asm-ia64/event.h	Thu Jul 28 07:16:12 2005 -0800
     8.3 @@ -9,11 +9,12 @@
     8.4  #ifndef __ASM_EVENT_H__
     8.5  #define __ASM_EVENT_H__
     8.6  
     8.7 +#include <public/arch-ia64.h>
     8.8  #include <asm/vcpu.h>
     8.9  
    8.10  static inline void evtchn_notify(struct vcpu *v)
    8.11  {
    8.12 -	vcpu_pend_interrupt(v, VCPU(v,evtchn_vector));
    8.13 +	vcpu_pend_interrupt(v, v->vcpu_info->arch.evtchn_vector);
    8.14  }
    8.15  
    8.16  #endif
     9.1 --- a/xen/include/asm-ia64/vcpu.h	Thu Jul 28 01:48:15 2005 -0800
     9.2 +++ b/xen/include/asm-ia64/vcpu.h	Thu Jul 28 07:16:12 2005 -0800
     9.3 @@ -15,7 +15,7 @@ typedef	struct vcpu VCPU;
     9.4  
     9.5  typedef struct pt_regs REGS;
     9.6  
     9.7 -#define VCPU(_v,_x)	_v->vcpu_info->arch._x
     9.8 +#define VCPU(_v,_x)	_v->vcpu_info->arch.privregs->_x
     9.9  
    9.10  #define PRIVOP_ADDR_COUNT
    9.11  #ifdef PRIVOP_ADDR_COUNT
    10.1 --- a/xen/include/asm-ia64/vmx_vpd.h	Thu Jul 28 01:48:15 2005 -0800
    10.2 +++ b/xen/include/asm-ia64/vmx_vpd.h	Thu Jul 28 07:16:12 2005 -0800
    10.3 @@ -30,32 +30,6 @@
    10.4  
    10.5  #define VPD_SHIFT	17	/* 128K requirement */
    10.6  #define VPD_SIZE	(1 << VPD_SHIFT)
    10.7 -typedef union {
    10.8 -	unsigned long value;
    10.9 -	struct {
   10.10 -		int 	a_int:1;
   10.11 -		int 	a_from_int_cr:1;
   10.12 -		int	a_to_int_cr:1;
   10.13 -		int	a_from_psr:1;
   10.14 -		int	a_from_cpuid:1;
   10.15 -		int	a_cover:1;
   10.16 -		int	a_bsw:1;
   10.17 -		long	reserved:57;
   10.18 -	};
   10.19 -} vac_t;
   10.20 -
   10.21 -typedef union {
   10.22 -	unsigned long value;
   10.23 -	struct {
   10.24 -		int 	d_vmsw:1;
   10.25 -		int 	d_extint:1;
   10.26 -		int	d_ibr_dbr:1;
   10.27 -		int	d_pmc:1;
   10.28 -		int	d_to_pmd:1;
   10.29 -		int	d_itm:1;
   10.30 -		long	reserved:58;
   10.31 -	};
   10.32 -} vdc_t;
   10.33  
   10.34  typedef struct {
   10.35  	unsigned long	dcr;		// CR0
   10.36 @@ -89,29 +63,6 @@ typedef struct {
   10.37  	unsigned long	rsv6[46];
   10.38  } cr_t;
   10.39  
   10.40 -typedef struct vpd {
   10.41 -	vac_t			vac;
   10.42 -	vdc_t			vdc;
   10.43 -	unsigned long		virt_env_vaddr;
   10.44 -	unsigned long		reserved1[29];
   10.45 -	unsigned long		vhpi;
   10.46 -	unsigned long		reserved2[95];
   10.47 -	unsigned long		vgr[16];
   10.48 -	unsigned long		vbgr[16];
   10.49 -	unsigned long		vnat;
   10.50 -	unsigned long		vbnat;
   10.51 -	unsigned long		vcpuid[5];
   10.52 -	unsigned long		reserved3[11];
   10.53 -	unsigned long		vpsr;
   10.54 -	unsigned long		vpr;
   10.55 -	unsigned long		reserved4[76];
   10.56 -	unsigned long		vcr[128];
   10.57 -	unsigned long		reserved5[128];
   10.58 -	unsigned long		reserved6[3456];
   10.59 -	unsigned long		vmm_avail[128];
   10.60 -	unsigned long		reserved7[4096];
   10.61 -} vpd_t;
   10.62 -
   10.63  void vmx_enter_scheduler(void);
   10.64  
   10.65  //FIXME: Map for LID to vcpu, Eddie
    11.1 --- a/xen/include/asm-ia64/xensystem.h	Thu Jul 28 01:48:15 2005 -0800
    11.2 +++ b/xen/include/asm-ia64/xensystem.h	Thu Jul 28 07:16:12 2005 -0800
    11.3 @@ -21,10 +21,13 @@
    11.4  #define XEN_RR7_SWITCH_STUB	 0xb700000000000000
    11.5  #endif // CONFIG_VTI
    11.6  
    11.7 +#define XEN_START_ADDR		 0xf000000000000000
    11.8  #define KERNEL_START		 0xf000000004000000
    11.9  #define PERCPU_ADDR		 0xf100000000000000-PERCPU_PAGE_SIZE
   11.10  #define SHAREDINFO_ADDR		 0xf100000000000000
   11.11  #define VHPT_ADDR		 0xf200000000000000
   11.12 +#define SHARED_ARCHINFO_ADDR	 0xf300000000000000
   11.13 +#define XEN_END_ADDR		 0xf400000000000000
   11.14  
   11.15  #ifndef __ASSEMBLY__
   11.16  
    12.1 --- a/xen/include/public/arch-ia64.h	Thu Jul 28 01:48:15 2005 -0800
    12.2 +++ b/xen/include/public/arch-ia64.h	Thu Jul 28 07:16:12 2005 -0800
    12.3 @@ -140,38 +140,121 @@ struct pt_regs {
    12.4  	struct pt_fpreg f11;		/* scratch */
    12.5  };
    12.6  
    12.7 +typedef union {
    12.8 +	unsigned long value;
    12.9 +	struct {
   12.10 +		int 	a_int:1;
   12.11 +		int 	a_from_int_cr:1;
   12.12 +		int	a_to_int_cr:1;
   12.13 +		int	a_from_psr:1;
   12.14 +		int	a_from_cpuid:1;
   12.15 +		int	a_cover:1;
   12.16 +		int	a_bsw:1;
   12.17 +		long	reserved:57;
   12.18 +	};
   12.19 +} vac_t;
   12.20 +
   12.21 +typedef union {
   12.22 +	unsigned long value;
   12.23 +	struct {
   12.24 +		int 	d_vmsw:1;
   12.25 +		int 	d_extint:1;
   12.26 +		int	d_ibr_dbr:1;
   12.27 +		int	d_pmc:1;
   12.28 +		int	d_to_pmd:1;
   12.29 +		int	d_itm:1;
   12.30 +		long	reserved:58;
   12.31 +	};
   12.32 +} vdc_t;
   12.33 +
   12.34  typedef struct {
   12.35 -	unsigned long ipsr;
   12.36 -	unsigned long iip;
   12.37 -	unsigned long ifs;
   12.38 -	unsigned long precover_ifs;
   12.39 -	unsigned long isr;
   12.40 -	unsigned long ifa;
   12.41 -	unsigned long iipa;
   12.42 -	unsigned long iim;
   12.43 -	unsigned long unat;  // not sure if this is needed until NaT arch is done
   12.44 -	unsigned long tpr;
   12.45 -	unsigned long iha;
   12.46 -	unsigned long itir;
   12.47 -	unsigned long itv;
   12.48 -	unsigned long pmv;
   12.49 -	unsigned long cmcv;
   12.50 -	unsigned long pta;
   12.51 -	int interrupt_collection_enabled; // virtual psr.ic
   12.52 -	int interrupt_delivery_enabled; // virtual psr.i
   12.53 -	int pending_interruption;
   12.54 -	int incomplete_regframe;	// see SDM vol2 6.8
   12.55 -	unsigned long delivery_mask[4];
   12.56 -	int metaphysical_mode;	// 1 = use metaphys mapping, 0 = use virtual
   12.57 -	int banknum;	// 0 or 1, which virtual register bank is active
   12.58 -	unsigned long bank0_regs[16]; // bank0 regs (r16-r31) when bank1 active
   12.59 -	unsigned long bank1_regs[16]; // bank1 regs (r16-r31) when bank0 active
   12.60 -	unsigned long rrs[8];	// region registers
   12.61 -	unsigned long krs[8];	// kernel registers
   12.62 -	unsigned long pkrs[8];	// protection key registers
   12.63 -	unsigned long tmp[8];	// temp registers (e.g. for hyperprivops)
   12.64 +	vac_t			vac;
   12.65 +	vdc_t			vdc;
   12.66 +	unsigned long		virt_env_vaddr;
   12.67 +	unsigned long		reserved1[29];
   12.68 +	unsigned long		vhpi;
   12.69 +	unsigned long		reserved2[95];
   12.70 +	union {
   12.71 +	  unsigned long		vgr[16];
   12.72 +  	  unsigned long bank1_regs[16]; // bank1 regs (r16-r31) when bank0 active
   12.73 +	};
   12.74 +	union {
   12.75 +	  unsigned long		vbgr[16];
   12.76 +	  unsigned long bank0_regs[16]; // bank0 regs (r16-r31) when bank1 active
   12.77 +	};
   12.78 +	unsigned long		vnat;
   12.79 +	unsigned long		vbnat;
   12.80 +	unsigned long		vcpuid[5];
   12.81 +	unsigned long		reserved3[11];
   12.82 +	unsigned long		vpsr;
   12.83 +	unsigned long		vpr;
   12.84 +	unsigned long		reserved4[76];
   12.85 +	union {
   12.86 +	  unsigned long		vcr[128];
   12.87 +          struct {
   12.88 +  	    unsigned long	dcr;		// CR0
   12.89 +	    unsigned long	itm;
   12.90 +	    unsigned long	iva;
   12.91 +	    unsigned long	rsv1[5];
   12.92 +	    unsigned long	pta;		// CR8
   12.93 +	    unsigned long	rsv2[7];
   12.94 +	    unsigned long	ipsr;		// CR16
   12.95 +	    unsigned long	isr;
   12.96 +	    unsigned long	rsv3;
   12.97 +	    unsigned long	iip;
   12.98 +	    unsigned long	ifa;
   12.99 +	    unsigned long	itir;
  12.100 +	    unsigned long	iipa;
  12.101 +	    unsigned long	ifs;
  12.102 +	    unsigned long	iim;		// CR24
  12.103 +	    unsigned long	iha;
  12.104 +	    unsigned long	rsv4[38];
  12.105 +	    unsigned long	lid;		// CR64
  12.106 +	    unsigned long	ivr;
  12.107 +	    unsigned long	tpr;
  12.108 +	    unsigned long	eoi;
  12.109 +	    unsigned long	irr[4];
  12.110 +	    unsigned long	itv;		// CR72
  12.111 +	    unsigned long	pmv;
  12.112 +	    unsigned long	cmcv;
  12.113 +	    unsigned long	rsv5[5];
  12.114 +	    unsigned long	lrr0;		// CR80
  12.115 +	    unsigned long	lrr1;
  12.116 +	    unsigned long	rsv6[46];
  12.117 +          };
  12.118 +	};
  12.119 +	union {
  12.120 +	  unsigned long		reserved5[128];
  12.121 +	  struct {
  12.122 +	    unsigned long precover_ifs;
  12.123 +	    unsigned long unat;  // not sure if this is needed until NaT arch is done
  12.124 +	    int interrupt_collection_enabled; // virtual psr.ic
  12.125 +	    int interrupt_delivery_enabled; // virtual psr.i
  12.126 +	    int pending_interruption;
  12.127 +	    int incomplete_regframe;	// see SDM vol2 6.8
  12.128 +	    unsigned long delivery_mask[4];
  12.129 +	    int metaphysical_mode;	// 1 = use metaphys mapping, 0 = use virtual
  12.130 +	    int banknum;	// 0 or 1, which virtual register bank is active
  12.131 +	    unsigned long rrs[8];	// region registers
  12.132 +	    unsigned long krs[8];	// kernel registers
  12.133 +	    unsigned long pkrs[8];	// protection key registers
  12.134 +	    unsigned long tmp[8];	// temp registers (e.g. for hyperprivops)
  12.135 +	  };
  12.136 +        };
  12.137 +#ifdef CONFIG_VTI
  12.138 +	unsigned long		reserved6[3456];
  12.139 +	unsigned long		vmm_avail[128];
  12.140 +	unsigned long		reserved7[4096];
  12.141 +#endif
  12.142 +} mapped_regs_t;
  12.143 +
  12.144 +typedef struct {
  12.145 +	mapped_regs_t *privregs;
  12.146  	int evtchn_vector;
  12.147  } arch_vcpu_info_t;
  12.148 +
  12.149 +typedef arch_vcpu_info_t vpd_t;
  12.150 +
  12.151  #define __ARCH_HAS_VCPU_INFO
  12.152  
  12.153  typedef struct {