direct-io.hg

view xen/drivers/pci/setup-res.c @ 875:ad4db8b417c1

bitkeeper revision 1.547 (3fa3dd2aH8eamu3ONvYovJgq8wBNbQ)

Many files:
Fixes to the DOM0 interface and domain building code. Ready for new save/restore dom0_ops.
author kaf24@scramble.cl.cam.ac.uk
date Sat Nov 01 16:19:54 2003 +0000 (2003-11-01)
parents bb07751512ba
children 890460f07ddf
line source
1 /*
2 * drivers/pci/setup-res.c
3 *
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
8 *
9 * Support routines for initializing a PCI subsystem.
10 */
12 /* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
14 /*
15 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Resource sorting
17 */
19 #include <linux/init.h>
20 #include <linux/lib.h>
21 #include <linux/pci.h>
22 #include <linux/errno.h>
23 #include <linux/ioport.h>
24 #include <linux/cache.h>
25 #include <linux/slab.h>
28 #define DEBUG_CONFIG 0
29 #if DEBUG_CONFIG
30 # define DBGC(args) printk args
31 #else
32 # define DBGC(args)
33 #endif
36 int __init
37 pci_claim_resource(struct pci_dev *dev, int resource)
38 {
39 struct resource *res = &dev->resource[resource];
40 struct resource *root = pci_find_parent_resource(dev, res);
41 int err;
43 err = -EINVAL;
44 if (root != NULL) {
45 err = request_resource(root, res);
46 if (err) {
47 printk(KERN_ERR "PCI: Address space collision on "
48 "region %d of device %s [%lx:%lx]\n",
49 resource, dev->name, res->start, res->end);
50 }
51 } else {
52 printk(KERN_ERR "PCI: No parent found for region %d "
53 "of device %s\n", resource, dev->name);
54 }
56 return err;
57 }
59 /*
60 * Given the PCI bus a device resides on, try to
61 * find an acceptable resource allocation for a
62 * specific device resource..
63 */
64 static int pci_assign_bus_resource(const struct pci_bus *bus,
65 struct pci_dev *dev,
66 struct resource *res,
67 unsigned long size,
68 unsigned long min,
69 unsigned int type_mask,
70 int resno)
71 {
72 unsigned long align;
73 int i;
75 type_mask |= IORESOURCE_IO | IORESOURCE_MEM;
76 for (i = 0 ; i < 4; i++) {
77 struct resource *r = bus->resource[i];
78 if (!r)
79 continue;
81 /* type_mask must match */
82 if ((res->flags ^ r->flags) & type_mask)
83 continue;
85 /* We cannot allocate a non-prefetching resource
86 from a pre-fetching area */
87 if ((r->flags & IORESOURCE_PREFETCH) &&
88 !(res->flags & IORESOURCE_PREFETCH))
89 continue;
91 /* The bridge resources are special, as their
92 size != alignment. Sizing routines return
93 required alignment in the "start" field. */
94 align = (resno < PCI_BRIDGE_RESOURCES) ? size : res->start;
96 /* Ok, try it out.. */
97 if (allocate_resource(r, res, size, min, -1, align,
98 pcibios_align_resource, dev) < 0)
99 continue;
101 /* Update PCI config space. */
102 pcibios_update_resource(dev, r, res, resno);
103 return 0;
104 }
105 return -EBUSY;
106 }
108 int
109 pci_assign_resource(struct pci_dev *dev, int i)
110 {
111 const struct pci_bus *bus = dev->bus;
112 struct resource *res = dev->resource + i;
113 unsigned long size, min;
115 size = res->end - res->start + 1;
116 min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
118 /* First, try exact prefetching match.. */
119 if (pci_assign_bus_resource(bus, dev, res, size, min, IORESOURCE_PREFETCH, i) < 0) {
120 /*
121 * That failed.
122 *
123 * But a prefetching area can handle a non-prefetching
124 * window (it will just not perform as well).
125 */
126 if (!(res->flags & IORESOURCE_PREFETCH) || pci_assign_bus_resource(bus, dev, res, size, min, 0, i) < 0) {
127 printk(KERN_ERR "PCI: Failed to allocate resource %d(%lx-%lx) for %s\n",
128 i, res->start, res->end, dev->slot_name);
129 return -EBUSY;
130 }
131 }
133 DBGC((KERN_ERR " got res[%lx:%lx] for resource %d of %s\n", res->start,
134 res->end, i, dev->name));
136 return 0;
137 }
139 /* Sort resources by alignment */
140 void __init
141 pdev_sort_resources(struct pci_dev *dev, struct resource_list *head)
142 {
143 int i;
145 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
146 struct resource *r;
147 struct resource_list *list, *tmp;
148 unsigned long r_align;
150 r = &dev->resource[i];
151 r_align = r->end - r->start;
153 if (!(r->flags) || r->parent)
154 continue;
155 if (!r_align) {
156 printk(KERN_WARNING "PCI: Ignore bogus resource %d "
157 "[%lx:%lx] of %s\n",
158 i, r->start, r->end, dev->name);
159 continue;
160 }
161 r_align = (i < PCI_BRIDGE_RESOURCES) ? r_align + 1 : r->start;
162 for (list = head; ; list = list->next) {
163 unsigned long align = 0;
164 struct resource_list *ln = list->next;
165 int idx;
167 if (ln) {
168 idx = ln->res - &ln->dev->resource[0];
169 align = (idx < PCI_BRIDGE_RESOURCES) ?
170 ln->res->end - ln->res->start + 1 :
171 ln->res->start;
172 }
173 if (r_align > align) {
174 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
175 if (!tmp)
176 panic("pdev_sort_resources(): "
177 "kmalloc() failed!\n");
178 tmp->next = ln;
179 tmp->res = r;
180 tmp->dev = dev;
181 list->next = tmp;
182 break;
183 }
184 }
185 }
186 }
188 void __init
189 pdev_enable_device(struct pci_dev *dev)
190 {
191 u32 reg;
192 u16 cmd;
193 int i;
195 DBGC((KERN_ERR "PCI enable device: (%s)\n", dev->name));
197 pci_read_config_word(dev, PCI_COMMAND, &cmd);
199 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
200 struct resource *res = &dev->resource[i];
202 if (res->flags & IORESOURCE_IO)
203 cmd |= PCI_COMMAND_IO;
204 else if (res->flags & IORESOURCE_MEM)
205 cmd |= PCI_COMMAND_MEMORY;
206 }
208 /* Special case, disable the ROM. Several devices act funny
209 (ie. do not respond to memory space writes) when it is left
210 enabled. A good example are QlogicISP adapters. */
212 if (dev->rom_base_reg) {
213 pci_read_config_dword(dev, dev->rom_base_reg, &reg);
214 reg &= ~PCI_ROM_ADDRESS_ENABLE;
215 pci_write_config_dword(dev, dev->rom_base_reg, reg);
216 dev->resource[PCI_ROM_RESOURCE].flags &= ~PCI_ROM_ADDRESS_ENABLE;
217 }
219 /* All of these (may) have I/O scattered all around and may not
220 use I/O base address registers at all. So we just have to
221 always enable IO to these devices. */
222 if ((dev->class >> 8) == PCI_CLASS_NOT_DEFINED
223 || (dev->class >> 8) == PCI_CLASS_NOT_DEFINED_VGA
224 || (dev->class >> 8) == PCI_CLASS_STORAGE_IDE
225 || (dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) {
226 cmd |= PCI_COMMAND_IO;
227 }
229 /* ??? Always turn on bus mastering. If the device doesn't support
230 it, the bit will go into the bucket. */
231 cmd |= PCI_COMMAND_MASTER;
233 /* Set the cache line and default latency (32). */
234 pci_write_config_word(dev, PCI_CACHE_LINE_SIZE,
235 (32 << 8) | (L1_CACHE_BYTES / sizeof(u32)));
237 /* Enable the appropriate bits in the PCI command register. */
238 pci_write_config_word(dev, PCI_COMMAND, cmd);
240 DBGC((KERN_ERR " cmd reg 0x%x\n", cmd));
241 }