direct-io.hg

view xen/drivers/pci/quirks.c @ 875:ad4db8b417c1

bitkeeper revision 1.547 (3fa3dd2aH8eamu3ONvYovJgq8wBNbQ)

Many files:
Fixes to the DOM0 interface and domain building code. Ready for new save/restore dom0_ops.
author kaf24@scramble.cl.cam.ac.uk
date Sat Nov 01 16:19:54 2003 +0000 (2003-11-01)
parents bb07751512ba
children 890460f07ddf
line source
1 /*
2 * $Id: quirks.c,v 1.5 1998/05/02 19:24:14 mj Exp $
3 *
4 * This file contains work-arounds for many known PCI hardware
5 * bugs. Devices present only on certain architectures (host
6 * bridges et cetera) should be handled in arch-specific code.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
10 * The bridge optimization stuff has been removed. If you really
11 * have a silly BIOS which is unable to set your host bridge right,
12 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
13 */
15 #include <linux/config.h>
16 #include <linux/types.h>
17 #include <linux/lib.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
20 #include <linux/delay.h>
22 #undef DEBUG
24 /* Deal with broken BIOS'es that neglect to enable passive release,
25 which can cause problems in combination with the 82441FX/PPro MTRRs */
26 static void __init quirk_passive_release(struct pci_dev *dev)
27 {
28 struct pci_dev *d = NULL;
29 unsigned char dlc;
31 /* We have to make sure a particular bit is set in the PIIX3
32 ISA bridge, so we have to go out and find it. */
33 while ((d = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
34 pci_read_config_byte(d, 0x82, &dlc);
35 if (!(dlc & 1<<1)) {
36 printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", d->slot_name);
37 dlc |= 1<<1;
38 pci_write_config_byte(d, 0x82, dlc);
39 }
40 }
41 }
43 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
44 but VIA don't answer queries. If you happen to have good contacts at VIA
45 ask them for me please -- Alan
47 This appears to be BIOS not version dependent. So presumably there is a
48 chipset level fix */
51 int isa_dma_bridge_buggy; /* Exported */
53 static void __init quirk_isa_dma_hangs(struct pci_dev *dev)
54 {
55 if (!isa_dma_bridge_buggy) {
56 isa_dma_bridge_buggy=1;
57 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n");
58 }
59 }
61 int pci_pci_problems;
63 /*
64 * Chipsets where PCI->PCI transfers vanish or hang
65 */
67 static void __init quirk_nopcipci(struct pci_dev *dev)
68 {
69 if((pci_pci_problems&PCIPCI_FAIL)==0)
70 {
71 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n");
72 pci_pci_problems|=PCIPCI_FAIL;
73 }
74 }
76 /*
77 * Triton requires workarounds to be used by the drivers
78 */
80 static void __init quirk_triton(struct pci_dev *dev)
81 {
82 if((pci_pci_problems&PCIPCI_TRITON)==0)
83 {
84 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
85 pci_pci_problems|=PCIPCI_TRITON;
86 }
87 }
89 /*
90 * VIA Apollo KT133 needs PCI latency patch
91 * Made according to a windows driver based patch by George E. Breese
92 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
93 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on which
94 * Mr Breese based his work.
95 *
96 * Updated based on further information from the site and also on
97 * information provided by VIA
98 */
99 static void __init quirk_vialatency(struct pci_dev *dev)
100 {
101 struct pci_dev *p;
102 u8 rev;
103 u8 busarb;
104 /* Ok we have a potential problem chipset here. Now see if we have
105 a buggy southbridge */
107 p=pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
108 if(p!=NULL)
109 {
110 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
111 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
112 /* Check for buggy part revisions */
113 if (rev < 0x40 || rev > 0x42)
114 return;
115 }
116 else
117 {
118 p = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
119 if(p==NULL) /* No problem parts */
120 return;
121 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
122 /* Check for buggy part revisions */
123 if (rev < 0x10 || rev > 0x12)
124 return;
125 }
127 /*
128 * Ok we have the problem. Now set the PCI master grant to
129 * occur every master grant. The apparent bug is that under high
130 * PCI load (quite common in Linux of course) you can get data
131 * loss when the CPU is held off the bus for 3 bus master requests
132 * This happens to include the IDE controllers....
133 *
134 * VIA only apply this fix when an SB Live! is present but under
135 * both Linux and Windows this isnt enough, and we have seen
136 * corruption without SB Live! but with things like 3 UDMA IDE
137 * controllers. So we ignore that bit of the VIA recommendation..
138 */
140 pci_read_config_byte(dev, 0x76, &busarb);
141 /* Set bit 4 and bi 5 of byte 76 to 0x01
142 "Master priority rotation on every PCI master grant */
143 busarb &= ~(1<<5);
144 busarb |= (1<<4);
145 pci_write_config_byte(dev, 0x76, busarb);
146 printk(KERN_INFO "Applying VIA southbridge workaround.\n");
147 }
149 /*
150 * VIA Apollo VP3 needs ETBF on BT848/878
151 */
153 static void __init quirk_viaetbf(struct pci_dev *dev)
154 {
155 if((pci_pci_problems&PCIPCI_VIAETBF)==0)
156 {
157 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
158 pci_pci_problems|=PCIPCI_VIAETBF;
159 }
160 }
161 static void __init quirk_vsfx(struct pci_dev *dev)
162 {
163 if((pci_pci_problems&PCIPCI_VSFX)==0)
164 {
165 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
166 pci_pci_problems|=PCIPCI_VSFX;
167 }
168 }
170 /*
171 * Ali Magik requires workarounds to be used by the drivers
172 * that DMA to AGP space. Latency must be set to 0xA and triton
173 * workaround applied too
174 * [Info kindly provided by ALi]
175 */
177 static void __init quirk_alimagik(struct pci_dev *dev)
178 {
179 if((pci_pci_problems&PCIPCI_ALIMAGIK)==0)
180 {
181 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
182 pci_pci_problems|=PCIPCI_ALIMAGIK|PCIPCI_TRITON;
183 }
184 }
186 /*
187 * Natoma has some interesting boundary conditions with Zoran stuff
188 * at least
189 */
191 static void __init quirk_natoma(struct pci_dev *dev)
192 {
193 if((pci_pci_problems&PCIPCI_NATOMA)==0)
194 {
195 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
196 pci_pci_problems|=PCIPCI_NATOMA;
197 }
198 }
200 /*
201 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
202 * If it's needed, re-allocate the region.
203 */
205 static void __init quirk_s3_64M(struct pci_dev *dev)
206 {
207 struct resource *r = &dev->resource[0];
209 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
210 r->start = 0;
211 r->end = 0x3ffffff;
212 }
213 }
215 static void __init quirk_io_region(struct pci_dev *dev, unsigned region, unsigned size, int nr)
216 {
217 region &= ~(size-1);
218 if (region) {
219 struct resource *res = dev->resource + nr;
221 res->name = dev->name;
222 res->start = region;
223 res->end = region + size - 1;
224 res->flags = IORESOURCE_IO;
225 pci_claim_resource(dev, nr);
226 }
227 }
229 /*
230 * ATI Northbridge setups MCE the processor if you even
231 * read somewhere between 0x3b0->0x3bb or read 0x3d3
232 */
234 static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
235 {
236 printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
237 /* Mae rhaid in i beidio a edrych ar y lleoliad I/O hyn */
238 request_region(0x3b0, 0x0C, "RadeonIGP");
239 request_region(0x3d3, 0x01, "RadeonIGP");
240 }
242 /*
243 * Let's make the southbridge information explicit instead
244 * of having to worry about people probing the ACPI areas,
245 * for example.. (Yes, it happens, and if you read the wrong
246 * ACPI register it will put the machine to sleep with no
247 * way of waking it up again. Bummer).
248 *
249 * ALI M7101: Two IO regions pointed to by words at
250 * 0xE0 (64 bytes of ACPI registers)
251 * 0xE2 (32 bytes of SMB registers)
252 */
253 static void __init quirk_ali7101_acpi(struct pci_dev *dev)
254 {
255 u16 region;
257 pci_read_config_word(dev, 0xE0, &region);
258 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES);
259 pci_read_config_word(dev, 0xE2, &region);
260 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1);
261 }
263 /*
264 * PIIX4 ACPI: Two IO regions pointed to by longwords at
265 * 0x40 (64 bytes of ACPI registers)
266 * 0x90 (32 bytes of SMB registers)
267 */
268 static void __init quirk_piix4_acpi(struct pci_dev *dev)
269 {
270 u32 region;
272 pci_read_config_dword(dev, 0x40, &region);
273 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES);
274 pci_read_config_dword(dev, 0x90, &region);
275 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1);
276 }
278 /*
279 * VIA ACPI: One IO region pointed to by longword at
280 * 0x48 or 0x20 (256 bytes of ACPI registers)
281 */
282 static void __init quirk_vt82c586_acpi(struct pci_dev *dev)
283 {
284 u8 rev;
285 u32 region;
287 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
288 if (rev & 0x10) {
289 pci_read_config_dword(dev, 0x48, &region);
290 region &= PCI_BASE_ADDRESS_IO_MASK;
291 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES);
292 }
293 }
295 /*
296 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
297 * 0x48 (256 bytes of ACPI registers)
298 * 0x70 (128 bytes of hardware monitoring register)
299 * 0x90 (16 bytes of SMB registers)
300 */
301 static void __init quirk_vt82c686_acpi(struct pci_dev *dev)
302 {
303 u16 hm;
304 u32 smb;
306 quirk_vt82c586_acpi(dev);
308 pci_read_config_word(dev, 0x70, &hm);
309 hm &= PCI_BASE_ADDRESS_IO_MASK;
310 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1);
312 pci_read_config_dword(dev, 0x90, &smb);
313 smb &= PCI_BASE_ADDRESS_IO_MASK;
314 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2);
315 }
318 #ifdef CONFIG_X86_IO_APIC
319 extern int nr_ioapics;
321 /*
322 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
323 * devices to the external APIC.
324 *
325 * TODO: When we have device-specific interrupt routers,
326 * this code will go away from quirks.
327 */
328 static void __init quirk_via_ioapic(struct pci_dev *dev)
329 {
330 u8 tmp;
332 if (nr_ioapics < 1)
333 tmp = 0; /* nothing routed to external APIC */
334 else
335 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
337 printk(KERN_INFO "PCI: %sbling Via external APIC routing\n",
338 tmp == 0 ? "Disa" : "Ena");
340 /* Offset 0x58: External APIC IRQ output control */
341 pci_write_config_byte (dev, 0x58, tmp);
342 }
344 #endif /* CONFIG_X86_IO_APIC */
347 /*
348 * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip
349 * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature:
350 * when written, it makes an internal connection to the PIC.
351 * For these devices, this register is defined to be 4 bits wide.
352 * Normally this is fine. However for IO-APIC motherboards, or
353 * non-x86 architectures (yes Via exists on PPC among other places),
354 * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get
355 * interrupts delivered properly.
356 *
357 * TODO: When we have device-specific interrupt routers,
358 * quirk_via_irqpic will go away from quirks.
359 */
361 /*
362 * FIXME: it is questionable that quirk_via_acpi
363 * is needed. It shows up as an ISA bridge, and does not
364 * support the PCI_INTERRUPT_LINE register at all. Therefore
365 * it seems like setting the pci_dev's 'irq' to the
366 * value of the ACPI SCI interrupt is only done for convenience.
367 * -jgarzik
368 */
369 static void __init quirk_via_acpi(struct pci_dev *d)
370 {
371 /*
372 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
373 */
374 u8 irq;
375 pci_read_config_byte(d, 0x42, &irq);
376 irq &= 0xf;
377 if (irq && (irq != 2))
378 d->irq = irq;
379 }
381 static void __init quirk_via_irqpic(struct pci_dev *dev)
382 {
383 u8 irq, new_irq = dev->irq & 0xf;
385 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
387 if (new_irq != irq) {
388 printk(KERN_INFO "PCI: Via IRQ fixup for %s, from %d to %d\n",
389 dev->slot_name, irq, new_irq);
391 udelay(15);
392 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
393 }
394 }
397 /*
398 * PIIX3 USB: We have to disable USB interrupts that are
399 * hardwired to PIRQD# and may be shared with an
400 * external device.
401 *
402 * Legacy Support Register (LEGSUP):
403 * bit13: USB PIRQ Enable (USBPIRQDEN),
404 * bit4: Trap/SMI On IRQ Enable (USBSMIEN).
405 *
406 * We mask out all r/wc bits, too.
407 */
408 static void __init quirk_piix3_usb(struct pci_dev *dev)
409 {
410 u16 legsup;
412 pci_read_config_word(dev, 0xc0, &legsup);
413 legsup &= 0x50ef;
414 pci_write_config_word(dev, 0xc0, legsup);
415 }
417 /*
418 * VIA VT82C598 has its device ID settable and many BIOSes
419 * set it to the ID of VT82C597 for backward compatibility.
420 * We need to switch it off to be able to recognize the real
421 * type of the chip.
422 */
423 static void __init quirk_vt82c598_id(struct pci_dev *dev)
424 {
425 pci_write_config_byte(dev, 0xfc, 0);
426 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
427 }
429 /*
430 * CardBus controllers have a legacy base address that enables them
431 * to respond as i82365 pcmcia controllers. We don't want them to
432 * do this even if the Linux CardBus driver is not loaded, because
433 * the Linux i82365 driver does not (and should not) handle CardBus.
434 */
435 static void __init quirk_cardbus_legacy(struct pci_dev *dev)
436 {
437 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
438 return;
439 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
440 }
442 /*
443 * The AMD io apic can hang the box when an apic irq is masked.
444 * We check all revs >= B0 (yet not in the pre production!) as the bug
445 * is currently marked NoFix
446 *
447 * We have multiple reports of hangs with this chipset that went away with
448 * noapic specified. For the moment we assume its the errata. We may be wrong
449 * of course. However the advice is demonstrably good even if so..
450 */
452 static void __init quirk_amd_ioapic(struct pci_dev *dev)
453 {
454 u8 rev;
456 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
457 if(rev >= 0x02)
458 {
459 printk(KERN_WARNING "I/O APIC: AMD Errata #22 may be present. In the event of instability try\n");
460 printk(KERN_WARNING " : booting with the \"noapic\" option.\n");
461 }
462 }
464 /*
465 * Following the PCI ordering rules is optional on the AMD762. I'm not
466 * sure what the designers were smoking but let's not inhale...
467 *
468 * To be fair to AMD, it follows the spec by default, its BIOS people
469 * who turn it off!
470 */
472 static void __init quirk_amd_ordering(struct pci_dev *dev)
473 {
474 u32 pcic;
475 pci_read_config_dword(dev, 0x4C, &pcic);
476 if((pcic&6)!=6)
477 {
478 pcic |= 6;
479 printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n");
480 pci_write_config_dword(dev, 0x4C, pcic);
481 pci_read_config_dword(dev, 0x84, &pcic);
482 pcic |= (1<<23); /* Required in this mode */
483 pci_write_config_dword(dev, 0x84, pcic);
484 }
485 }
487 /*
488 * DreamWorks provided workaround for Dunord I-3000 problem
489 *
490 * This card decodes and responds to addresses not apparently
491 * assigned to it. We force a larger allocation to ensure that
492 * nothing gets put too close to it.
493 */
495 static void __init quirk_dunord ( struct pci_dev * dev )
496 {
497 struct resource * r = & dev -> resource [ 1 ];
498 r -> start = 0;
499 r -> end = 0xffffff;
500 }
502 static void __init quirk_transparent_bridge(struct pci_dev *dev)
503 {
504 dev->transparent = 1;
505 }
507 /*
508 * Common misconfiguration of the MediaGX/Geode PCI master that will
509 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
510 * datasheets found at http://www.national.com/ds/GX for info on what
511 * these bits do. <christer@weinigel.se>
512 */
514 static void __init quirk_mediagx_master(struct pci_dev *dev)
515 {
516 u8 reg;
517 pci_read_config_byte(dev, 0x41, &reg);
518 if (reg & 2) {
519 reg &= ~2;
520 printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
521 pci_write_config_byte(dev, 0x41, reg);
522 }
523 }
525 /*
526 * As per PCI spec, ignore base address registers 0-3 of the IDE controllers
527 * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and
528 * secondary channels respectively). If the device reports Compatible mode
529 * but does use BAR0-3 for address decoding, we assume that firmware has
530 * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374).
531 * Exceptions (if they exist) must be handled in chip/architecture specific
532 * fixups.
533 *
534 * Note: for non x86 people. You may need an arch specific quirk to handle
535 * moving IDE devices to native mode as well. Some plug in card devices power
536 * up in compatible mode and assume the BIOS will adjust them.
537 *
538 * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as
539 * we do now ? We don't want is pci_enable_device to come along
540 * and assign new resources. Both approaches work for that.
541 */
543 static void __devinit quirk_ide_bases(struct pci_dev *dev)
544 {
545 struct resource *res;
546 int first_bar = 2, last_bar = 0;
548 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
549 return;
551 res = &dev->resource[0];
553 /* primary channel: ProgIf bit 0, BAR0, BAR1 */
554 if (!(dev->class & 1) && (res[0].flags || res[1].flags)) {
555 res[0].start = res[0].end = res[0].flags = 0;
556 res[1].start = res[1].end = res[1].flags = 0;
557 first_bar = 0;
558 last_bar = 1;
559 }
561 /* secondary channel: ProgIf bit 2, BAR2, BAR3 */
562 if (!(dev->class & 4) && (res[2].flags || res[3].flags)) {
563 res[2].start = res[2].end = res[2].flags = 0;
564 res[3].start = res[3].end = res[3].flags = 0;
565 last_bar = 3;
566 }
568 if (!last_bar)
569 return;
571 printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n",
572 first_bar, last_bar, dev->slot_name);
573 }
575 /*
576 * The main table of quirks.
577 */
579 static struct pci_fixup pci_fixups[] __initdata = {
580 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord },
581 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release },
582 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release },
583 /*
584 * Its not totally clear which chipsets are the problematic ones
585 * We know 82C586 and 82C596 variants are affected.
586 */
587 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs },
588 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs },
589 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs },
590 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M },
591 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M },
592 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton },
593 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton },
594 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton },
595 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton },
596 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma },
597 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma },
598 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma },
599 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma },
600 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma },
601 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma },
602 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik },
603 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik },
604 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci },
605 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci },
606 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency },
607 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency },
608 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency },
609 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx },
610 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf },
611 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id },
612 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi },
613 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi },
614 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi },
615 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi },
616 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_2, quirk_piix3_usb },
617 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_2, quirk_piix3_usb },
618 { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases },
619 { PCI_FIXUP_FINAL, PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy },
621 #ifdef CONFIG_X86_IO_APIC
622 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic },
623 #endif
624 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi },
625 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi },
626 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, quirk_via_irqpic },
627 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_5, quirk_via_irqpic },
628 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_6, quirk_via_irqpic },
630 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic },
631 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering },
632 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_IGP, quirk_ati_exploding_mce },
633 /*
634 * i82380FB mobile docking controller: its PCI-to-PCI bridge
635 * is subtractive decoding (transparent), and does indicate this
636 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
637 * instead of 0x01.
638 */
639 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge },
641 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master },
643 { 0 }
644 };
647 static void pci_do_fixups(struct pci_dev *dev, int pass, struct pci_fixup *f)
648 {
649 while (f->pass) {
650 if (f->pass == pass &&
651 (f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
652 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
653 #ifdef DEBUG
654 printk(KERN_INFO "PCI: Calling quirk %p for %s\n", f->hook, dev->slot_name);
655 #endif
656 f->hook(dev);
657 }
658 f++;
659 }
660 }
662 void pci_fixup_device(int pass, struct pci_dev *dev)
663 {
664 pci_do_fixups(dev, pass, pcibios_fixups);
665 pci_do_fixups(dev, pass, pci_fixups);
666 }