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view xen/drivers/net/tg3.h @ 875:ad4db8b417c1

bitkeeper revision 1.547 (3fa3dd2aH8eamu3ONvYovJgq8wBNbQ)

Many files:
Fixes to the DOM0 interface and domain building code. Ready for new save/restore dom0_ops.
author kaf24@scramble.cl.cam.ac.uk
date Sat Nov 01 16:19:54 2003 +0000 (2003-11-01)
parents 47f6cdee5a9b
children d8941770d7a7
line source
1 /* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $
2 * tg3.h: Definitions for Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com)
6 */
8 #ifndef _T3_H
9 #define _T3_H
11 #define TG3_64BIT_REG_HIGH 0x00UL
12 #define TG3_64BIT_REG_LOW 0x04UL
14 /* Descriptor block info. */
15 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
16 #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
17 #define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */
18 #define BDINFO_FLAGS_DISABLED 0x00000002
19 #define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
20 #define BDINFO_FLAGS_MAXLEN_SHIFT 16
21 #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
22 #define TG3_BDINFO_SIZE 0x10UL
24 /* XXX Xen: No copy break. */
25 #define RX_COPY_THRESHOLD 0 /*256*/
27 #define RX_STD_MAX_SIZE 1536
28 #define RX_JUMBO_MAX_SIZE 0xdeadbeef /* XXX */
30 /* First 256 bytes are a mirror of PCI config space. */
31 #define TG3PCI_VENDOR 0x00000000
32 #define TG3PCI_VENDOR_BROADCOM 0x14e4
33 #define TG3PCI_DEVICE 0x00000002
34 #define TG3PCI_DEVICE_TIGON3_1 0x1644 /* BCM5700 */
35 #define TG3PCI_DEVICE_TIGON3_2 0x1645 /* BCM5701 */
36 #define TG3PCI_DEVICE_TIGON3_3 0x1646 /* BCM5702 */
37 #define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */
38 #define TG3PCI_COMMAND 0x00000004
39 #define TG3PCI_STATUS 0x00000006
40 #define TG3PCI_CCREVID 0x00000008
41 #define TG3PCI_CACHELINESZ 0x0000000c
42 #define TG3PCI_LATTIMER 0x0000000d
43 #define TG3PCI_HEADERTYPE 0x0000000e
44 #define TG3PCI_BIST 0x0000000f
45 #define TG3PCI_BASE0_LOW 0x00000010
46 #define TG3PCI_BASE0_HIGH 0x00000014
47 /* 0x18 --> 0x2c unused */
48 #define TG3PCI_SUBSYSVENID 0x0000002c
49 #define TG3PCI_SUBSYSID 0x0000002e
50 #define TG3PCI_ROMADDR 0x00000030
51 #define TG3PCI_CAPLIST 0x00000034
52 /* 0x35 --> 0x3c unused */
53 #define TG3PCI_IRQ_LINE 0x0000003c
54 #define TG3PCI_IRQ_PIN 0x0000003d
55 #define TG3PCI_MIN_GNT 0x0000003e
56 #define TG3PCI_MAX_LAT 0x0000003f
57 #define TG3PCI_X_CAPS 0x00000040
58 #define PCIX_CAPS_RELAXED_ORDERING 0x00020000
59 #define PCIX_CAPS_SPLIT_MASK 0x00700000
60 #define PCIX_CAPS_SPLIT_SHIFT 20
61 #define PCIX_CAPS_BURST_MASK 0x000c0000
62 #define PCIX_CAPS_BURST_SHIFT 18
63 #define PCIX_CAPS_MAX_BURST_5704 2
64 #define TG3PCI_PM_CAP_PTR 0x00000041
65 #define TG3PCI_X_COMMAND 0x00000042
66 #define TG3PCI_X_STATUS 0x00000044
67 #define TG3PCI_PM_CAP_ID 0x00000048
68 #define TG3PCI_VPD_CAP_PTR 0x00000049
69 #define TG3PCI_PM_CAPS 0x0000004a
70 #define TG3PCI_PM_CTRL_STAT 0x0000004c
71 #define TG3PCI_BR_SUPP_EXT 0x0000004e
72 #define TG3PCI_PM_DATA 0x0000004f
73 #define TG3PCI_VPD_CAP_ID 0x00000050
74 #define TG3PCI_MSI_CAP_PTR 0x00000051
75 #define TG3PCI_VPD_ADDR_FLAG 0x00000052
76 #define VPD_ADDR_FLAG_WRITE 0x00008000
77 #define TG3PCI_VPD_DATA 0x00000054
78 #define TG3PCI_MSI_CAP_ID 0x00000058
79 #define TG3PCI_NXT_CAP_PTR 0x00000059
80 #define TG3PCI_MSI_CTRL 0x0000005a
81 #define TG3PCI_MSI_ADDR_LOW 0x0000005c
82 #define TG3PCI_MSI_ADDR_HIGH 0x00000060
83 #define TG3PCI_MSI_DATA 0x00000064
84 /* 0x66 --> 0x68 unused */
85 #define TG3PCI_MISC_HOST_CTRL 0x00000068
86 #define MISC_HOST_CTRL_CLEAR_INT 0x00000001
87 #define MISC_HOST_CTRL_MASK_PCI_INT 0x00000002
88 #define MISC_HOST_CTRL_BYTE_SWAP 0x00000004
89 #define MISC_HOST_CTRL_WORD_SWAP 0x00000008
90 #define MISC_HOST_CTRL_PCISTATE_RW 0x00000010
91 #define MISC_HOST_CTRL_CLKREG_RW 0x00000020
92 #define MISC_HOST_CTRL_REGWORD_SWAP 0x00000040
93 #define MISC_HOST_CTRL_INDIR_ACCESS 0x00000080
94 #define MISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100
95 #define MISC_HOST_CTRL_TAGGED_STATUS 0x00000200
96 #define MISC_HOST_CTRL_CHIPREV 0xffff0000
97 #define MISC_HOST_CTRL_CHIPREV_SHIFT 16
98 #define GET_CHIP_REV_ID(MISC_HOST_CTRL) \
99 (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \
100 MISC_HOST_CTRL_CHIPREV_SHIFT)
101 #define CHIPREV_ID_5700_A0 0x7000
102 #define CHIPREV_ID_5700_A1 0x7001
103 #define CHIPREV_ID_5700_B0 0x7100
104 #define CHIPREV_ID_5700_B1 0x7101
105 #define CHIPREV_ID_5700_B3 0x7102
106 #define CHIPREV_ID_5700_ALTIMA 0x7104
107 #define CHIPREV_ID_5700_C0 0x7200
108 #define CHIPREV_ID_5701_A0 0x0000
109 #define CHIPREV_ID_5701_B0 0x0100
110 #define CHIPREV_ID_5701_B2 0x0102
111 #define CHIPREV_ID_5701_B5 0x0105
112 #define CHIPREV_ID_5703_A0 0x1000
113 #define CHIPREV_ID_5703_A1 0x1001
114 #define CHIPREV_ID_5703_A2 0x1002
115 #define CHIPREV_ID_5703_A3 0x1003
116 #define CHIPREV_ID_5704_A0 0x2000
117 #define CHIPREV_ID_5704_A1 0x2001
118 #define CHIPREV_ID_5704_A2 0x2002
119 #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12)
120 #define ASIC_REV_5700 0x07
121 #define ASIC_REV_5701 0x00
122 #define ASIC_REV_5703 0x01
123 #define ASIC_REV_5704 0x02
124 #define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8)
125 #define CHIPREV_5700_AX 0x70
126 #define CHIPREV_5700_BX 0x71
127 #define CHIPREV_5700_CX 0x72
128 #define CHIPREV_5701_AX 0x00
129 #define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff)
130 #define METAL_REV_A0 0x00
131 #define METAL_REV_A1 0x01
132 #define METAL_REV_B0 0x00
133 #define METAL_REV_B1 0x01
134 #define METAL_REV_B2 0x02
135 #define TG3PCI_DMA_RW_CTRL 0x0000006c
136 #define DMA_RWCTRL_MIN_DMA 0x000000ff
137 #define DMA_RWCTRL_MIN_DMA_SHIFT 0
138 #define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700
139 #define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000
140 #define DMA_RWCTRL_READ_BNDRY_16 0x00000100
141 #define DMA_RWCTRL_READ_BNDRY_32 0x00000200
142 #define DMA_RWCTRL_READ_BNDRY_64 0x00000300
143 #define DMA_RWCTRL_READ_BNDRY_128 0x00000400
144 #define DMA_RWCTRL_READ_BNDRY_256 0x00000500
145 #define DMA_RWCTRL_READ_BNDRY_512 0x00000600
146 #define DMA_RWCTRL_READ_BNDRY_1024 0x00000700
147 #define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800
148 #define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000
149 #define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800
150 #define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000
151 #define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800
152 #define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000
153 #define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800
154 #define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000
155 #define DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800
156 #define DMA_RWCTRL_ONE_DMA 0x00004000
157 #define DMA_RWCTRL_READ_WATER 0x00070000
158 #define DMA_RWCTRL_READ_WATER_SHIFT 16
159 #define DMA_RWCTRL_WRITE_WATER 0x00380000
160 #define DMA_RWCTRL_WRITE_WATER_SHIFT 19
161 #define DMA_RWCTRL_USE_MEM_READ_MULT 0x00400000
162 #define DMA_RWCTRL_ASSERT_ALL_BE 0x00800000
163 #define DMA_RWCTRL_PCI_READ_CMD 0x0f000000
164 #define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24
165 #define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000
166 #define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28
167 #define TG3PCI_PCISTATE 0x00000070
168 #define PCISTATE_FORCE_RESET 0x00000001
169 #define PCISTATE_INT_NOT_ACTIVE 0x00000002
170 #define PCISTATE_CONV_PCI_MODE 0x00000004
171 #define PCISTATE_BUS_SPEED_HIGH 0x00000008
172 #define PCISTATE_BUS_32BIT 0x00000010
173 #define PCISTATE_ROM_ENABLE 0x00000020
174 #define PCISTATE_ROM_RETRY_ENABLE 0x00000040
175 #define PCISTATE_FLAT_VIEW 0x00000100
176 #define PCISTATE_RETRY_SAME_DMA 0x00002000
177 #define TG3PCI_CLOCK_CTRL 0x00000074
178 #define CLOCK_CTRL_CORECLK_DISABLE 0x00000200
179 #define CLOCK_CTRL_RXCLK_DISABLE 0x00000400
180 #define CLOCK_CTRL_TXCLK_DISABLE 0x00000800
181 #define CLOCK_CTRL_ALTCLK 0x00001000
182 #define CLOCK_CTRL_PWRDOWN_PLL133 0x00008000
183 #define CLOCK_CTRL_44MHZ_CORE 0x00040000
184 #define CLOCK_CTRL_DELAY_PCI_GRANT 0x80000000
185 #define TG3PCI_REG_BASE_ADDR 0x00000078
186 #define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c
187 #define TG3PCI_REG_DATA 0x00000080
188 #define TG3PCI_MEM_WIN_DATA 0x00000084
189 #define TG3PCI_MODE_CTRL 0x00000088
190 #define TG3PCI_MISC_CFG 0x0000008c
191 #define TG3PCI_MISC_LOCAL_CTRL 0x00000090
192 /* 0x94 --> 0x98 unused */
193 #define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */
194 #define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */
195 #define TG3PCI_SND_PROD_IDX 0x000000a8 /* 64-bit */
196 /* 0xb0 --> 0x100 unused */
198 /* 0x100 --> 0x200 unused */
200 /* Mailbox registers */
201 #define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */
202 #define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */
203 #define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */
204 #define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */
205 #define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */
206 #define MAILBOX_GENERAL_1 0x00000228 /* 64-bit */
207 #define MAILBOX_GENERAL_2 0x00000230 /* 64-bit */
208 #define MAILBOX_GENERAL_3 0x00000238 /* 64-bit */
209 #define MAILBOX_GENERAL_4 0x00000240 /* 64-bit */
210 #define MAILBOX_GENERAL_5 0x00000248 /* 64-bit */
211 #define MAILBOX_GENERAL_6 0x00000250 /* 64-bit */
212 #define MAILBOX_GENERAL_7 0x00000258 /* 64-bit */
213 #define MAILBOX_RELOAD_STAT 0x00000260 /* 64-bit */
214 #define MAILBOX_RCV_STD_PROD_IDX 0x00000268 /* 64-bit */
215 #define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270 /* 64-bit */
216 #define MAILBOX_RCV_MINI_PROD_IDX 0x00000278 /* 64-bit */
217 #define MAILBOX_RCVRET_CON_IDX_0 0x00000280 /* 64-bit */
218 #define MAILBOX_RCVRET_CON_IDX_1 0x00000288 /* 64-bit */
219 #define MAILBOX_RCVRET_CON_IDX_2 0x00000290 /* 64-bit */
220 #define MAILBOX_RCVRET_CON_IDX_3 0x00000298 /* 64-bit */
221 #define MAILBOX_RCVRET_CON_IDX_4 0x000002a0 /* 64-bit */
222 #define MAILBOX_RCVRET_CON_IDX_5 0x000002a8 /* 64-bit */
223 #define MAILBOX_RCVRET_CON_IDX_6 0x000002b0 /* 64-bit */
224 #define MAILBOX_RCVRET_CON_IDX_7 0x000002b8 /* 64-bit */
225 #define MAILBOX_RCVRET_CON_IDX_8 0x000002c0 /* 64-bit */
226 #define MAILBOX_RCVRET_CON_IDX_9 0x000002c8 /* 64-bit */
227 #define MAILBOX_RCVRET_CON_IDX_10 0x000002d0 /* 64-bit */
228 #define MAILBOX_RCVRET_CON_IDX_11 0x000002d8 /* 64-bit */
229 #define MAILBOX_RCVRET_CON_IDX_12 0x000002e0 /* 64-bit */
230 #define MAILBOX_RCVRET_CON_IDX_13 0x000002e8 /* 64-bit */
231 #define MAILBOX_RCVRET_CON_IDX_14 0x000002f0 /* 64-bit */
232 #define MAILBOX_RCVRET_CON_IDX_15 0x000002f8 /* 64-bit */
233 #define MAILBOX_SNDHOST_PROD_IDX_0 0x00000300 /* 64-bit */
234 #define MAILBOX_SNDHOST_PROD_IDX_1 0x00000308 /* 64-bit */
235 #define MAILBOX_SNDHOST_PROD_IDX_2 0x00000310 /* 64-bit */
236 #define MAILBOX_SNDHOST_PROD_IDX_3 0x00000318 /* 64-bit */
237 #define MAILBOX_SNDHOST_PROD_IDX_4 0x00000320 /* 64-bit */
238 #define MAILBOX_SNDHOST_PROD_IDX_5 0x00000328 /* 64-bit */
239 #define MAILBOX_SNDHOST_PROD_IDX_6 0x00000330 /* 64-bit */
240 #define MAILBOX_SNDHOST_PROD_IDX_7 0x00000338 /* 64-bit */
241 #define MAILBOX_SNDHOST_PROD_IDX_8 0x00000340 /* 64-bit */
242 #define MAILBOX_SNDHOST_PROD_IDX_9 0x00000348 /* 64-bit */
243 #define MAILBOX_SNDHOST_PROD_IDX_10 0x00000350 /* 64-bit */
244 #define MAILBOX_SNDHOST_PROD_IDX_11 0x00000358 /* 64-bit */
245 #define MAILBOX_SNDHOST_PROD_IDX_12 0x00000360 /* 64-bit */
246 #define MAILBOX_SNDHOST_PROD_IDX_13 0x00000368 /* 64-bit */
247 #define MAILBOX_SNDHOST_PROD_IDX_14 0x00000370 /* 64-bit */
248 #define MAILBOX_SNDHOST_PROD_IDX_15 0x00000378 /* 64-bit */
249 #define MAILBOX_SNDNIC_PROD_IDX_0 0x00000380 /* 64-bit */
250 #define MAILBOX_SNDNIC_PROD_IDX_1 0x00000388 /* 64-bit */
251 #define MAILBOX_SNDNIC_PROD_IDX_2 0x00000390 /* 64-bit */
252 #define MAILBOX_SNDNIC_PROD_IDX_3 0x00000398 /* 64-bit */
253 #define MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0 /* 64-bit */
254 #define MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8 /* 64-bit */
255 #define MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0 /* 64-bit */
256 #define MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8 /* 64-bit */
257 #define MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0 /* 64-bit */
258 #define MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8 /* 64-bit */
259 #define MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0 /* 64-bit */
260 #define MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8 /* 64-bit */
261 #define MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0 /* 64-bit */
262 #define MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8 /* 64-bit */
263 #define MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0 /* 64-bit */
264 #define MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8 /* 64-bit */
266 /* MAC control registers */
267 #define MAC_MODE 0x00000400
268 #define MAC_MODE_RESET 0x00000001
269 #define MAC_MODE_HALF_DUPLEX 0x00000002
270 #define MAC_MODE_PORT_MODE_MASK 0x0000000c
271 #define MAC_MODE_PORT_MODE_TBI 0x0000000c
272 #define MAC_MODE_PORT_MODE_GMII 0x00000008
273 #define MAC_MODE_PORT_MODE_MII 0x00000004
274 #define MAC_MODE_PORT_MODE_NONE 0x00000000
275 #define MAC_MODE_PORT_INT_LPBACK 0x00000010
276 #define MAC_MODE_TAGGED_MAC_CTRL 0x00000080
277 #define MAC_MODE_TX_BURSTING 0x00000100
278 #define MAC_MODE_MAX_DEFER 0x00000200
279 #define MAC_MODE_LINK_POLARITY 0x00000400
280 #define MAC_MODE_RXSTAT_ENABLE 0x00000800
281 #define MAC_MODE_RXSTAT_CLEAR 0x00001000
282 #define MAC_MODE_RXSTAT_FLUSH 0x00002000
283 #define MAC_MODE_TXSTAT_ENABLE 0x00004000
284 #define MAC_MODE_TXSTAT_CLEAR 0x00008000
285 #define MAC_MODE_TXSTAT_FLUSH 0x00010000
286 #define MAC_MODE_SEND_CONFIGS 0x00020000
287 #define MAC_MODE_MAGIC_PKT_ENABLE 0x00040000
288 #define MAC_MODE_ACPI_ENABLE 0x00080000
289 #define MAC_MODE_MIP_ENABLE 0x00100000
290 #define MAC_MODE_TDE_ENABLE 0x00200000
291 #define MAC_MODE_RDE_ENABLE 0x00400000
292 #define MAC_MODE_FHDE_ENABLE 0x00800000
293 #define MAC_STATUS 0x00000404
294 #define MAC_STATUS_PCS_SYNCED 0x00000001
295 #define MAC_STATUS_SIGNAL_DET 0x00000002
296 #define MAC_STATUS_RCVD_CFG 0x00000004
297 #define MAC_STATUS_CFG_CHANGED 0x00000008
298 #define MAC_STATUS_SYNC_CHANGED 0x00000010
299 #define MAC_STATUS_PORT_DEC_ERR 0x00000400
300 #define MAC_STATUS_LNKSTATE_CHANGED 0x00001000
301 #define MAC_STATUS_MI_COMPLETION 0x00400000
302 #define MAC_STATUS_MI_INTERRUPT 0x00800000
303 #define MAC_STATUS_AP_ERROR 0x01000000
304 #define MAC_STATUS_ODI_ERROR 0x02000000
305 #define MAC_STATUS_RXSTAT_OVERRUN 0x04000000
306 #define MAC_STATUS_TXSTAT_OVERRUN 0x08000000
307 #define MAC_EVENT 0x00000408
308 #define MAC_EVENT_PORT_DECODE_ERR 0x00000400
309 #define MAC_EVENT_LNKSTATE_CHANGED 0x00001000
310 #define MAC_EVENT_MI_COMPLETION 0x00400000
311 #define MAC_EVENT_MI_INTERRUPT 0x00800000
312 #define MAC_EVENT_AP_ERROR 0x01000000
313 #define MAC_EVENT_ODI_ERROR 0x02000000
314 #define MAC_EVENT_RXSTAT_OVERRUN 0x04000000
315 #define MAC_EVENT_TXSTAT_OVERRUN 0x08000000
316 #define MAC_LED_CTRL 0x0000040c
317 #define LED_CTRL_LNKLED_OVERRIDE 0x00000001
318 #define LED_CTRL_1000MBPS_ON 0x00000002
319 #define LED_CTRL_100MBPS_ON 0x00000004
320 #define LED_CTRL_10MBPS_ON 0x00000008
321 #define LED_CTRL_TRAFFIC_OVERRIDE 0x00000010
322 #define LED_CTRL_TRAFFIC_BLINK 0x00000020
323 #define LED_CTRL_TRAFFIC_LED 0x00000040
324 #define LED_CTRL_1000MBPS_STATUS 0x00000080
325 #define LED_CTRL_100MBPS_STATUS 0x00000100
326 #define LED_CTRL_10MBPS_STATUS 0x00000200
327 #define LED_CTRL_TRAFFIC_STATUS 0x00000400
328 #define LED_CTRL_MAC_MODE 0x00000000
329 #define LED_CTRL_PHY_MODE_1 0x00000800
330 #define LED_CTRL_PHY_MODE_2 0x00001000
331 #define LED_CTRL_BLINK_RATE_MASK 0x7ff80000
332 #define LED_CTRL_BLINK_RATE_SHIFT 19
333 #define LED_CTRL_BLINK_PER_OVERRIDE 0x00080000
334 #define LED_CTRL_BLINK_RATE_OVERRIDE 0x80000000
335 #define MAC_ADDR_0_HIGH 0x00000410 /* upper 2 bytes */
336 #define MAC_ADDR_0_LOW 0x00000414 /* lower 4 bytes */
337 #define MAC_ADDR_1_HIGH 0x00000418 /* upper 2 bytes */
338 #define MAC_ADDR_1_LOW 0x0000041c /* lower 4 bytes */
339 #define MAC_ADDR_2_HIGH 0x00000420 /* upper 2 bytes */
340 #define MAC_ADDR_2_LOW 0x00000424 /* lower 4 bytes */
341 #define MAC_ADDR_3_HIGH 0x00000428 /* upper 2 bytes */
342 #define MAC_ADDR_3_LOW 0x0000042c /* lower 4 bytes */
343 #define MAC_ACPI_MBUF_PTR 0x00000430
344 #define MAC_ACPI_LEN_OFFSET 0x00000434
345 #define ACPI_LENOFF_LEN_MASK 0x0000ffff
346 #define ACPI_LENOFF_LEN_SHIFT 0
347 #define ACPI_LENOFF_OFF_MASK 0x0fff0000
348 #define ACPI_LENOFF_OFF_SHIFT 16
349 #define MAC_TX_BACKOFF_SEED 0x00000438
350 #define TX_BACKOFF_SEED_MASK 0x000003ff
351 #define MAC_RX_MTU_SIZE 0x0000043c
352 #define RX_MTU_SIZE_MASK 0x0000ffff
353 #define MAC_PCS_TEST 0x00000440
354 #define PCS_TEST_PATTERN_MASK 0x000fffff
355 #define PCS_TEST_PATTERN_SHIFT 0
356 #define PCS_TEST_ENABLE 0x00100000
357 #define MAC_TX_AUTO_NEG 0x00000444
358 #define TX_AUTO_NEG_MASK 0x0000ffff
359 #define TX_AUTO_NEG_SHIFT 0
360 #define MAC_RX_AUTO_NEG 0x00000448
361 #define RX_AUTO_NEG_MASK 0x0000ffff
362 #define RX_AUTO_NEG_SHIFT 0
363 #define MAC_MI_COM 0x0000044c
364 #define MI_COM_CMD_MASK 0x0c000000
365 #define MI_COM_CMD_WRITE 0x04000000
366 #define MI_COM_CMD_READ 0x08000000
367 #define MI_COM_READ_FAILED 0x10000000
368 #define MI_COM_START 0x20000000
369 #define MI_COM_BUSY 0x20000000
370 #define MI_COM_PHY_ADDR_MASK 0x03e00000
371 #define MI_COM_PHY_ADDR_SHIFT 21
372 #define MI_COM_REG_ADDR_MASK 0x001f0000
373 #define MI_COM_REG_ADDR_SHIFT 16
374 #define MI_COM_DATA_MASK 0x0000ffff
375 #define MAC_MI_STAT 0x00000450
376 #define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001
377 #define MAC_MI_MODE 0x00000454
378 #define MAC_MI_MODE_CLK_10MHZ 0x00000001
379 #define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002
380 #define MAC_MI_MODE_AUTO_POLL 0x00000010
381 #define MAC_MI_MODE_CORE_CLK_62MHZ 0x00008000
382 #define MAC_MI_MODE_BASE 0x000c0000 /* XXX magic values XXX */
383 #define MAC_AUTO_POLL_STATUS 0x00000458
384 #define MAC_AUTO_POLL_ERROR 0x00000001
385 #define MAC_TX_MODE 0x0000045c
386 #define TX_MODE_RESET 0x00000001
387 #define TX_MODE_ENABLE 0x00000002
388 #define TX_MODE_FLOW_CTRL_ENABLE 0x00000010
389 #define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020
390 #define TX_MODE_LONG_PAUSE_ENABLE 0x00000040
391 #define MAC_TX_STATUS 0x00000460
392 #define TX_STATUS_XOFFED 0x00000001
393 #define TX_STATUS_SENT_XOFF 0x00000002
394 #define TX_STATUS_SENT_XON 0x00000004
395 #define TX_STATUS_LINK_UP 0x00000008
396 #define TX_STATUS_ODI_UNDERRUN 0x00000010
397 #define TX_STATUS_ODI_OVERRUN 0x00000020
398 #define MAC_TX_LENGTHS 0x00000464
399 #define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff
400 #define TX_LENGTHS_SLOT_TIME_SHIFT 0
401 #define TX_LENGTHS_IPG_MASK 0x00000f00
402 #define TX_LENGTHS_IPG_SHIFT 8
403 #define TX_LENGTHS_IPG_CRS_MASK 0x00003000
404 #define TX_LENGTHS_IPG_CRS_SHIFT 12
405 #define MAC_RX_MODE 0x00000468
406 #define RX_MODE_RESET 0x00000001
407 #define RX_MODE_ENABLE 0x00000002
408 #define RX_MODE_FLOW_CTRL_ENABLE 0x00000004
409 #define RX_MODE_KEEP_MAC_CTRL 0x00000008
410 #define RX_MODE_KEEP_PAUSE 0x00000010
411 #define RX_MODE_ACCEPT_OVERSIZED 0x00000020
412 #define RX_MODE_ACCEPT_RUNTS 0x00000040
413 #define RX_MODE_LEN_CHECK 0x00000080
414 #define RX_MODE_PROMISC 0x00000100
415 #define RX_MODE_NO_CRC_CHECK 0x00000200
416 #define RX_MODE_KEEP_VLAN_TAG 0x00000400
417 #define MAC_RX_STATUS 0x0000046c
418 #define RX_STATUS_REMOTE_TX_XOFFED 0x00000001
419 #define RX_STATUS_XOFF_RCVD 0x00000002
420 #define RX_STATUS_XON_RCVD 0x00000004
421 #define MAC_HASH_REG_0 0x00000470
422 #define MAC_HASH_REG_1 0x00000474
423 #define MAC_HASH_REG_2 0x00000478
424 #define MAC_HASH_REG_3 0x0000047c
425 #define MAC_RCV_RULE_0 0x00000480
426 #define MAC_RCV_VALUE_0 0x00000484
427 #define MAC_RCV_RULE_1 0x00000488
428 #define MAC_RCV_VALUE_1 0x0000048c
429 #define MAC_RCV_RULE_2 0x00000490
430 #define MAC_RCV_VALUE_2 0x00000494
431 #define MAC_RCV_RULE_3 0x00000498
432 #define MAC_RCV_VALUE_3 0x0000049c
433 #define MAC_RCV_RULE_4 0x000004a0
434 #define MAC_RCV_VALUE_4 0x000004a4
435 #define MAC_RCV_RULE_5 0x000004a8
436 #define MAC_RCV_VALUE_5 0x000004ac
437 #define MAC_RCV_RULE_6 0x000004b0
438 #define MAC_RCV_VALUE_6 0x000004b4
439 #define MAC_RCV_RULE_7 0x000004b8
440 #define MAC_RCV_VALUE_7 0x000004bc
441 #define MAC_RCV_RULE_8 0x000004c0
442 #define MAC_RCV_VALUE_8 0x000004c4
443 #define MAC_RCV_RULE_9 0x000004c8
444 #define MAC_RCV_VALUE_9 0x000004cc
445 #define MAC_RCV_RULE_10 0x000004d0
446 #define MAC_RCV_VALUE_10 0x000004d4
447 #define MAC_RCV_RULE_11 0x000004d8
448 #define MAC_RCV_VALUE_11 0x000004dc
449 #define MAC_RCV_RULE_12 0x000004e0
450 #define MAC_RCV_VALUE_12 0x000004e4
451 #define MAC_RCV_RULE_13 0x000004e8
452 #define MAC_RCV_VALUE_13 0x000004ec
453 #define MAC_RCV_RULE_14 0x000004f0
454 #define MAC_RCV_VALUE_14 0x000004f4
455 #define MAC_RCV_RULE_15 0x000004f8
456 #define MAC_RCV_VALUE_15 0x000004fc
457 #define RCV_RULE_DISABLE_MASK 0x7fffffff
458 #define MAC_RCV_RULE_CFG 0x00000500
459 #define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008
460 #define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504
461 /* 0x504 --> 0x590 unused */
462 #define MAC_SERDES_CFG 0x00000590
463 #define MAC_SERDES_STAT 0x00000594
464 /* 0x598 --> 0x600 unused */
465 #define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */
466 #define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */
467 /* 0x624 --> 0x800 unused */
468 #define MAC_RX_STATS_BASE 0x00000800 /* 26 32-bit words */
469 /* 0x868 --> 0x880 unused */
470 #define MAC_TX_STATS_BASE 0x00000880 /* 28 32-bit words */
471 /* 0x8f0 --> 0xc00 unused */
473 /* Send data initiator control registers */
474 #define SNDDATAI_MODE 0x00000c00
475 #define SNDDATAI_MODE_RESET 0x00000001
476 #define SNDDATAI_MODE_ENABLE 0x00000002
477 #define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004
478 #define SNDDATAI_STATUS 0x00000c04
479 #define SNDDATAI_STATUS_STAT_OFLOW 0x00000004
480 #define SNDDATAI_STATSCTRL 0x00000c08
481 #define SNDDATAI_SCTRL_ENABLE 0x00000001
482 #define SNDDATAI_SCTRL_FASTUPD 0x00000002
483 #define SNDDATAI_SCTRL_CLEAR 0x00000004
484 #define SNDDATAI_SCTRL_FLUSH 0x00000008
485 #define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010
486 #define SNDDATAI_STATSENAB 0x00000c0c
487 #define SNDDATAI_STATSINCMASK 0x00000c10
488 /* 0xc14 --> 0xc80 unused */
489 #define SNDDATAI_COS_CNT_0 0x00000c80
490 #define SNDDATAI_COS_CNT_1 0x00000c84
491 #define SNDDATAI_COS_CNT_2 0x00000c88
492 #define SNDDATAI_COS_CNT_3 0x00000c8c
493 #define SNDDATAI_COS_CNT_4 0x00000c90
494 #define SNDDATAI_COS_CNT_5 0x00000c94
495 #define SNDDATAI_COS_CNT_6 0x00000c98
496 #define SNDDATAI_COS_CNT_7 0x00000c9c
497 #define SNDDATAI_COS_CNT_8 0x00000ca0
498 #define SNDDATAI_COS_CNT_9 0x00000ca4
499 #define SNDDATAI_COS_CNT_10 0x00000ca8
500 #define SNDDATAI_COS_CNT_11 0x00000cac
501 #define SNDDATAI_COS_CNT_12 0x00000cb0
502 #define SNDDATAI_COS_CNT_13 0x00000cb4
503 #define SNDDATAI_COS_CNT_14 0x00000cb8
504 #define SNDDATAI_COS_CNT_15 0x00000cbc
505 #define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0
506 #define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4
507 #define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8
508 #define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc
509 #define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0
510 #define SNDDATAI_INTERRUPTS_CNT 0x00000cd4
511 #define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8
512 #define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc
513 /* 0xce0 --> 0x1000 unused */
515 /* Send data completion control registers */
516 #define SNDDATAC_MODE 0x00001000
517 #define SNDDATAC_MODE_RESET 0x00000001
518 #define SNDDATAC_MODE_ENABLE 0x00000002
519 /* 0x1004 --> 0x1400 unused */
521 /* Send BD ring selector */
522 #define SNDBDS_MODE 0x00001400
523 #define SNDBDS_MODE_RESET 0x00000001
524 #define SNDBDS_MODE_ENABLE 0x00000002
525 #define SNDBDS_MODE_ATTN_ENABLE 0x00000004
526 #define SNDBDS_STATUS 0x00001404
527 #define SNDBDS_STATUS_ERROR_ATTN 0x00000004
528 #define SNDBDS_HWDIAG 0x00001408
529 /* 0x140c --> 0x1440 */
530 #define SNDBDS_SEL_CON_IDX_0 0x00001440
531 #define SNDBDS_SEL_CON_IDX_1 0x00001444
532 #define SNDBDS_SEL_CON_IDX_2 0x00001448
533 #define SNDBDS_SEL_CON_IDX_3 0x0000144c
534 #define SNDBDS_SEL_CON_IDX_4 0x00001450
535 #define SNDBDS_SEL_CON_IDX_5 0x00001454
536 #define SNDBDS_SEL_CON_IDX_6 0x00001458
537 #define SNDBDS_SEL_CON_IDX_7 0x0000145c
538 #define SNDBDS_SEL_CON_IDX_8 0x00001460
539 #define SNDBDS_SEL_CON_IDX_9 0x00001464
540 #define SNDBDS_SEL_CON_IDX_10 0x00001468
541 #define SNDBDS_SEL_CON_IDX_11 0x0000146c
542 #define SNDBDS_SEL_CON_IDX_12 0x00001470
543 #define SNDBDS_SEL_CON_IDX_13 0x00001474
544 #define SNDBDS_SEL_CON_IDX_14 0x00001478
545 #define SNDBDS_SEL_CON_IDX_15 0x0000147c
546 /* 0x1480 --> 0x1800 unused */
548 /* Send BD initiator control registers */
549 #define SNDBDI_MODE 0x00001800
550 #define SNDBDI_MODE_RESET 0x00000001
551 #define SNDBDI_MODE_ENABLE 0x00000002
552 #define SNDBDI_MODE_ATTN_ENABLE 0x00000004
553 #define SNDBDI_STATUS 0x00001804
554 #define SNDBDI_STATUS_ERROR_ATTN 0x00000004
555 #define SNDBDI_IN_PROD_IDX_0 0x00001808
556 #define SNDBDI_IN_PROD_IDX_1 0x0000180c
557 #define SNDBDI_IN_PROD_IDX_2 0x00001810
558 #define SNDBDI_IN_PROD_IDX_3 0x00001814
559 #define SNDBDI_IN_PROD_IDX_4 0x00001818
560 #define SNDBDI_IN_PROD_IDX_5 0x0000181c
561 #define SNDBDI_IN_PROD_IDX_6 0x00001820
562 #define SNDBDI_IN_PROD_IDX_7 0x00001824
563 #define SNDBDI_IN_PROD_IDX_8 0x00001828
564 #define SNDBDI_IN_PROD_IDX_9 0x0000182c
565 #define SNDBDI_IN_PROD_IDX_10 0x00001830
566 #define SNDBDI_IN_PROD_IDX_11 0x00001834
567 #define SNDBDI_IN_PROD_IDX_12 0x00001838
568 #define SNDBDI_IN_PROD_IDX_13 0x0000183c
569 #define SNDBDI_IN_PROD_IDX_14 0x00001840
570 #define SNDBDI_IN_PROD_IDX_15 0x00001844
571 /* 0x1848 --> 0x1c00 unused */
573 /* Send BD completion control registers */
574 #define SNDBDC_MODE 0x00001c00
575 #define SNDBDC_MODE_RESET 0x00000001
576 #define SNDBDC_MODE_ENABLE 0x00000002
577 #define SNDBDC_MODE_ATTN_ENABLE 0x00000004
578 /* 0x1c04 --> 0x2000 unused */
580 /* Receive list placement control registers */
581 #define RCVLPC_MODE 0x00002000
582 #define RCVLPC_MODE_RESET 0x00000001
583 #define RCVLPC_MODE_ENABLE 0x00000002
584 #define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004
585 #define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008
586 #define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010
587 #define RCVLPC_STATUS 0x00002004
588 #define RCVLPC_STATUS_CLASS0 0x00000004
589 #define RCVLPC_STATUS_MAPOOR 0x00000008
590 #define RCVLPC_STATUS_STAT_OFLOW 0x00000010
591 #define RCVLPC_LOCK 0x00002008
592 #define RCVLPC_LOCK_REQ_MASK 0x0000ffff
593 #define RCVLPC_LOCK_REQ_SHIFT 0
594 #define RCVLPC_LOCK_GRANT_MASK 0xffff0000
595 #define RCVLPC_LOCK_GRANT_SHIFT 16
596 #define RCVLPC_NON_EMPTY_BITS 0x0000200c
597 #define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff
598 #define RCVLPC_CONFIG 0x00002010
599 #define RCVLPC_STATSCTRL 0x00002014
600 #define RCVLPC_STATSCTRL_ENABLE 0x00000001
601 #define RCVLPC_STATSCTRL_FASTUPD 0x00000002
602 #define RCVLPC_STATS_ENABLE 0x00002018
603 #define RCVLPC_STATS_INCMASK 0x0000201c
604 /* 0x2020 --> 0x2100 unused */
605 #define RCVLPC_SELLST_BASE 0x00002100 /* 16 16-byte entries */
606 #define SELLST_TAIL 0x00000004
607 #define SELLST_CONT 0x00000008
608 #define SELLST_UNUSED 0x0000000c
609 #define RCVLPC_COS_CNTL_BASE 0x00002200 /* 16 4-byte entries */
610 #define RCVLPC_DROP_FILTER_CNT 0x00002240
611 #define RCVLPC_DMA_WQ_FULL_CNT 0x00002244
612 #define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248
613 #define RCVLPC_NO_RCV_BD_CNT 0x0000224c
614 #define RCVLPC_IN_DISCARDS_CNT 0x00002250
615 #define RCVLPC_IN_ERRORS_CNT 0x00002254
616 #define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258
617 /* 0x225c --> 0x2400 unused */
619 /* Receive Data and Receive BD Initiator Control */
620 #define RCVDBDI_MODE 0x00002400
621 #define RCVDBDI_MODE_RESET 0x00000001
622 #define RCVDBDI_MODE_ENABLE 0x00000002
623 #define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004
624 #define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008
625 #define RCVDBDI_MODE_INV_RING_SZ 0x00000010
626 #define RCVDBDI_STATUS 0x00002404
627 #define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004
628 #define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008
629 #define RCVDBDI_STATUS_INV_RING_SZ 0x00000010
630 #define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408
631 /* 0x240c --> 0x2440 unused */
632 #define RCVDBDI_JUMBO_BD 0x00002440 /* TG3_BDINFO_... */
633 #define RCVDBDI_STD_BD 0x00002450 /* TG3_BDINFO_... */
634 #define RCVDBDI_MINI_BD 0x00002460 /* TG3_BDINFO_... */
635 #define RCVDBDI_JUMBO_CON_IDX 0x00002470
636 #define RCVDBDI_STD_CON_IDX 0x00002474
637 #define RCVDBDI_MINI_CON_IDX 0x00002478
638 /* 0x247c --> 0x2480 unused */
639 #define RCVDBDI_BD_PROD_IDX_0 0x00002480
640 #define RCVDBDI_BD_PROD_IDX_1 0x00002484
641 #define RCVDBDI_BD_PROD_IDX_2 0x00002488
642 #define RCVDBDI_BD_PROD_IDX_3 0x0000248c
643 #define RCVDBDI_BD_PROD_IDX_4 0x00002490
644 #define RCVDBDI_BD_PROD_IDX_5 0x00002494
645 #define RCVDBDI_BD_PROD_IDX_6 0x00002498
646 #define RCVDBDI_BD_PROD_IDX_7 0x0000249c
647 #define RCVDBDI_BD_PROD_IDX_8 0x000024a0
648 #define RCVDBDI_BD_PROD_IDX_9 0x000024a4
649 #define RCVDBDI_BD_PROD_IDX_10 0x000024a8
650 #define RCVDBDI_BD_PROD_IDX_11 0x000024ac
651 #define RCVDBDI_BD_PROD_IDX_12 0x000024b0
652 #define RCVDBDI_BD_PROD_IDX_13 0x000024b4
653 #define RCVDBDI_BD_PROD_IDX_14 0x000024b8
654 #define RCVDBDI_BD_PROD_IDX_15 0x000024bc
655 #define RCVDBDI_HWDIAG 0x000024c0
656 /* 0x24c4 --> 0x2800 unused */
658 /* Receive Data Completion Control */
659 #define RCVDCC_MODE 0x00002800
660 #define RCVDCC_MODE_RESET 0x00000001
661 #define RCVDCC_MODE_ENABLE 0x00000002
662 #define RCVDCC_MODE_ATTN_ENABLE 0x00000004
663 /* 0x2804 --> 0x2c00 unused */
665 /* Receive BD Initiator Control Registers */
666 #define RCVBDI_MODE 0x00002c00
667 #define RCVBDI_MODE_RESET 0x00000001
668 #define RCVBDI_MODE_ENABLE 0x00000002
669 #define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004
670 #define RCVBDI_STATUS 0x00002c04
671 #define RCVBDI_STATUS_RCB_ATTN 0x00000004
672 #define RCVBDI_JUMBO_PROD_IDX 0x00002c08
673 #define RCVBDI_STD_PROD_IDX 0x00002c0c
674 #define RCVBDI_MINI_PROD_IDX 0x00002c10
675 #define RCVBDI_MINI_THRESH 0x00002c14
676 #define RCVBDI_STD_THRESH 0x00002c18
677 #define RCVBDI_JUMBO_THRESH 0x00002c1c
678 /* 0x2c20 --> 0x3000 unused */
680 /* Receive BD Completion Control Registers */
681 #define RCVCC_MODE 0x00003000
682 #define RCVCC_MODE_RESET 0x00000001
683 #define RCVCC_MODE_ENABLE 0x00000002
684 #define RCVCC_MODE_ATTN_ENABLE 0x00000004
685 #define RCVCC_STATUS 0x00003004
686 #define RCVCC_STATUS_ERROR_ATTN 0x00000004
687 #define RCVCC_JUMP_PROD_IDX 0x00003008
688 #define RCVCC_STD_PROD_IDX 0x0000300c
689 #define RCVCC_MINI_PROD_IDX 0x00003010
690 /* 0x3014 --> 0x3400 unused */
692 /* Receive list selector control registers */
693 #define RCVLSC_MODE 0x00003400
694 #define RCVLSC_MODE_RESET 0x00000001
695 #define RCVLSC_MODE_ENABLE 0x00000002
696 #define RCVLSC_MODE_ATTN_ENABLE 0x00000004
697 #define RCVLSC_STATUS 0x00003404
698 #define RCVLSC_STATUS_ERROR_ATTN 0x00000004
699 /* 0x3408 --> 0x3800 unused */
701 /* Mbuf cluster free registers */
702 #define MBFREE_MODE 0x00003800
703 #define MBFREE_MODE_RESET 0x00000001
704 #define MBFREE_MODE_ENABLE 0x00000002
705 #define MBFREE_STATUS 0x00003804
706 /* 0x3808 --> 0x3c00 unused */
708 /* Host coalescing control registers */
709 #define HOSTCC_MODE 0x00003c00
710 #define HOSTCC_MODE_RESET 0x00000001
711 #define HOSTCC_MODE_ENABLE 0x00000002
712 #define HOSTCC_MODE_ATTN 0x00000004
713 #define HOSTCC_MODE_NOW 0x00000008
714 #define HOSTCC_MODE_FULL_STATUS 0x00000000
715 #define HOSTCC_MODE_64BYTE 0x00000080
716 #define HOSTCC_MODE_32BYTE 0x00000100
717 #define HOSTCC_MODE_CLRTICK_RXBD 0x00000200
718 #define HOSTCC_MODE_CLRTICK_TXBD 0x00000400
719 #define HOSTCC_MODE_NOINT_ON_NOW 0x00000800
720 #define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000
721 #define HOSTCC_STATUS 0x00003c04
722 #define HOSTCC_STATUS_ERROR_ATTN 0x00000004
723 #define HOSTCC_RXCOL_TICKS 0x00003c08
724 #define LOW_RXCOL_TICKS 0x00000032
725 #define DEFAULT_RXCOL_TICKS 0x00000048
726 #define HIGH_RXCOL_TICKS 0x00000096
727 #define HOSTCC_TXCOL_TICKS 0x00003c0c
728 #define LOW_TXCOL_TICKS 0x00000096
729 #define DEFAULT_TXCOL_TICKS 0x0000012c
730 #define HIGH_TXCOL_TICKS 0x00000145
731 #define HOSTCC_RXMAX_FRAMES 0x00003c10
732 #define LOW_RXMAX_FRAMES 0x00000005
733 #define DEFAULT_RXMAX_FRAMES 0x00000008
734 #define HIGH_RXMAX_FRAMES 0x00000012
735 #define HOSTCC_TXMAX_FRAMES 0x00003c14
736 #define LOW_TXMAX_FRAMES 0x00000035
737 #define DEFAULT_TXMAX_FRAMES 0x0000004b
738 #define HIGH_TXMAX_FRAMES 0x00000052
739 #define HOSTCC_RXCOAL_TICK_INT 0x00003c18
740 #define DEFAULT_RXCOAL_TICK_INT 0x00000019
741 #define HOSTCC_TXCOAL_TICK_INT 0x00003c1c
742 #define DEFAULT_TXCOAL_TICK_INT 0x00000019
743 #define HOSTCC_RXCOAL_MAXF_INT 0x00003c20
744 #define DEFAULT_RXCOAL_MAXF_INT 0x00000005
745 #define HOSTCC_TXCOAL_MAXF_INT 0x00003c24
746 #define DEFAULT_TXCOAL_MAXF_INT 0x00000005
747 #define HOSTCC_STAT_COAL_TICKS 0x00003c28
748 #define DEFAULT_STAT_COAL_TICKS 0x000f4240
749 /* 0x3c2c --> 0x3c30 unused */
750 #define HOSTCC_STATS_BLK_HOST_ADDR 0x00003c30 /* 64-bit */
751 #define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */
752 #define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40
753 #define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44
754 #define HOSTCC_FLOW_ATTN 0x00003c48
755 /* 0x3c4c --> 0x3c50 unused */
756 #define HOSTCC_JUMBO_CON_IDX 0x00003c50
757 #define HOSTCC_STD_CON_IDX 0x00003c54
758 #define HOSTCC_MINI_CON_IDX 0x00003c58
759 /* 0x3c5c --> 0x3c80 unused */
760 #define HOSTCC_RET_PROD_IDX_0 0x00003c80
761 #define HOSTCC_RET_PROD_IDX_1 0x00003c84
762 #define HOSTCC_RET_PROD_IDX_2 0x00003c88
763 #define HOSTCC_RET_PROD_IDX_3 0x00003c8c
764 #define HOSTCC_RET_PROD_IDX_4 0x00003c90
765 #define HOSTCC_RET_PROD_IDX_5 0x00003c94
766 #define HOSTCC_RET_PROD_IDX_6 0x00003c98
767 #define HOSTCC_RET_PROD_IDX_7 0x00003c9c
768 #define HOSTCC_RET_PROD_IDX_8 0x00003ca0
769 #define HOSTCC_RET_PROD_IDX_9 0x00003ca4
770 #define HOSTCC_RET_PROD_IDX_10 0x00003ca8
771 #define HOSTCC_RET_PROD_IDX_11 0x00003cac
772 #define HOSTCC_RET_PROD_IDX_12 0x00003cb0
773 #define HOSTCC_RET_PROD_IDX_13 0x00003cb4
774 #define HOSTCC_RET_PROD_IDX_14 0x00003cb8
775 #define HOSTCC_RET_PROD_IDX_15 0x00003cbc
776 #define HOSTCC_SND_CON_IDX_0 0x00003cc0
777 #define HOSTCC_SND_CON_IDX_1 0x00003cc4
778 #define HOSTCC_SND_CON_IDX_2 0x00003cc8
779 #define HOSTCC_SND_CON_IDX_3 0x00003ccc
780 #define HOSTCC_SND_CON_IDX_4 0x00003cd0
781 #define HOSTCC_SND_CON_IDX_5 0x00003cd4
782 #define HOSTCC_SND_CON_IDX_6 0x00003cd8
783 #define HOSTCC_SND_CON_IDX_7 0x00003cdc
784 #define HOSTCC_SND_CON_IDX_8 0x00003ce0
785 #define HOSTCC_SND_CON_IDX_9 0x00003ce4
786 #define HOSTCC_SND_CON_IDX_10 0x00003ce8
787 #define HOSTCC_SND_CON_IDX_11 0x00003cec
788 #define HOSTCC_SND_CON_IDX_12 0x00003cf0
789 #define HOSTCC_SND_CON_IDX_13 0x00003cf4
790 #define HOSTCC_SND_CON_IDX_14 0x00003cf8
791 #define HOSTCC_SND_CON_IDX_15 0x00003cfc
792 /* 0x3d00 --> 0x4000 unused */
794 /* Memory arbiter control registers */
795 #define MEMARB_MODE 0x00004000
796 #define MEMARB_MODE_RESET 0x00000001
797 #define MEMARB_MODE_ENABLE 0x00000002
798 #define MEMARB_STATUS 0x00004004
799 #define MEMARB_TRAP_ADDR_LOW 0x00004008
800 #define MEMARB_TRAP_ADDR_HIGH 0x0000400c
801 /* 0x4010 --> 0x4400 unused */
803 /* Buffer manager control registers */
804 #define BUFMGR_MODE 0x00004400
805 #define BUFMGR_MODE_RESET 0x00000001
806 #define BUFMGR_MODE_ENABLE 0x00000002
807 #define BUFMGR_MODE_ATTN_ENABLE 0x00000004
808 #define BUFMGR_MODE_BM_TEST 0x00000008
809 #define BUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010
810 #define BUFMGR_STATUS 0x00004404
811 #define BUFMGR_STATUS_ERROR 0x00000004
812 #define BUFMGR_STATUS_MBLOW 0x00000010
813 #define BUFMGR_MB_POOL_ADDR 0x00004408
814 #define BUFMGR_MB_POOL_SIZE 0x0000440c
815 #define BUFMGR_MB_RDMA_LOW_WATER 0x00004410
816 #define DEFAULT_MB_RDMA_LOW_WATER 0x00000040
817 #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
818 #define BUFMGR_MB_MACRX_LOW_WATER 0x00004414
819 #define DEFAULT_MB_MACRX_LOW_WATER 0x00000020
820 #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
821 #define BUFMGR_MB_HIGH_WATER 0x00004418
822 #define DEFAULT_MB_HIGH_WATER 0x00000060
823 #define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c
824 #define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c
825 #define BUFMGR_MB_ALLOC_BIT 0x10000000
826 #define BUFMGR_RX_MB_ALLOC_RESP 0x00004420
827 #define BUFMGR_TX_MB_ALLOC_REQ 0x00004424
828 #define BUFMGR_TX_MB_ALLOC_RESP 0x00004428
829 #define BUFMGR_DMA_DESC_POOL_ADDR 0x0000442c
830 #define BUFMGR_DMA_DESC_POOL_SIZE 0x00004430
831 #define BUFMGR_DMA_LOW_WATER 0x00004434
832 #define DEFAULT_DMA_LOW_WATER 0x00000005
833 #define BUFMGR_DMA_HIGH_WATER 0x00004438
834 #define DEFAULT_DMA_HIGH_WATER 0x0000000a
835 #define BUFMGR_RX_DMA_ALLOC_REQ 0x0000443c
836 #define BUFMGR_RX_DMA_ALLOC_RESP 0x00004440
837 #define BUFMGR_TX_DMA_ALLOC_REQ 0x00004444
838 #define BUFMGR_TX_DMA_ALLOC_RESP 0x00004448
839 #define BUFMGR_HWDIAG_0 0x0000444c
840 #define BUFMGR_HWDIAG_1 0x00004450
841 #define BUFMGR_HWDIAG_2 0x00004454
842 /* 0x4458 --> 0x4800 unused */
844 /* Read DMA control registers */
845 #define RDMAC_MODE 0x00004800
846 #define RDMAC_MODE_RESET 0x00000001
847 #define RDMAC_MODE_ENABLE 0x00000002
848 #define RDMAC_MODE_TGTABORT_ENAB 0x00000004
849 #define RDMAC_MODE_MSTABORT_ENAB 0x00000008
850 #define RDMAC_MODE_PARITYERR_ENAB 0x00000010
851 #define RDMAC_MODE_ADDROFLOW_ENAB 0x00000020
852 #define RDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
853 #define RDMAC_MODE_FIFOURUN_ENAB 0x00000080
854 #define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100
855 #define RDMAC_MODE_LNGREAD_ENAB 0x00000200
856 #define RDMAC_MODE_SPLIT_ENABLE 0x00000800
857 #define RDMAC_MODE_SPLIT_RESET 0x00001000
858 #define RDMAC_STATUS 0x00004804
859 #define RDMAC_STATUS_TGTABORT 0x00000004
860 #define RDMAC_STATUS_MSTABORT 0x00000008
861 #define RDMAC_STATUS_PARITYERR 0x00000010
862 #define RDMAC_STATUS_ADDROFLOW 0x00000020
863 #define RDMAC_STATUS_FIFOOFLOW 0x00000040
864 #define RDMAC_STATUS_FIFOURUN 0x00000080
865 #define RDMAC_STATUS_FIFOOREAD 0x00000100
866 #define RDMAC_STATUS_LNGREAD 0x00000200
867 /* 0x4808 --> 0x4c00 unused */
869 /* Write DMA control registers */
870 #define WDMAC_MODE 0x00004c00
871 #define WDMAC_MODE_RESET 0x00000001
872 #define WDMAC_MODE_ENABLE 0x00000002
873 #define WDMAC_MODE_TGTABORT_ENAB 0x00000004
874 #define WDMAC_MODE_MSTABORT_ENAB 0x00000008
875 #define WDMAC_MODE_PARITYERR_ENAB 0x00000010
876 #define WDMAC_MODE_ADDROFLOW_ENAB 0x00000020
877 #define WDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
878 #define WDMAC_MODE_FIFOURUN_ENAB 0x00000080
879 #define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100
880 #define WDMAC_MODE_LNGREAD_ENAB 0x00000200
881 #define WDMAC_STATUS 0x00004c04
882 #define WDMAC_STATUS_TGTABORT 0x00000004
883 #define WDMAC_STATUS_MSTABORT 0x00000008
884 #define WDMAC_STATUS_PARITYERR 0x00000010
885 #define WDMAC_STATUS_ADDROFLOW 0x00000020
886 #define WDMAC_STATUS_FIFOOFLOW 0x00000040
887 #define WDMAC_STATUS_FIFOURUN 0x00000080
888 #define WDMAC_STATUS_FIFOOREAD 0x00000100
889 #define WDMAC_STATUS_LNGREAD 0x00000200
890 /* 0x4c08 --> 0x5000 unused */
892 /* Per-cpu register offsets (arm9) */
893 #define CPU_MODE 0x00000000
894 #define CPU_MODE_RESET 0x00000001
895 #define CPU_MODE_HALT 0x00000400
896 #define CPU_STATE 0x00000004
897 #define CPU_EVTMASK 0x00000008
898 /* 0xc --> 0x1c reserved */
899 #define CPU_PC 0x0000001c
900 #define CPU_INSN 0x00000020
901 #define CPU_SPAD_UFLOW 0x00000024
902 #define CPU_WDOG_CLEAR 0x00000028
903 #define CPU_WDOG_VECTOR 0x0000002c
904 #define CPU_WDOG_PC 0x00000030
905 #define CPU_HW_BP 0x00000034
906 /* 0x38 --> 0x44 unused */
907 #define CPU_WDOG_SAVED_STATE 0x00000044
908 #define CPU_LAST_BRANCH_ADDR 0x00000048
909 #define CPU_SPAD_UFLOW_SET 0x0000004c
910 /* 0x50 --> 0x200 unused */
911 #define CPU_R0 0x00000200
912 #define CPU_R1 0x00000204
913 #define CPU_R2 0x00000208
914 #define CPU_R3 0x0000020c
915 #define CPU_R4 0x00000210
916 #define CPU_R5 0x00000214
917 #define CPU_R6 0x00000218
918 #define CPU_R7 0x0000021c
919 #define CPU_R8 0x00000220
920 #define CPU_R9 0x00000224
921 #define CPU_R10 0x00000228
922 #define CPU_R11 0x0000022c
923 #define CPU_R12 0x00000230
924 #define CPU_R13 0x00000234
925 #define CPU_R14 0x00000238
926 #define CPU_R15 0x0000023c
927 #define CPU_R16 0x00000240
928 #define CPU_R17 0x00000244
929 #define CPU_R18 0x00000248
930 #define CPU_R19 0x0000024c
931 #define CPU_R20 0x00000250
932 #define CPU_R21 0x00000254
933 #define CPU_R22 0x00000258
934 #define CPU_R23 0x0000025c
935 #define CPU_R24 0x00000260
936 #define CPU_R25 0x00000264
937 #define CPU_R26 0x00000268
938 #define CPU_R27 0x0000026c
939 #define CPU_R28 0x00000270
940 #define CPU_R29 0x00000274
941 #define CPU_R30 0x00000278
942 #define CPU_R31 0x0000027c
943 /* 0x280 --> 0x400 unused */
945 #define RX_CPU_BASE 0x00005000
946 #define TX_CPU_BASE 0x00005400
948 /* Mailboxes */
949 #define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */
950 #define GRCMBOX_INTERRUPT_1 0x00005808 /* 64-bit */
951 #define GRCMBOX_INTERRUPT_2 0x00005810 /* 64-bit */
952 #define GRCMBOX_INTERRUPT_3 0x00005818 /* 64-bit */
953 #define GRCMBOX_GENERAL_0 0x00005820 /* 64-bit */
954 #define GRCMBOX_GENERAL_1 0x00005828 /* 64-bit */
955 #define GRCMBOX_GENERAL_2 0x00005830 /* 64-bit */
956 #define GRCMBOX_GENERAL_3 0x00005838 /* 64-bit */
957 #define GRCMBOX_GENERAL_4 0x00005840 /* 64-bit */
958 #define GRCMBOX_GENERAL_5 0x00005848 /* 64-bit */
959 #define GRCMBOX_GENERAL_6 0x00005850 /* 64-bit */
960 #define GRCMBOX_GENERAL_7 0x00005858 /* 64-bit */
961 #define GRCMBOX_RELOAD_STAT 0x00005860 /* 64-bit */
962 #define GRCMBOX_RCVSTD_PROD_IDX 0x00005868 /* 64-bit */
963 #define GRCMBOX_RCVJUMBO_PROD_IDX 0x00005870 /* 64-bit */
964 #define GRCMBOX_RCVMINI_PROD_IDX 0x00005878 /* 64-bit */
965 #define GRCMBOX_RCVRET_CON_IDX_0 0x00005880 /* 64-bit */
966 #define GRCMBOX_RCVRET_CON_IDX_1 0x00005888 /* 64-bit */
967 #define GRCMBOX_RCVRET_CON_IDX_2 0x00005890 /* 64-bit */
968 #define GRCMBOX_RCVRET_CON_IDX_3 0x00005898 /* 64-bit */
969 #define GRCMBOX_RCVRET_CON_IDX_4 0x000058a0 /* 64-bit */
970 #define GRCMBOX_RCVRET_CON_IDX_5 0x000058a8 /* 64-bit */
971 #define GRCMBOX_RCVRET_CON_IDX_6 0x000058b0 /* 64-bit */
972 #define GRCMBOX_RCVRET_CON_IDX_7 0x000058b8 /* 64-bit */
973 #define GRCMBOX_RCVRET_CON_IDX_8 0x000058c0 /* 64-bit */
974 #define GRCMBOX_RCVRET_CON_IDX_9 0x000058c8 /* 64-bit */
975 #define GRCMBOX_RCVRET_CON_IDX_10 0x000058d0 /* 64-bit */
976 #define GRCMBOX_RCVRET_CON_IDX_11 0x000058d8 /* 64-bit */
977 #define GRCMBOX_RCVRET_CON_IDX_12 0x000058e0 /* 64-bit */
978 #define GRCMBOX_RCVRET_CON_IDX_13 0x000058e8 /* 64-bit */
979 #define GRCMBOX_RCVRET_CON_IDX_14 0x000058f0 /* 64-bit */
980 #define GRCMBOX_RCVRET_CON_IDX_15 0x000058f8 /* 64-bit */
981 #define GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900 /* 64-bit */
982 #define GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908 /* 64-bit */
983 #define GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910 /* 64-bit */
984 #define GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918 /* 64-bit */
985 #define GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920 /* 64-bit */
986 #define GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928 /* 64-bit */
987 #define GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930 /* 64-bit */
988 #define GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938 /* 64-bit */
989 #define GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940 /* 64-bit */
990 #define GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948 /* 64-bit */
991 #define GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950 /* 64-bit */
992 #define GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958 /* 64-bit */
993 #define GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960 /* 64-bit */
994 #define GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968 /* 64-bit */
995 #define GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970 /* 64-bit */
996 #define GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978 /* 64-bit */
997 #define GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980 /* 64-bit */
998 #define GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988 /* 64-bit */
999 #define GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990 /* 64-bit */
1000 #define GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998 /* 64-bit */
1001 #define GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0 /* 64-bit */
1002 #define GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8 /* 64-bit */
1003 #define GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0 /* 64-bit */
1004 #define GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8 /* 64-bit */
1005 #define GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0 /* 64-bit */
1006 #define GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8 /* 64-bit */
1007 #define GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0 /* 64-bit */
1008 #define GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8 /* 64-bit */
1009 #define GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0 /* 64-bit */
1010 #define GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8 /* 64-bit */
1011 #define GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0 /* 64-bit */
1012 #define GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8 /* 64-bit */
1013 #define GRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00
1014 #define GRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04
1015 #define GRCMBOX_LOW_PRIO_EV_VEC 0x00005a08
1016 #define GRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c
1017 /* 0x5a10 --> 0x5c00 */
1019 /* Flow Through queues */
1020 #define FTQ_RESET 0x00005c00
1021 /* 0x5c04 --> 0x5c10 unused */
1022 #define FTQ_DMA_NORM_READ_CTL 0x00005c10
1023 #define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14
1024 #define FTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18
1025 #define FTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c
1026 #define FTQ_DMA_HIGH_READ_CTL 0x00005c20
1027 #define FTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24
1028 #define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28
1029 #define FTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c
1030 #define FTQ_DMA_COMP_DISC_CTL 0x00005c30
1031 #define FTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34
1032 #define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38
1033 #define FTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c
1034 #define FTQ_SEND_BD_COMP_CTL 0x00005c40
1035 #define FTQ_SEND_BD_COMP_FULL_CNT 0x00005c44
1036 #define FTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48
1037 #define FTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c
1038 #define FTQ_SEND_DATA_INIT_CTL 0x00005c50
1039 #define FTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54
1040 #define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58
1041 #define FTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c
1042 #define FTQ_DMA_NORM_WRITE_CTL 0x00005c60
1043 #define FTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64
1044 #define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68
1045 #define FTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c
1046 #define FTQ_DMA_HIGH_WRITE_CTL 0x00005c70
1047 #define FTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74
1048 #define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78
1049 #define FTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c
1050 #define FTQ_SWTYPE1_CTL 0x00005c80
1051 #define FTQ_SWTYPE1_FULL_CNT 0x00005c84
1052 #define FTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88
1053 #define FTQ_SWTYPE1_WRITE_PEEK 0x00005c8c
1054 #define FTQ_SEND_DATA_COMP_CTL 0x00005c90
1055 #define FTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94
1056 #define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98
1057 #define FTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c
1058 #define FTQ_HOST_COAL_CTL 0x00005ca0
1059 #define FTQ_HOST_COAL_FULL_CNT 0x00005ca4
1060 #define FTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8
1061 #define FTQ_HOST_COAL_WRITE_PEEK 0x00005cac
1062 #define FTQ_MAC_TX_CTL 0x00005cb0
1063 #define FTQ_MAC_TX_FULL_CNT 0x00005cb4
1064 #define FTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8
1065 #define FTQ_MAC_TX_WRITE_PEEK 0x00005cbc
1066 #define FTQ_MB_FREE_CTL 0x00005cc0
1067 #define FTQ_MB_FREE_FULL_CNT 0x00005cc4
1068 #define FTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8
1069 #define FTQ_MB_FREE_WRITE_PEEK 0x00005ccc
1070 #define FTQ_RCVBD_COMP_CTL 0x00005cd0
1071 #define FTQ_RCVBD_COMP_FULL_CNT 0x00005cd4
1072 #define FTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8
1073 #define FTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc
1074 #define FTQ_RCVLST_PLMT_CTL 0x00005ce0
1075 #define FTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4
1076 #define FTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8
1077 #define FTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec
1078 #define FTQ_RCVDATA_INI_CTL 0x00005cf0
1079 #define FTQ_RCVDATA_INI_FULL_CNT 0x00005cf4
1080 #define FTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8
1081 #define FTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc
1082 #define FTQ_RCVDATA_COMP_CTL 0x00005d00
1083 #define FTQ_RCVDATA_COMP_FULL_CNT 0x00005d04
1084 #define FTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08
1085 #define FTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c
1086 #define FTQ_SWTYPE2_CTL 0x00005d10
1087 #define FTQ_SWTYPE2_FULL_CNT 0x00005d14
1088 #define FTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18
1089 #define FTQ_SWTYPE2_WRITE_PEEK 0x00005d1c
1090 /* 0x5d20 --> 0x6000 unused */
1092 /* Message signaled interrupt registers */
1093 #define MSGINT_MODE 0x00006000
1094 #define MSGINT_MODE_RESET 0x00000001
1095 #define MSGINT_MODE_ENABLE 0x00000002
1096 #define MSGINT_STATUS 0x00006004
1097 #define MSGINT_FIFO 0x00006008
1098 /* 0x600c --> 0x6400 unused */
1100 /* DMA completion registers */
1101 #define DMAC_MODE 0x00006400
1102 #define DMAC_MODE_RESET 0x00000001
1103 #define DMAC_MODE_ENABLE 0x00000002
1104 /* 0x6404 --> 0x6800 unused */
1106 /* GRC registers */
1107 #define GRC_MODE 0x00006800
1108 #define GRC_MODE_UPD_ON_COAL 0x00000001
1109 #define GRC_MODE_BSWAP_NONFRM_DATA 0x00000002
1110 #define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004
1111 #define GRC_MODE_BSWAP_DATA 0x00000010
1112 #define GRC_MODE_WSWAP_DATA 0x00000020
1113 #define GRC_MODE_SPLITHDR 0x00000100
1114 #define GRC_MODE_NOFRM_CRACKING 0x00000200
1115 #define GRC_MODE_INCL_CRC 0x00000400
1116 #define GRC_MODE_ALLOW_BAD_FRMS 0x00000800
1117 #define GRC_MODE_NOIRQ_ON_SENDS 0x00002000
1118 #define GRC_MODE_NOIRQ_ON_RCV 0x00004000
1119 #define GRC_MODE_FORCE_PCI32BIT 0x00008000
1120 #define GRC_MODE_HOST_STACKUP 0x00010000
1121 #define GRC_MODE_HOST_SENDBDS 0x00020000
1122 #define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000
1123 #define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000
1124 #define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000
1125 #define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000
1126 #define GRC_MODE_IRQ_ON_MAC_ATTN 0x04000000
1127 #define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000
1128 #define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000
1129 #define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000
1130 #define GRC_MODE_MCAST_FRM_ENABLE 0x40000000
1131 #define GRC_MISC_CFG 0x00006804
1132 #define GRC_MISC_CFG_CORECLK_RESET 0x00000001
1133 #define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe
1134 #define GRC_MISC_CFG_PRESCALAR_SHIFT 1
1135 #define GRC_MISC_CFG_BOARD_ID_MASK 0x0001e000
1136 #define GRC_MISC_CFG_BOARD_ID_5700 0x0001e000
1137 #define GRC_MISC_CFG_BOARD_ID_5701 0x00000000
1138 #define GRC_MISC_CFG_BOARD_ID_5702FE 0x00004000
1139 #define GRC_MISC_CFG_BOARD_ID_5703 0x00000000
1140 #define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000
1141 #define GRC_MISC_CFG_BOARD_ID_5704 0x00000000
1142 #define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000
1143 #define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000
1144 #define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
1145 #define GRC_LOCAL_CTRL 0x00006808
1146 #define GRC_LCLCTRL_INT_ACTIVE 0x00000001
1147 #define GRC_LCLCTRL_CLEARINT 0x00000002
1148 #define GRC_LCLCTRL_SETINT 0x00000004
1149 #define GRC_LCLCTRL_INT_ON_ATTN 0x00000008
1150 #define GRC_LCLCTRL_GPIO_INPUT0 0x00000100
1151 #define GRC_LCLCTRL_GPIO_INPUT1 0x00000200
1152 #define GRC_LCLCTRL_GPIO_INPUT2 0x00000400
1153 #define GRC_LCLCTRL_GPIO_OE0 0x00000800
1154 #define GRC_LCLCTRL_GPIO_OE1 0x00001000
1155 #define GRC_LCLCTRL_GPIO_OE2 0x00002000
1156 #define GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000
1157 #define GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000
1158 #define GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000
1159 #define GRC_LCLCTRL_EXTMEM_ENABLE 0x00020000
1160 #define GRC_LCLCTRL_MEMSZ_MASK 0x001c0000
1161 #define GRC_LCLCTRL_MEMSZ_256K 0x00000000
1162 #define GRC_LCLCTRL_MEMSZ_512K 0x00040000
1163 #define GRC_LCLCTRL_MEMSZ_1M 0x00080000
1164 #define GRC_LCLCTRL_MEMSZ_2M 0x000c0000
1165 #define GRC_LCLCTRL_MEMSZ_4M 0x00100000
1166 #define GRC_LCLCTRL_MEMSZ_8M 0x00140000
1167 #define GRC_LCLCTRL_MEMSZ_16M 0x00180000
1168 #define GRC_LCLCTRL_BANK_SELECT 0x00200000
1169 #define GRC_LCLCTRL_SSRAM_TYPE 0x00400000
1170 #define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000
1171 #define GRC_TIMER 0x0000680c
1172 #define GRC_RX_CPU_EVENT 0x00006810
1173 #define GRC_RX_TIMER_REF 0x00006814
1174 #define GRC_RX_CPU_SEM 0x00006818
1175 #define GRC_REMOTE_RX_CPU_ATTN 0x0000681c
1176 #define GRC_TX_CPU_EVENT 0x00006820
1177 #define GRC_TX_TIMER_REF 0x00006824
1178 #define GRC_TX_CPU_SEM 0x00006828
1179 #define GRC_REMOTE_TX_CPU_ATTN 0x0000682c
1180 #define GRC_MEM_POWER_UP 0x00006830 /* 64-bit */
1181 #define GRC_EEPROM_ADDR 0x00006838
1182 #define EEPROM_ADDR_WRITE 0x00000000
1183 #define EEPROM_ADDR_READ 0x80000000
1184 #define EEPROM_ADDR_COMPLETE 0x40000000
1185 #define EEPROM_ADDR_FSM_RESET 0x20000000
1186 #define EEPROM_ADDR_DEVID_MASK 0x1c000000
1187 #define EEPROM_ADDR_DEVID_SHIFT 26
1188 #define EEPROM_ADDR_START 0x02000000
1189 #define EEPROM_ADDR_CLKPERD_SHIFT 16
1190 #define EEPROM_ADDR_ADDR_MASK 0x0000ffff
1191 #define EEPROM_ADDR_ADDR_SHIFT 0
1192 #define EEPROM_DEFAULT_CLOCK_PERIOD 0x60
1193 #define EEPROM_CHIP_SIZE (64 * 1024)
1194 #define GRC_EEPROM_DATA 0x0000683c
1195 #define GRC_EEPROM_CTRL 0x00006840
1196 #define GRC_MDI_CTRL 0x00006844
1197 #define GRC_SEEPROM_DELAY 0x00006848
1198 /* 0x684c --> 0x6c00 unused */
1200 /* 0x6c00 --> 0x7000 unused */
1202 /* NVRAM Control registers */
1203 #define NVRAM_CMD 0x00007000
1204 #define NVRAM_CMD_RESET 0x00000001
1205 #define NVRAM_CMD_DONE 0x00000008
1206 #define NVRAM_CMD_GO 0x00000010
1207 #define NVRAM_CMD_WR 0x00000020
1208 #define NVRAM_CMD_RD 0x00000000
1209 #define NVRAM_CMD_ERASE 0x00000040
1210 #define NVRAM_CMD_FIRST 0x00000080
1211 #define NVRAM_CMD_LAST 0x00000100
1212 #define NVRAM_STAT 0x00007004
1213 #define NVRAM_WRDATA 0x00007008
1214 #define NVRAM_ADDR 0x0000700c
1215 #define NVRAM_ADDR_MSK 0x00ffffff
1216 #define NVRAM_RDDATA 0x00007010
1217 #define NVRAM_CFG1 0x00007014
1218 #define NVRAM_CFG1_FLASHIF_ENAB 0x00000001
1219 #define NVRAM_CFG1_BUFFERED_MODE 0x00000002
1220 #define NVRAM_CFG1_PASS_THRU 0x00000004
1221 #define NVRAM_CFG1_BIT_BANG 0x00000008
1222 #define NVRAM_CFG1_COMPAT_BYPASS 0x80000000
1223 #define NVRAM_CFG2 0x00007018
1224 #define NVRAM_CFG3 0x0000701c
1225 #define NVRAM_SWARB 0x00007020
1226 #define SWARB_REQ_SET0 0x00000001
1227 #define SWARB_REQ_SET1 0x00000002
1228 #define SWARB_REQ_SET2 0x00000004
1229 #define SWARB_REQ_SET3 0x00000008
1230 #define SWARB_REQ_CLR0 0x00000010
1231 #define SWARB_REQ_CLR1 0x00000020
1232 #define SWARB_REQ_CLR2 0x00000040
1233 #define SWARB_REQ_CLR3 0x00000080
1234 #define SWARB_GNT0 0x00000100
1235 #define SWARB_GNT1 0x00000200
1236 #define SWARB_GNT2 0x00000400
1237 #define SWARB_GNT3 0x00000800
1238 #define SWARB_REQ0 0x00001000
1239 #define SWARB_REQ1 0x00002000
1240 #define SWARB_REQ2 0x00004000
1241 #define SWARB_REQ3 0x00008000
1242 #define NVRAM_BUFFERED_PAGE_SIZE 264
1243 #define NVRAM_BUFFERED_PAGE_POS 9
1244 /* 0x7024 --> 0x7400 unused */
1246 /* 0x7400 --> 0x8000 unused */
1248 /* 32K Window into NIC internal memory */
1249 #define NIC_SRAM_WIN_BASE 0x00008000
1251 /* Offsets into first 32k of NIC internal memory. */
1252 #define NIC_SRAM_PAGE_ZERO 0x00000000
1253 #define NIC_SRAM_SEND_RCB 0x00000100 /* 16 * TG3_BDINFO_... */
1254 #define NIC_SRAM_RCV_RET_RCB 0x00000200 /* 16 * TG3_BDINFO_... */
1255 #define NIC_SRAM_STATS_BLK 0x00000300
1256 #define NIC_SRAM_STATUS_BLK 0x00000b00
1258 #define NIC_SRAM_FIRMWARE_MBOX 0x00000b50
1259 #define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654
1260 #define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b /* !dma on linkchg */
1262 #define NIC_SRAM_DATA_SIG 0x00000b54
1263 #define NIC_SRAM_DATA_SIG_MAGIC 0x4b657654 /* ascii for 'KevT' */
1265 #define NIC_SRAM_DATA_CFG 0x00000b58
1266 #define NIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c
1267 #define NIC_SRAM_DATA_CFG_LED_MODE_UNKNOWN 0x00000000
1268 #define NIC_SRAM_DATA_CFG_LED_TRIPLE_SPD 0x00000004
1269 #define NIC_SRAM_DATA_CFG_LED_OPEN_DRAIN 0x00000004
1270 #define NIC_SRAM_DATA_CFG_LED_LINK_SPD 0x00000008
1271 #define NIC_SRAM_DATA_CFG_LED_OUTPUT 0x00000008
1272 #define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030
1273 #define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN 0x00000000
1274 #define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER 0x00000010
1275 #define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER 0x00000020
1276 #define NIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040
1277 #define NIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080
1278 #define NIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100
1279 #define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000
1281 #define NIC_SRAM_DATA_PHY_ID 0x00000b74
1282 #define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000
1283 #define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff
1285 #define NIC_SRAM_FW_CMD_MBOX 0x00000b78
1286 #define FWCMD_NICDRV_ALIVE 0x00000001
1287 #define FWCMD_NICDRV_PAUSE_FW 0x00000002
1288 #define FWCMD_NICDRV_IPV4ADDR_CHG 0x00000003
1289 #define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004
1290 #define FWCMD_NICDRV_FIX_DMAR 0x00000005
1291 #define FWCMD_NICDRV_FIX_DMAW 0x00000006
1292 #define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c
1293 #define NIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80
1294 #define NIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00
1295 #define NIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04
1296 #define DRV_STATE_START 0x00000001
1297 #define DRV_STATE_UNLOAD 0x00000002
1298 #define DRV_STATE_WOL 0x00000003
1299 #define DRV_STATE_SUSPEND 0x00000004
1301 #define NIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08
1303 #define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14
1304 #define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18
1306 #define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
1308 #define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000
1309 #define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000
1310 #define NIC_SRAM_TX_BUFFER_DESC 0x00004000 /* 512 entries */
1311 #define NIC_SRAM_RX_BUFFER_DESC 0x00006000 /* 256 entries */
1312 #define NIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000 /* 256 entries */
1313 #define NIC_SRAM_MBUF_POOL_BASE 0x00008000
1314 #define NIC_SRAM_MBUF_POOL_SIZE96 0x00018000
1315 #define NIC_SRAM_MBUF_POOL_SIZE64 0x00010000
1317 /* Currently this is fixed. */
1318 #define PHY_ADDR 0x01
1320 /* Tigon3 specific PHY MII registers. */
1321 #define TG3_BMCR_SPEED1000 0x0040
1323 #define MII_TG3_CTRL 0x09 /* 1000-baseT control register */
1324 #define MII_TG3_CTRL_ADV_1000_HALF 0x0100
1325 #define MII_TG3_CTRL_ADV_1000_FULL 0x0200
1326 #define MII_TG3_CTRL_AS_MASTER 0x0800
1327 #define MII_TG3_CTRL_ENABLE_AS_MASTER 0x1000
1329 #define MII_TG3_EXT_CTRL 0x10 /* Extended control register */
1330 #define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002
1331 #define MII_TG3_EXT_CTRL_TBI 0x8000
1333 #define MII_TG3_EXT_STAT 0x11 /* Extended status register */
1334 #define MII_TG3_EXT_STAT_LPASS 0x0100
1336 #define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */
1338 #define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */
1340 #define MII_TG3_AUX_CTRL 0x18 /* auxilliary control register */
1342 #define MII_TG3_AUX_STAT 0x19 /* auxilliary status register */
1343 #define MII_TG3_AUX_STAT_LPASS 0x0004
1344 #define MII_TG3_AUX_STAT_SPDMASK 0x0700
1345 #define MII_TG3_AUX_STAT_10HALF 0x0100
1346 #define MII_TG3_AUX_STAT_10FULL 0x0200
1347 #define MII_TG3_AUX_STAT_100HALF 0x0300
1348 #define MII_TG3_AUX_STAT_100_4 0x0400
1349 #define MII_TG3_AUX_STAT_100FULL 0x0500
1350 #define MII_TG3_AUX_STAT_1000HALF 0x0600
1351 #define MII_TG3_AUX_STAT_1000FULL 0x0700
1353 #define MII_TG3_ISTAT 0x1a /* IRQ status register */
1354 #define MII_TG3_IMASK 0x1b /* IRQ mask register */
1356 /* ISTAT/IMASK event bits */
1357 #define MII_TG3_INT_LINKCHG 0x0002
1358 #define MII_TG3_INT_SPEEDCHG 0x0004
1359 #define MII_TG3_INT_DUPLEXCHG 0x0008
1360 #define MII_TG3_INT_ANEG_PAGE_RX 0x0400
1362 /* XXX Add this to mii.h */
1363 #ifndef ADVERTISE_PAUSE
1364 #define ADVERTISE_PAUSE_CAP 0x0400
1365 #endif
1366 #ifndef ADVERTISE_PAUSE_ASYM
1367 #define ADVERTISE_PAUSE_ASYM 0x0800
1368 #endif
1369 #ifndef LPA_PAUSE
1370 #define LPA_PAUSE_CAP 0x0400
1371 #endif
1372 #ifndef LPA_PAUSE_ASYM
1373 #define LPA_PAUSE_ASYM 0x0800
1374 #endif
1376 /* There are two ways to manage the TX descriptors on the tigon3.
1377 * Either the descriptors are in host DMA'able memory, or they
1378 * exist only in the cards on-chip SRAM. All 16 send bds are under
1379 * the same mode, they may not be configured individually.
1381 * The mode we use is controlled by TG3_FLAG_HOST_TXDS in tp->tg3_flags.
1383 * To use host memory TX descriptors:
1384 * 1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register.
1385 * Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear.
1386 * 2) Allocate DMA'able memory.
1387 * 3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
1388 * a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory
1389 * obtained in step 2
1390 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC.
1391 * c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number
1392 * of TX descriptors. Leave flags field clear.
1393 * 4) Access TX descriptors via host memory. The chip
1394 * will refetch into local SRAM as needed when producer
1395 * index mailboxes are updated.
1397 * To use on-chip TX descriptors:
1398 * 1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register.
1399 * Make sure GRC_MODE_HOST_SENDBDS is clear.
1400 * 2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
1401 * a) Set TG3_BDINFO_HOST_ADDR to zero.
1402 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC
1403 * c) TG3_BDINFO_MAXLEN_FLAGS is don't care.
1404 * 3) Access TX descriptors directly in on-chip SRAM
1405 * using normal {read,write}l(). (and not using
1406 * pointer dereferencing of ioremap()'d memory like
1407 * the broken Broadcom driver does)
1409 * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of
1410 * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices.
1411 */
1412 struct tg3_tx_buffer_desc {
1413 u32 addr_hi;
1414 u32 addr_lo;
1416 u32 len_flags;
1417 #define TXD_FLAG_TCPUDP_CSUM 0x0001
1418 #define TXD_FLAG_IP_CSUM 0x0002
1419 #define TXD_FLAG_END 0x0004
1420 #define TXD_FLAG_IP_FRAG 0x0008
1421 #define TXD_FLAG_IP_FRAG_END 0x0010
1422 #define TXD_FLAG_VLAN 0x0040
1423 #define TXD_FLAG_COAL_NOW 0x0080
1424 #define TXD_FLAG_CPU_PRE_DMA 0x0100
1425 #define TXD_FLAG_CPU_POST_DMA 0x0200
1426 #define TXD_FLAG_ADD_SRC_ADDR 0x1000
1427 #define TXD_FLAG_CHOOSE_SRC_ADDR 0x6000
1428 #define TXD_FLAG_NO_CRC 0x8000
1429 #define TXD_LEN_SHIFT 16
1431 u32 vlan_tag;
1432 #define TXD_VLAN_TAG_SHIFT 0
1433 #define TXD_MSS_SHIFT 16
1434 };
1436 #define TXD_ADDR 0x00UL /* 64-bit */
1437 #define TXD_LEN_FLAGS 0x08UL /* 32-bit (upper 16-bits are len) */
1438 #define TXD_VLAN_TAG 0x0cUL /* 32-bit (upper 16-bits are tag) */
1439 #define TXD_SIZE 0x10UL
1441 struct tg3_rx_buffer_desc {
1442 u32 addr_hi;
1443 u32 addr_lo;
1445 u32 idx_len;
1446 #define RXD_IDX_MASK 0xffff0000
1447 #define RXD_IDX_SHIFT 16
1448 #define RXD_LEN_MASK 0x0000ffff
1449 #define RXD_LEN_SHIFT 0
1451 u32 type_flags;
1452 #define RXD_TYPE_SHIFT 16
1453 #define RXD_FLAGS_SHIFT 0
1455 #define RXD_FLAG_END 0x0004
1456 #define RXD_FLAG_MINI 0x0800
1457 #define RXD_FLAG_JUMBO 0x0020
1458 #define RXD_FLAG_VLAN 0x0040
1459 #define RXD_FLAG_ERROR 0x0400
1460 #define RXD_FLAG_IP_CSUM 0x1000
1461 #define RXD_FLAG_TCPUDP_CSUM 0x2000
1462 #define RXD_FLAG_IS_TCP 0x4000
1464 u32 ip_tcp_csum;
1465 #define RXD_IPCSUM_MASK 0xffff0000
1466 #define RXD_IPCSUM_SHIFT 16
1467 #define RXD_TCPCSUM_MASK 0x0000ffff
1468 #define RXD_TCPCSUM_SHIFT 0
1470 u32 err_vlan;
1472 #define RXD_VLAN_MASK 0x0000ffff
1474 #define RXD_ERR_BAD_CRC 0x00010000
1475 #define RXD_ERR_COLLISION 0x00020000
1476 #define RXD_ERR_LINK_LOST 0x00040000
1477 #define RXD_ERR_PHY_DECODE 0x00080000
1478 #define RXD_ERR_ODD_NIBBLE_RCVD_MII 0x00100000
1479 #define RXD_ERR_MAC_ABRT 0x00200000
1480 #define RXD_ERR_TOO_SMALL 0x00400000
1481 #define RXD_ERR_NO_RESOURCES 0x00800000
1482 #define RXD_ERR_HUGE_FRAME 0x01000000
1483 #define RXD_ERR_MASK 0xffff0000
1485 u32 reserved;
1486 u32 opaque;
1487 #define RXD_OPAQUE_INDEX_MASK 0x0000ffff
1488 #define RXD_OPAQUE_INDEX_SHIFT 0
1489 #define RXD_OPAQUE_RING_STD 0x00010000
1490 #define RXD_OPAQUE_RING_JUMBO 0x00020000
1491 #define RXD_OPAQUE_RING_MINI 0x00040000
1492 #define RXD_OPAQUE_RING_MASK 0x00070000
1493 };
1495 struct tg3_ext_rx_buffer_desc {
1496 struct {
1497 u32 addr_hi;
1498 u32 addr_lo;
1499 } addrlist[3];
1500 u32 len2_len1;
1501 u32 resv_len3;
1502 struct tg3_rx_buffer_desc std;
1503 };
1505 /* We only use this when testing out the DMA engine
1506 * at probe time. This is the internal format of buffer
1507 * descriptors used by the chip at NIC_SRAM_DMA_DESCS.
1508 */
1509 struct tg3_internal_buffer_desc {
1510 u32 addr_hi;
1511 u32 addr_lo;
1512 u32 nic_mbuf;
1513 /* XXX FIX THIS */
1514 #ifdef __BIG_ENDIAN
1515 u16 cqid_sqid;
1516 u16 len;
1517 #else
1518 u16 len;
1519 u16 cqid_sqid;
1520 #endif
1521 u32 flags;
1522 u32 __cookie1;
1523 u32 __cookie2;
1524 u32 __cookie3;
1525 };
1527 #define TG3_HW_STATUS_SIZE 0x50
1528 struct tg3_hw_status {
1529 u32 status;
1530 #define SD_STATUS_UPDATED 0x00000001
1531 #define SD_STATUS_LINK_CHG 0x00000002
1532 #define SD_STATUS_ERROR 0x00000004
1534 u32 status_tag;
1536 #ifdef __BIG_ENDIAN
1537 u16 rx_consumer;
1538 u16 rx_jumbo_consumer;
1539 #else
1540 u16 rx_jumbo_consumer;
1541 u16 rx_consumer;
1542 #endif
1544 #ifdef __BIG_ENDIAN
1545 u16 reserved;
1546 u16 rx_mini_consumer;
1547 #else
1548 u16 rx_mini_consumer;
1549 u16 reserved;
1550 #endif
1551 struct {
1552 #ifdef __BIG_ENDIAN
1553 u16 tx_consumer;
1554 u16 rx_producer;
1555 #else
1556 u16 rx_producer;
1557 u16 tx_consumer;
1558 #endif
1559 } idx[16];
1560 };
1562 typedef struct {
1563 u32 high, low;
1564 } tg3_stat64_t;
1566 struct tg3_hw_stats {
1567 u8 __reserved0[0x400-0x300];
1569 /* Statistics maintained by Receive MAC. */
1570 tg3_stat64_t rx_octets;
1571 u64 __reserved1;
1572 tg3_stat64_t rx_fragments;
1573 tg3_stat64_t rx_ucast_packets;
1574 tg3_stat64_t rx_mcast_packets;
1575 tg3_stat64_t rx_bcast_packets;
1576 tg3_stat64_t rx_fcs_errors;
1577 tg3_stat64_t rx_align_errors;
1578 tg3_stat64_t rx_xon_pause_rcvd;
1579 tg3_stat64_t rx_xoff_pause_rcvd;
1580 tg3_stat64_t rx_mac_ctrl_rcvd;
1581 tg3_stat64_t rx_xoff_entered;
1582 tg3_stat64_t rx_frame_too_long_errors;
1583 tg3_stat64_t rx_jabbers;
1584 tg3_stat64_t rx_undersize_packets;
1585 tg3_stat64_t rx_in_length_errors;
1586 tg3_stat64_t rx_out_length_errors;
1587 tg3_stat64_t rx_64_or_less_octet_packets;
1588 tg3_stat64_t rx_65_to_127_octet_packets;
1589 tg3_stat64_t rx_128_to_255_octet_packets;
1590 tg3_stat64_t rx_256_to_511_octet_packets;
1591 tg3_stat64_t rx_512_to_1023_octet_packets;
1592 tg3_stat64_t rx_1024_to_1522_octet_packets;
1593 tg3_stat64_t rx_1523_to_2047_octet_packets;
1594 tg3_stat64_t rx_2048_to_4095_octet_packets;
1595 tg3_stat64_t rx_4096_to_8191_octet_packets;
1596 tg3_stat64_t rx_8192_to_9022_octet_packets;
1598 u64 __unused0[37];
1600 /* Statistics maintained by Transmit MAC. */
1601 tg3_stat64_t tx_octets;
1602 u64 __reserved2;
1603 tg3_stat64_t tx_collisions;
1604 tg3_stat64_t tx_xon_sent;
1605 tg3_stat64_t tx_xoff_sent;
1606 tg3_stat64_t tx_flow_control;
1607 tg3_stat64_t tx_mac_errors;
1608 tg3_stat64_t tx_single_collisions;
1609 tg3_stat64_t tx_mult_collisions;
1610 tg3_stat64_t tx_deferred;
1611 u64 __reserved3;
1612 tg3_stat64_t tx_excessive_collisions;
1613 tg3_stat64_t tx_late_collisions;
1614 tg3_stat64_t tx_collide_2times;
1615 tg3_stat64_t tx_collide_3times;
1616 tg3_stat64_t tx_collide_4times;
1617 tg3_stat64_t tx_collide_5times;
1618 tg3_stat64_t tx_collide_6times;
1619 tg3_stat64_t tx_collide_7times;
1620 tg3_stat64_t tx_collide_8times;
1621 tg3_stat64_t tx_collide_9times;
1622 tg3_stat64_t tx_collide_10times;
1623 tg3_stat64_t tx_collide_11times;
1624 tg3_stat64_t tx_collide_12times;
1625 tg3_stat64_t tx_collide_13times;
1626 tg3_stat64_t tx_collide_14times;
1627 tg3_stat64_t tx_collide_15times;
1628 tg3_stat64_t tx_ucast_packets;
1629 tg3_stat64_t tx_mcast_packets;
1630 tg3_stat64_t tx_bcast_packets;
1631 tg3_stat64_t tx_carrier_sense_errors;
1632 tg3_stat64_t tx_discards;
1633 tg3_stat64_t tx_errors;
1635 u64 __unused1[31];
1637 /* Statistics maintained by Receive List Placement. */
1638 tg3_stat64_t COS_rx_packets[16];
1639 tg3_stat64_t COS_rx_filter_dropped;
1640 tg3_stat64_t dma_writeq_full;
1641 tg3_stat64_t dma_write_prioq_full;
1642 tg3_stat64_t rxbds_empty;
1643 tg3_stat64_t rx_discards;
1644 tg3_stat64_t rx_errors;
1645 tg3_stat64_t rx_threshold_hit;
1647 u64 __unused2[9];
1649 /* Statistics maintained by Send Data Initiator. */
1650 tg3_stat64_t COS_out_packets[16];
1651 tg3_stat64_t dma_readq_full;
1652 tg3_stat64_t dma_read_prioq_full;
1653 tg3_stat64_t tx_comp_queue_full;
1655 /* Statistics maintained by Host Coalescing. */
1656 tg3_stat64_t ring_set_send_prod_index;
1657 tg3_stat64_t ring_status_update;
1658 tg3_stat64_t nic_irqs;
1659 tg3_stat64_t nic_avoided_irqs;
1660 tg3_stat64_t nic_tx_threshold_hit;
1662 u8 __reserved4[0xb00-0x9c0];
1663 };
1665 enum phy_led_mode {
1666 led_mode_auto,
1667 led_mode_three_link,
1668 led_mode_link10
1669 };
1671 /* 'mapping' is superfluous as the chip does not write into
1672 * the tx/rx post rings so we could just fetch it from there.
1673 * But the cache behavior is better how we are doing it now.
1674 */
1675 struct ring_info {
1676 struct sk_buff *skb;
1677 DECLARE_PCI_UNMAP_ADDR(mapping)
1678 };
1680 struct tx_ring_info {
1681 struct sk_buff *skb;
1682 DECLARE_PCI_UNMAP_ADDR(mapping)
1683 u32 prev_vlan_tag;
1684 };
1686 struct tg3_config_info {
1687 u32 flags;
1688 };
1690 struct tg3_link_config {
1691 /* Describes what we're trying to get. */
1692 u32 advertising;
1693 u16 speed;
1694 u8 duplex;
1695 u8 autoneg;
1697 /* Describes what we actually have. */
1698 u16 active_speed;
1699 u8 active_duplex;
1700 #define SPEED_INVALID 0xffff
1701 #define DUPLEX_INVALID 0xff
1702 #define AUTONEG_INVALID 0xff
1704 /* When we go in and out of low power mode we need
1705 * to swap with this state.
1706 */
1707 int phy_is_low_power;
1708 u16 orig_speed;
1709 u8 orig_duplex;
1710 u8 orig_autoneg;
1711 };
1713 struct tg3_bufmgr_config {
1714 u32 mbuf_read_dma_low_water;
1715 u32 mbuf_mac_rx_low_water;
1716 u32 mbuf_high_water;
1718 u32 mbuf_read_dma_low_water_jumbo;
1719 u32 mbuf_mac_rx_low_water_jumbo;
1720 u32 mbuf_high_water_jumbo;
1722 u32 dma_low_water;
1723 u32 dma_high_water;
1724 };
1726 struct tg3 {
1727 /* begin "general, frequently-used members" cacheline section */
1729 /* SMP locking strategy:
1731 * lock: Held during all operations except TX packet
1732 * processing.
1734 * tx_lock: Held during tg3_start_xmit{,_4gbug} and tg3_tx
1736 * If you want to shut up all asynchronous processing you must
1737 * acquire both locks, 'lock' taken before 'tx_lock'. IRQs must
1738 * be disabled to take 'lock' but only softirq disabling is
1739 * necessary for acquisition of 'tx_lock'.
1740 */
1741 spinlock_t lock;
1742 spinlock_t indirect_lock;
1744 unsigned long regs;
1745 struct net_device *dev;
1746 struct pci_dev *pdev;
1748 struct tg3_hw_status *hw_status;
1749 dma_addr_t status_mapping;
1751 u32 msg_enable;
1753 /* begin "tx thread" cacheline section */
1754 u32 tx_prod;
1755 u32 tx_cons;
1756 u32 tx_pending;
1758 spinlock_t tx_lock;
1760 /* TX descs are only used if TG3_FLAG_HOST_TXDS is set. */
1761 struct tg3_tx_buffer_desc *tx_ring;
1762 struct tx_ring_info *tx_buffers;
1763 dma_addr_t tx_desc_mapping;
1765 /* begin "rx thread" cacheline section */
1766 u32 rx_rcb_ptr;
1767 u32 rx_std_ptr;
1768 u32 rx_jumbo_ptr;
1769 u32 rx_pending;
1770 u32 rx_jumbo_pending;
1771 #if TG3_VLAN_TAG_USED
1772 struct vlan_group *vlgrp;
1773 #endif
1775 struct tg3_rx_buffer_desc *rx_std;
1776 struct ring_info *rx_std_buffers;
1777 dma_addr_t rx_std_mapping;
1779 struct tg3_rx_buffer_desc *rx_jumbo;
1780 struct ring_info *rx_jumbo_buffers;
1781 dma_addr_t rx_jumbo_mapping;
1783 struct tg3_rx_buffer_desc *rx_rcb;
1784 dma_addr_t rx_rcb_mapping;
1786 /* begin "everything else" cacheline(s) section */
1787 struct net_device_stats net_stats;
1788 struct net_device_stats net_stats_prev;
1789 unsigned long phy_crc_errors;
1791 u32 rx_offset;
1792 u32 tg3_flags;
1793 #define TG3_FLAG_HOST_TXDS 0x00000001
1794 #define TG3_FLAG_TXD_MBOX_HWBUG 0x00000002
1795 #define TG3_FLAG_RX_CHECKSUMS 0x00000004
1796 #define TG3_FLAG_USE_LINKCHG_REG 0x00000008
1797 #define TG3_FLAG_USE_MI_INTERRUPT 0x00000010
1798 #define TG3_FLAG_ENABLE_ASF 0x00000020
1799 #define TG3_FLAG_5701_REG_WRITE_BUG 0x00000040
1800 #define TG3_FLAG_POLL_SERDES 0x00000080
1801 #define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100
1802 #define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200
1803 #define TG3_FLAG_WOL_SPEED_100MB 0x00000400
1804 #define TG3_FLAG_WOL_ENABLE 0x00000800
1805 #define TG3_FLAG_EEPROM_WRITE_PROT 0x00001000
1806 #define TG3_FLAG_NVRAM 0x00002000
1807 #define TG3_FLAG_NVRAM_BUFFERED 0x00004000
1808 #define TG3_FLAG_RX_PAUSE 0x00008000
1809 #define TG3_FLAG_TX_PAUSE 0x00010000
1810 #define TG3_FLAG_PCIX_MODE 0x00020000
1811 #define TG3_FLAG_PCI_HIGH_SPEED 0x00040000
1812 #define TG3_FLAG_PCI_32BIT 0x00080000
1813 #define TG3_FLAG_NO_TX_PSEUDO_CSUM 0x00100000
1814 #define TG3_FLAG_NO_RX_PSEUDO_CSUM 0x00200000
1815 #define TG3_FLAG_SERDES_WOL_CAP 0x00400000
1816 #define TG3_FLAG_JUMBO_ENABLE 0x00800000
1817 #define TG3_FLAG_10_100_ONLY 0x01000000
1818 #define TG3_FLAG_PAUSE_AUTONEG 0x02000000
1819 #define TG3_FLAG_PAUSE_RX 0x04000000
1820 #define TG3_FLAG_PAUSE_TX 0x08000000
1821 #define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000
1822 #define TG3_FLAG_GOT_SERDES_FLOWCTL 0x20000000
1823 #define TG3_FLAG_SPLIT_MODE 0x40000000
1824 #define TG3_FLAG_INIT_COMPLETE 0x80000000
1825 u32 tg3_flags2;
1826 #define TG3_FLG2_RESTART_TIMER 0x00000001
1828 u32 split_mode_max_reqs;
1829 #define SPLIT_MODE_5704_MAX_REQ 3
1831 struct timer_list timer;
1832 u16 timer_counter;
1833 u16 timer_multiplier;
1834 u32 timer_offset;
1835 u16 asf_counter;
1836 u16 asf_multiplier;
1838 struct tg3_link_config link_config;
1839 struct tg3_bufmgr_config bufmgr_config;
1841 /* cache h/w values, often passed straight to h/w */
1842 u32 rx_mode;
1843 u32 tx_mode;
1844 u32 mac_mode;
1845 u32 mi_mode;
1846 u32 misc_host_ctrl;
1847 u32 grc_mode;
1848 u32 grc_local_ctrl;
1849 u32 dma_rwctrl;
1850 u32 coalesce_mode;
1852 /* PCI block */
1853 u16 pci_chip_rev_id;
1854 u8 pci_cacheline_sz;
1855 u8 pci_lat_timer;
1856 u8 pci_hdr_type;
1857 u8 pci_bist;
1858 u32 pci_cfg_state[64 / sizeof(u32)];
1860 int pm_cap;
1862 /* PHY info */
1863 u32 phy_id;
1864 #define PHY_ID_MASK 0xfffffff0
1865 #define PHY_ID_BCM5400 0x60008040
1866 #define PHY_ID_BCM5401 0x60008050
1867 #define PHY_ID_BCM5411 0x60008070
1868 #define PHY_ID_BCM5701 0x60008110
1869 #define PHY_ID_BCM5703 0x60008160
1870 #define PHY_ID_BCM5704 0x60008190
1871 #define PHY_ID_BCM8002 0x60010140
1872 #define PHY_ID_SERDES 0xfeedbee0
1873 #define PHY_ID_INVALID 0xffffffff
1874 #define PHY_ID_REV_MASK 0x0000000f
1875 #define PHY_REV_BCM5401_B0 0x1
1876 #define PHY_REV_BCM5401_B2 0x3
1877 #define PHY_REV_BCM5401_C0 0x6
1878 #define PHY_REV_BCM5411_X0 0x1 /* Found on Netgear GA302T */
1880 enum phy_led_mode led_mode;
1882 char board_part_number[24];
1884 /* This macro assumes the passed PHY ID is already masked
1885 * with PHY_ID_MASK.
1886 */
1887 #define KNOWN_PHY_ID(X) \
1888 ((X) == PHY_ID_BCM5400 || (X) == PHY_ID_BCM5401 || \
1889 (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \
1890 (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \
1891 (X) == PHY_ID_BCM8002 || (X) == PHY_ID_SERDES)
1893 struct tg3_hw_stats *hw_stats;
1894 dma_addr_t stats_mapping;
1895 struct tq_struct reset_task;
1896 };
1898 #endif /* !(_T3_H) */