direct-io.hg

view linux-2.6-xen-sparse/arch/ia64/kernel/setup.c @ 13860:66ca8a0e046d

[IA64] Update installing the panic notifier for new upstream

Signed-off-by: Alex Williamson <alex.williamson@hp.com>
author awilliam@xenbuild2.aw
date Sun Jan 28 16:31:08 2007 -0700 (2007-01-28)
parents 3c8bb086025e
children 1502ba048b73
line source
1 /*
2 * Architecture-specific setup.
3 *
4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co
5 * David Mosberger-Tang <davidm@hpl.hp.com>
6 * Stephane Eranian <eranian@hpl.hp.com>
7 * Copyright (C) 2000, 2004 Intel Corp
8 * Rohit Seth <rohit.seth@intel.com>
9 * Suresh Siddha <suresh.b.siddha@intel.com>
10 * Gordon Jin <gordon.jin@intel.com>
11 * Copyright (C) 1999 VA Linux Systems
12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
13 *
14 * 12/26/04 S.Siddha, G.Jin, R.Seth
15 * Add multi-threading and multi-core detection
16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo().
17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map
18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes
19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes...
20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP
21 * 01/07/99 S.Eranian added the support for command line argument
22 * 06/24/99 W.Drummond added boot_cpu_data.
23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()"
24 */
25 #include <linux/module.h>
26 #include <linux/init.h>
28 #include <linux/acpi.h>
29 #include <linux/bootmem.h>
30 #include <linux/console.h>
31 #include <linux/delay.h>
32 #include <linux/kernel.h>
33 #include <linux/reboot.h>
34 #include <linux/sched.h>
35 #include <linux/seq_file.h>
36 #include <linux/string.h>
37 #include <linux/threads.h>
38 #include <linux/screen_info.h>
39 #include <linux/dmi.h>
40 #include <linux/serial.h>
41 #include <linux/serial_core.h>
42 #include <linux/efi.h>
43 #include <linux/initrd.h>
44 #include <linux/pm.h>
45 #include <linux/cpufreq.h>
47 #include <asm/ia32.h>
48 #include <asm/machvec.h>
49 #include <asm/mca.h>
50 #include <asm/meminit.h>
51 #include <asm/page.h>
52 #include <asm/patch.h>
53 #include <asm/pgtable.h>
54 #include <asm/processor.h>
55 #include <asm/sal.h>
56 #include <asm/sections.h>
57 #include <asm/serial.h>
58 #include <asm/setup.h>
59 #include <asm/smp.h>
60 #include <asm/system.h>
61 #include <asm/unistd.h>
62 #include <asm/system.h>
63 #ifdef CONFIG_XEN
64 #include <asm/hypervisor.h>
65 #include <asm/xen/xencomm.h>
66 #endif
67 #include <linux/dma-mapping.h>
69 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE)
70 # error "struct cpuinfo_ia64 too big!"
71 #endif
73 #ifdef CONFIG_SMP
74 unsigned long __per_cpu_offset[NR_CPUS];
75 EXPORT_SYMBOL(__per_cpu_offset);
76 #endif
78 #ifdef CONFIG_XEN
79 static void
80 xen_panic_hypercall(struct unw_frame_info *info, void *arg)
81 {
82 current->thread.ksp = (__u64)info->sw - 16;
83 HYPERVISOR_shutdown(SHUTDOWN_crash);
84 /* we're never actually going to get here... */
85 }
87 static int
88 xen_panic_event(struct notifier_block *this, unsigned long event, void *ptr)
89 {
90 unw_init_running(xen_panic_hypercall, NULL);
91 /* we're never actually going to get here... */
92 return NOTIFY_DONE;
93 }
95 static struct notifier_block xen_panic_block = {
96 xen_panic_event, NULL, 0 /* try to go last */
97 };
98 #endif
100 extern void ia64_setup_printk_clock(void);
102 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info);
103 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset);
104 DEFINE_PER_CPU(unsigned long, ia64_phys_stacked_size_p8);
105 unsigned long ia64_cycles_per_usec;
106 struct ia64_boot_param *ia64_boot_param;
107 struct screen_info screen_info;
108 unsigned long vga_console_iobase;
109 unsigned long vga_console_membase;
111 static struct resource data_resource = {
112 .name = "Kernel data",
113 .flags = IORESOURCE_BUSY | IORESOURCE_MEM
114 };
116 static struct resource code_resource = {
117 .name = "Kernel code",
118 .flags = IORESOURCE_BUSY | IORESOURCE_MEM
119 };
120 extern void efi_initialize_iomem_resources(struct resource *,
121 struct resource *);
122 extern char _text[], _end[], _etext[];
124 unsigned long ia64_max_cacheline_size;
126 int dma_get_cache_alignment(void)
127 {
128 return ia64_max_cacheline_size;
129 }
130 EXPORT_SYMBOL(dma_get_cache_alignment);
132 unsigned long ia64_iobase; /* virtual address for I/O accesses */
133 EXPORT_SYMBOL(ia64_iobase);
134 struct io_space io_space[MAX_IO_SPACES];
135 EXPORT_SYMBOL(io_space);
136 unsigned int num_io_spaces;
138 /*
139 * "flush_icache_range()" needs to know what processor dependent stride size to use
140 * when it makes i-cache(s) coherent with d-caches.
141 */
142 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */
143 unsigned long ia64_i_cache_stride_shift = ~0;
145 /*
146 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This
147 * mask specifies a mask of address bits that must be 0 in order for two buffers to be
148 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start
149 * address of the second buffer must be aligned to (merge_mask+1) in order to be
150 * mergeable). By default, we assume there is no I/O MMU which can merge physically
151 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu
152 * page-size of 2^64.
153 */
154 unsigned long ia64_max_iommu_merge_mask = ~0UL;
155 EXPORT_SYMBOL(ia64_max_iommu_merge_mask);
157 /*
158 * We use a special marker for the end of memory and it uses the extra (+1) slot
159 */
160 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1] __initdata;
161 int num_rsvd_regions __initdata;
164 /*
165 * Filter incoming memory segments based on the primitive map created from the boot
166 * parameters. Segments contained in the map are removed from the memory ranges. A
167 * caller-specified function is called with the memory ranges that remain after filtering.
168 * This routine does not assume the incoming segments are sorted.
169 */
170 int __init
171 filter_rsvd_memory (unsigned long start, unsigned long end, void *arg)
172 {
173 unsigned long range_start, range_end, prev_start;
174 void (*func)(unsigned long, unsigned long, int);
175 int i;
177 #if IGNORE_PFN0
178 if (start == PAGE_OFFSET) {
179 printk(KERN_WARNING "warning: skipping physical page 0\n");
180 start += PAGE_SIZE;
181 if (start >= end) return 0;
182 }
183 #endif
184 /*
185 * lowest possible address(walker uses virtual)
186 */
187 prev_start = PAGE_OFFSET;
188 func = arg;
190 for (i = 0; i < num_rsvd_regions; ++i) {
191 range_start = max(start, prev_start);
192 range_end = min(end, rsvd_region[i].start);
194 if (range_start < range_end)
195 call_pernode_memory(__pa(range_start), range_end - range_start, func);
197 /* nothing more available in this segment */
198 if (range_end == end) return 0;
200 prev_start = rsvd_region[i].end;
201 }
202 /* end of memory marker allows full processing inside loop body */
203 return 0;
204 }
206 static void __init
207 sort_regions (struct rsvd_region *rsvd_region, int max)
208 {
209 int j;
211 /* simple bubble sorting */
212 while (max--) {
213 for (j = 0; j < max; ++j) {
214 if (rsvd_region[j].start > rsvd_region[j+1].start) {
215 struct rsvd_region tmp;
216 tmp = rsvd_region[j];
217 rsvd_region[j] = rsvd_region[j + 1];
218 rsvd_region[j + 1] = tmp;
219 }
220 }
221 }
222 }
224 /*
225 * Request address space for all standard resources
226 */
227 static int __init register_memory(void)
228 {
229 code_resource.start = ia64_tpa(_text);
230 code_resource.end = ia64_tpa(_etext) - 1;
231 data_resource.start = ia64_tpa(_etext);
232 data_resource.end = ia64_tpa(_end) - 1;
233 efi_initialize_iomem_resources(&code_resource, &data_resource);
235 return 0;
236 }
238 __initcall(register_memory);
240 /**
241 * reserve_memory - setup reserved memory areas
242 *
243 * Setup the reserved memory areas set aside for the boot parameters,
244 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined,
245 * see include/asm-ia64/meminit.h if you need to define more.
246 */
247 void __init
248 reserve_memory (void)
249 {
250 int n = 0;
252 /*
253 * none of the entries in this table overlap
254 */
255 rsvd_region[n].start = (unsigned long) ia64_boot_param;
256 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param);
257 n++;
259 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap);
260 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size;
261 n++;
263 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line);
264 rsvd_region[n].end = (rsvd_region[n].start
265 + strlen(__va(ia64_boot_param->command_line)) + 1);
266 n++;
268 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START);
269 rsvd_region[n].end = (unsigned long) ia64_imva(_end);
270 n++;
272 #ifdef CONFIG_XEN
273 if (is_running_on_xen()) {
274 rsvd_region[n].start = (unsigned long)__va((HYPERVISOR_shared_info->arch.start_info_pfn << PAGE_SHIFT));
275 rsvd_region[n].end = rsvd_region[n].start + PAGE_SIZE;
276 n++;
277 }
278 #endif
280 #ifdef CONFIG_BLK_DEV_INITRD
281 if (ia64_boot_param->initrd_start) {
282 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start);
283 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size;
284 n++;
285 }
286 #endif
288 efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end);
289 n++;
291 /* end of memory marker */
292 rsvd_region[n].start = ~0UL;
293 rsvd_region[n].end = ~0UL;
294 n++;
296 num_rsvd_regions = n;
297 BUG_ON(IA64_MAX_RSVD_REGIONS + 1 < n);
299 sort_regions(rsvd_region, num_rsvd_regions);
300 }
302 /**
303 * find_initrd - get initrd parameters from the boot parameter structure
304 *
305 * Grab the initrd start and end from the boot parameter struct given us by
306 * the boot loader.
307 */
308 void __init
309 find_initrd (void)
310 {
311 #ifdef CONFIG_BLK_DEV_INITRD
312 if (ia64_boot_param->initrd_start) {
313 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start);
314 initrd_end = initrd_start+ia64_boot_param->initrd_size;
316 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n",
317 initrd_start, ia64_boot_param->initrd_size);
318 }
319 #endif
320 }
322 static void __init
323 io_port_init (void)
324 {
325 unsigned long phys_iobase;
327 /*
328 * Set `iobase' based on the EFI memory map or, failing that, the
329 * value firmware left in ar.k0.
330 *
331 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute
332 * the port's virtual address, so ia32_load_state() loads it with a
333 * user virtual address. But in ia64 mode, glibc uses the
334 * *physical* address in ar.k0 to mmap the appropriate area from
335 * /dev/mem, and the inX()/outX() interfaces use MMIO. In both
336 * cases, user-mode can only use the legacy 0-64K I/O port space.
337 *
338 * ar.k0 is not involved in kernel I/O port accesses, which can use
339 * any of the I/O port spaces and are done via MMIO using the
340 * virtual mmio_base from the appropriate io_space[].
341 */
342 phys_iobase = efi_get_iobase();
343 if (!phys_iobase) {
344 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE);
345 printk(KERN_INFO "No I/O port range found in EFI memory map, "
346 "falling back to AR.KR0 (0x%lx)\n", phys_iobase);
347 }
348 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0);
349 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase));
351 /* setup legacy IO port space */
352 io_space[0].mmio_base = ia64_iobase;
353 io_space[0].sparse = 1;
354 num_io_spaces = 1;
355 }
357 /**
358 * early_console_setup - setup debugging console
359 *
360 * Consoles started here require little enough setup that we can start using
361 * them very early in the boot process, either right after the machine
362 * vector initialization, or even before if the drivers can detect their hw.
363 *
364 * Returns non-zero if a console couldn't be setup.
365 */
366 static inline int __init
367 early_console_setup (char *cmdline)
368 {
369 int earlycons = 0;
371 #ifdef CONFIG_XEN
372 #ifndef CONFIG_IA64_HP_SIM
373 if (is_running_on_xen()) {
374 extern struct console hpsim_cons;
375 hpsim_cons.flags |= CON_BOOT;
376 register_console(&hpsim_cons);
377 earlycons++;
378 }
379 #endif
380 #endif
381 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE
382 {
383 extern int sn_serial_console_early_setup(void);
384 if (!sn_serial_console_early_setup())
385 earlycons++;
386 }
387 #endif
388 #ifdef CONFIG_EFI_PCDP
389 if (!efi_setup_pcdp_console(cmdline))
390 earlycons++;
391 #endif
392 #ifdef CONFIG_SERIAL_8250_CONSOLE
393 if (!early_serial_console_init(cmdline))
394 earlycons++;
395 #endif
397 return (earlycons) ? 0 : -1;
398 }
400 static inline void
401 mark_bsp_online (void)
402 {
403 #ifdef CONFIG_SMP
404 /* If we register an early console, allow CPU 0 to printk */
405 cpu_set(smp_processor_id(), cpu_online_map);
406 #endif
407 }
409 #ifdef CONFIG_SMP
410 static void __init
411 check_for_logical_procs (void)
412 {
413 pal_logical_to_physical_t info;
414 s64 status;
416 status = ia64_pal_logical_to_phys(0, &info);
417 if (status == -1) {
418 printk(KERN_INFO "No logical to physical processor mapping "
419 "available\n");
420 return;
421 }
422 if (status) {
423 printk(KERN_ERR "ia64_pal_logical_to_phys failed with %ld\n",
424 status);
425 return;
426 }
427 /*
428 * Total number of siblings that BSP has. Though not all of them
429 * may have booted successfully. The correct number of siblings
430 * booted is in info.overview_num_log.
431 */
432 smp_num_siblings = info.overview_tpc;
433 smp_num_cpucores = info.overview_cpp;
434 }
435 #endif
437 static __initdata int nomca;
438 static __init int setup_nomca(char *s)
439 {
440 nomca = 1;
441 return 0;
442 }
443 early_param("nomca", setup_nomca);
445 void __init
446 setup_arch (char **cmdline_p)
447 {
448 unw_init();
450 #ifdef CONFIG_XEN
451 if (is_running_on_xen()) {
452 /* Must be done before any hypercall. */
453 xencomm_init();
455 setup_xen_features();
456 /* Register a call for panic conditions. */
457 atomic_notifier_chain_register(&panic_notifier_list,
458 &xen_panic_block);
459 }
460 #endif
462 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist);
464 *cmdline_p = __va(ia64_boot_param->command_line);
465 strlcpy(saved_command_line, *cmdline_p, COMMAND_LINE_SIZE);
467 efi_init();
468 io_port_init();
470 parse_early_param();
472 #ifdef CONFIG_IA64_GENERIC
473 machvec_init(NULL);
474 #endif
476 if (early_console_setup(*cmdline_p) == 0)
477 mark_bsp_online();
479 #ifdef CONFIG_ACPI
480 /* Initialize the ACPI boot-time table parser */
481 acpi_table_init();
482 # ifdef CONFIG_ACPI_NUMA
483 acpi_numa_init();
484 # endif
485 #else
486 # ifdef CONFIG_SMP
487 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */
488 # endif
489 #endif /* CONFIG_APCI_BOOT */
491 find_memory();
493 /* process SAL system table: */
494 ia64_sal_init(__va(efi.sal_systab));
496 ia64_setup_printk_clock();
498 #ifdef CONFIG_SMP
499 cpu_physical_id(0) = hard_smp_processor_id();
501 cpu_set(0, cpu_sibling_map[0]);
502 cpu_set(0, cpu_core_map[0]);
504 check_for_logical_procs();
505 if (smp_num_cpucores > 1)
506 printk(KERN_INFO
507 "cpu package is Multi-Core capable: number of cores=%d\n",
508 smp_num_cpucores);
509 if (smp_num_siblings > 1)
510 printk(KERN_INFO
511 "cpu package is Multi-Threading capable: number of siblings=%d\n",
512 smp_num_siblings);
513 #endif
515 cpu_init(); /* initialize the bootstrap CPU */
516 mmu_context_init(); /* initialize context_id bitmap */
518 #ifdef CONFIG_ACPI
519 acpi_boot_init();
520 #endif
522 #ifdef CONFIG_VT
523 if (!conswitchp) {
524 # if defined(CONFIG_DUMMY_CONSOLE)
525 conswitchp = &dummy_con;
526 # endif
527 # if defined(CONFIG_VGA_CONSOLE)
528 /*
529 * Non-legacy systems may route legacy VGA MMIO range to system
530 * memory. vga_con probes the MMIO hole, so memory looks like
531 * a VGA device to it. The EFI memory map can tell us if it's
532 * memory so we can avoid this problem.
533 */
534 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY)
535 conswitchp = &vga_con;
536 # endif
537 }
538 #ifdef CONFIG_XEN
539 if (is_running_on_xen()) {
540 shared_info_t *s = HYPERVISOR_shared_info;
542 xen_start_info = __va(s->arch.start_info_pfn << PAGE_SHIFT);
544 printk("Running on Xen! start_info_pfn=0x%lx nr_pages=%ld "
545 "flags=0x%x\n", s->arch.start_info_pfn,
546 xen_start_info->nr_pages, xen_start_info->flags);
548 if (!is_initial_xendomain()) {
549 #if !defined(CONFIG_VT) || !defined(CONFIG_DUMMY_CONSOLE)
550 conswitchp = NULL;
551 #endif
552 }
553 }
554 xencons_early_setup();
555 #endif
556 #endif
559 /* enable IA-64 Machine Check Abort Handling unless disabled */
560 if (!nomca)
561 ia64_mca_init();
563 platform_setup(cmdline_p);
564 paging_init();
565 #ifdef CONFIG_XEN
566 contiguous_bitmap_init(max_pfn);
567 #endif
568 }
570 /*
571 * Display cpu info for all cpu's.
572 */
573 static int
574 show_cpuinfo (struct seq_file *m, void *v)
575 {
576 #ifdef CONFIG_SMP
577 # define lpj c->loops_per_jiffy
578 # define cpunum c->cpu
579 #else
580 # define lpj loops_per_jiffy
581 # define cpunum 0
582 #endif
583 static struct {
584 unsigned long mask;
585 const char *feature_name;
586 } feature_bits[] = {
587 { 1UL << 0, "branchlong" },
588 { 1UL << 1, "spontaneous deferral"},
589 { 1UL << 2, "16-byte atomic ops" }
590 };
591 char family[32], features[128], *cp, sep;
592 struct cpuinfo_ia64 *c = v;
593 unsigned long mask;
594 unsigned long proc_freq;
595 int i;
597 mask = c->features;
599 switch (c->family) {
600 case 0x07: memcpy(family, "Itanium", 8); break;
601 case 0x1f: memcpy(family, "Itanium 2", 10); break;
602 default: sprintf(family, "%u", c->family); break;
603 }
605 /* build the feature string: */
606 memcpy(features, " standard", 10);
607 cp = features;
608 sep = 0;
609 for (i = 0; i < (int) ARRAY_SIZE(feature_bits); ++i) {
610 if (mask & feature_bits[i].mask) {
611 if (sep)
612 *cp++ = sep;
613 sep = ',';
614 *cp++ = ' ';
615 strcpy(cp, feature_bits[i].feature_name);
616 cp += strlen(feature_bits[i].feature_name);
617 mask &= ~feature_bits[i].mask;
618 }
619 }
620 if (mask) {
621 /* print unknown features as a hex value: */
622 if (sep)
623 *cp++ = sep;
624 sprintf(cp, " 0x%lx", mask);
625 }
627 proc_freq = cpufreq_quick_get(cpunum);
628 if (!proc_freq)
629 proc_freq = c->proc_freq / 1000;
631 seq_printf(m,
632 "processor : %d\n"
633 "vendor : %s\n"
634 "arch : IA-64\n"
635 "family : %s\n"
636 "model : %u\n"
637 "revision : %u\n"
638 "archrev : %u\n"
639 "features :%s\n" /* don't change this---it _is_ right! */
640 "cpu number : %lu\n"
641 "cpu regs : %u\n"
642 "cpu MHz : %lu.%06lu\n"
643 "itc MHz : %lu.%06lu\n"
644 "BogoMIPS : %lu.%02lu\n",
645 cpunum, c->vendor, family, c->model, c->revision, c->archrev,
646 features, c->ppn, c->number,
647 proc_freq / 1000, proc_freq % 1000,
648 c->itc_freq / 1000000, c->itc_freq % 1000000,
649 lpj*HZ/500000, (lpj*HZ/5000) % 100);
650 #ifdef CONFIG_SMP
651 seq_printf(m, "siblings : %u\n", cpus_weight(cpu_core_map[cpunum]));
652 if (c->threads_per_core > 1 || c->cores_per_socket > 1)
653 seq_printf(m,
654 "physical id: %u\n"
655 "core id : %u\n"
656 "thread id : %u\n",
657 c->socket_id, c->core_id, c->thread_id);
658 #endif
659 seq_printf(m,"\n");
661 return 0;
662 }
664 static void *
665 c_start (struct seq_file *m, loff_t *pos)
666 {
667 #ifdef CONFIG_SMP
668 while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map))
669 ++*pos;
670 #endif
671 return *pos < NR_CPUS ? cpu_data(*pos) : NULL;
672 }
674 static void *
675 c_next (struct seq_file *m, void *v, loff_t *pos)
676 {
677 ++*pos;
678 return c_start(m, pos);
679 }
681 static void
682 c_stop (struct seq_file *m, void *v)
683 {
684 }
686 struct seq_operations cpuinfo_op = {
687 .start = c_start,
688 .next = c_next,
689 .stop = c_stop,
690 .show = show_cpuinfo
691 };
693 static void __cpuinit
694 identify_cpu (struct cpuinfo_ia64 *c)
695 {
696 union {
697 unsigned long bits[5];
698 struct {
699 /* id 0 & 1: */
700 char vendor[16];
702 /* id 2 */
703 u64 ppn; /* processor serial number */
705 /* id 3: */
706 unsigned number : 8;
707 unsigned revision : 8;
708 unsigned model : 8;
709 unsigned family : 8;
710 unsigned archrev : 8;
711 unsigned reserved : 24;
713 /* id 4: */
714 u64 features;
715 } field;
716 } cpuid;
717 pal_vm_info_1_u_t vm1;
718 pal_vm_info_2_u_t vm2;
719 pal_status_t status;
720 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */
721 int i;
723 for (i = 0; i < 5; ++i)
724 cpuid.bits[i] = ia64_get_cpuid(i);
726 memcpy(c->vendor, cpuid.field.vendor, 16);
727 #ifdef CONFIG_SMP
728 c->cpu = smp_processor_id();
730 /* below default values will be overwritten by identify_siblings()
731 * for Multi-Threading/Multi-Core capable cpu's
732 */
733 c->threads_per_core = c->cores_per_socket = c->num_log = 1;
734 c->socket_id = -1;
736 identify_siblings(c);
737 #endif
738 c->ppn = cpuid.field.ppn;
739 c->number = cpuid.field.number;
740 c->revision = cpuid.field.revision;
741 c->model = cpuid.field.model;
742 c->family = cpuid.field.family;
743 c->archrev = cpuid.field.archrev;
744 c->features = cpuid.field.features;
746 status = ia64_pal_vm_summary(&vm1, &vm2);
747 if (status == PAL_STATUS_SUCCESS) {
748 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb;
749 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size;
750 }
751 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1));
752 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1));
753 }
755 void
756 setup_per_cpu_areas (void)
757 {
758 /* start_kernel() requires this... */
759 #ifdef CONFIG_ACPI_HOTPLUG_CPU
760 prefill_possible_map();
761 #endif
762 }
764 /*
765 * Calculate the max. cache line size.
766 *
767 * In addition, the minimum of the i-cache stride sizes is calculated for
768 * "flush_icache_range()".
769 */
770 static void __cpuinit
771 get_max_cacheline_size (void)
772 {
773 unsigned long line_size, max = 1;
774 unsigned int cache_size = 0;
775 u64 l, levels, unique_caches;
776 pal_cache_config_info_t cci;
777 s64 status;
779 status = ia64_pal_cache_summary(&levels, &unique_caches);
780 if (status != 0) {
781 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
782 __FUNCTION__, status);
783 max = SMP_CACHE_BYTES;
784 /* Safest setup for "flush_icache_range()" */
785 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT;
786 goto out;
787 }
789 for (l = 0; l < levels; ++l) {
790 status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2,
791 &cci);
792 if (status != 0) {
793 printk(KERN_ERR
794 "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n",
795 __FUNCTION__, l, status);
796 max = SMP_CACHE_BYTES;
797 /* The safest setup for "flush_icache_range()" */
798 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
799 cci.pcci_unified = 1;
800 }
801 line_size = 1 << cci.pcci_line_size;
802 if (line_size > max)
803 max = line_size;
804 if (cache_size < cci.pcci_cache_size)
805 cache_size = cci.pcci_cache_size;
806 if (!cci.pcci_unified) {
807 status = ia64_pal_cache_config_info(l,
808 /* cache_type (instruction)= */ 1,
809 &cci);
810 if (status != 0) {
811 printk(KERN_ERR
812 "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n",
813 __FUNCTION__, l, status);
814 /* The safest setup for "flush_icache_range()" */
815 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
816 }
817 }
818 if (cci.pcci_stride < ia64_i_cache_stride_shift)
819 ia64_i_cache_stride_shift = cci.pcci_stride;
820 }
821 out:
822 #ifdef CONFIG_SMP
823 max_cache_size = max(max_cache_size, cache_size);
824 #endif
825 if (max > ia64_max_cacheline_size)
826 ia64_max_cacheline_size = max;
827 }
829 /*
830 * cpu_init() initializes state that is per-CPU. This function acts
831 * as a 'CPU state barrier', nothing should get across.
832 */
833 void __cpuinit
834 cpu_init (void)
835 {
836 extern void __cpuinit ia64_mmu_init (void *);
837 unsigned long num_phys_stacked;
838 pal_vm_info_2_u_t vmi;
839 unsigned int max_ctx;
840 struct cpuinfo_ia64 *cpu_info;
841 void *cpu_data;
843 cpu_data = per_cpu_init();
845 /*
846 * We set ar.k3 so that assembly code in MCA handler can compute
847 * physical addresses of per cpu variables with a simple:
848 * phys = ar.k3 + &per_cpu_var
849 */
850 ia64_set_kr(IA64_KR_PER_CPU_DATA,
851 ia64_tpa(cpu_data) - (long) __per_cpu_start);
853 get_max_cacheline_size();
855 /*
856 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called
857 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it
858 * depends on the data returned by identify_cpu(). We break the dependency by
859 * accessing cpu_data() through the canonical per-CPU address.
860 */
861 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start);
862 identify_cpu(cpu_info);
864 #ifdef CONFIG_MCKINLEY
865 {
866 # define FEATURE_SET 16
867 struct ia64_pal_retval iprv;
869 if (cpu_info->family == 0x1f) {
870 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0);
871 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80))
872 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES,
873 (iprv.v1 | 0x80), FEATURE_SET, 0);
874 }
875 }
876 #endif
878 /* Clear the stack memory reserved for pt_regs: */
879 memset(task_pt_regs(current), 0, sizeof(struct pt_regs));
881 ia64_set_kr(IA64_KR_FPU_OWNER, 0);
883 /*
884 * Initialize the page-table base register to a global
885 * directory with all zeroes. This ensure that we can handle
886 * TLB-misses to user address-space even before we created the
887 * first user address-space. This may happen, e.g., due to
888 * aggressive use of lfetch.fault.
889 */
890 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page)));
892 /*
893 * Initialize default control register to defer speculative faults except
894 * for those arising from TLB misses, which are not deferred. The
895 * kernel MUST NOT depend on a particular setting of these bits (in other words,
896 * the kernel must have recovery code for all speculative accesses). Turn on
897 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps
898 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll
899 * be fine).
900 */
901 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR
902 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC));
903 atomic_inc(&init_mm.mm_count);
904 current->active_mm = &init_mm;
905 if (current->mm)
906 BUG();
908 ia64_mmu_init(ia64_imva(cpu_data));
909 ia64_mca_cpu_init(ia64_imva(cpu_data));
911 #ifdef CONFIG_IA32_SUPPORT
912 ia32_cpu_init();
913 #endif
915 /* Clear ITC to eliminiate sched_clock() overflows in human time. */
916 ia64_set_itc(0);
918 /* disable all local interrupt sources: */
919 ia64_set_itv(1 << 16);
920 ia64_set_lrr0(1 << 16);
921 ia64_set_lrr1(1 << 16);
922 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16);
923 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16);
925 /* clear TPR & XTP to enable all interrupt classes: */
926 ia64_setreg(_IA64_REG_CR_TPR, 0);
927 #ifdef CONFIG_SMP
928 normal_xtp();
929 #endif
931 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */
932 if (ia64_pal_vm_summary(NULL, &vmi) == 0)
933 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1;
934 else {
935 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n");
936 max_ctx = (1U << 15) - 1; /* use architected minimum */
937 }
938 while (max_ctx < ia64_ctx.max_ctx) {
939 unsigned int old = ia64_ctx.max_ctx;
940 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old)
941 break;
942 }
944 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) {
945 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical "
946 "stacked regs\n");
947 num_phys_stacked = 96;
948 }
949 /* size of physical stacked register partition plus 8 bytes: */
950 __get_cpu_var(ia64_phys_stacked_size_p8) = num_phys_stacked*8 + 8;
951 platform_cpu_init();
953 #ifdef CONFIG_XEN
954 /* Need to be moved into platform_cpu_init later */
955 if (is_running_on_xen()) {
956 extern void xen_smp_intr_init(void);
957 xen_smp_intr_init();
958 }
959 #endif
961 pm_idle = default_idle;
962 }
964 /*
965 * On SMP systems, when the scheduler does migration-cost autodetection,
966 * it needs a way to flush as much of the CPU's caches as possible.
967 */
968 void sched_cacheflush(void)
969 {
970 ia64_sal_cache_flush(3);
971 }
973 void __init
974 check_bugs (void)
975 {
976 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles,
977 (unsigned long) __end___mckinley_e9_bundles);
978 }
980 static int __init run_dmi_scan(void)
981 {
982 dmi_scan_machine();
983 return 0;
984 }
985 core_initcall(run_dmi_scan);