direct-io.hg

view xen/arch/x86/mtrr/generic.c @ 3379:275b77086005

bitkeeper revision 1.1159.213.2 (41dc5bb8NoFeyC8xMcZdstILsQ-Tqg)

patch from Leendert van Doorn <leendert@watson.ibm.com>

Hyperthreading on VMX is broken in the xeno-unstable.bk tree. The diff
below fixes this.
It turns out that the mtrr code clears too many bits, some of them cause
Xen to crash. Being a bit more precise fixes the problem.
author iap10@labyrinth.cl.cam.ac.uk
date Wed Jan 05 21:27:20 2005 +0000 (2005-01-05)
parents c23dd7ec1f54
children e17a946c7a91
line source
1 /* This only handles 32bit MTRR on 32bit hosts. This is strictly wrong
2 because MTRRs can span upto 40 bits (36bits on most modern x86) */
3 #include <xen/init.h>
4 #include <xen/slab.h>
5 #include <xen/mm.h>
6 #include <asm/io.h>
7 #include <asm/mtrr.h>
8 #include <asm/msr.h>
9 #include <asm/system.h>
10 #include <asm/cpufeature.h>
11 //#include <asm/tlbflush.h>
12 #include "mtrr.h"
14 struct mtrr_state {
15 struct mtrr_var_range *var_ranges;
16 mtrr_type fixed_ranges[NUM_FIXED_RANGES];
17 unsigned char enabled;
18 mtrr_type def_type;
19 };
21 static unsigned long smp_changes_mask;
22 struct mtrr_state mtrr_state = {};
25 /* Get the MSR pair relating to a var range */
26 static void __init
27 get_mtrr_var_range(unsigned int index, struct mtrr_var_range *vr)
28 {
29 rdmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi);
30 rdmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi);
31 }
33 static void __init
34 get_fixed_ranges(mtrr_type * frs)
35 {
36 unsigned int *p = (unsigned int *) frs;
37 int i;
39 rdmsr(MTRRfix64K_00000_MSR, p[0], p[1]);
41 for (i = 0; i < 2; i++)
42 rdmsr(MTRRfix16K_80000_MSR + i, p[2 + i * 2], p[3 + i * 2]);
43 for (i = 0; i < 8; i++)
44 rdmsr(MTRRfix4K_C0000_MSR + i, p[6 + i * 2], p[7 + i * 2]);
45 }
47 /* Grab all of the MTRR state for this CPU into *state */
48 void __init get_mtrr_state(void)
49 {
50 unsigned int i;
51 struct mtrr_var_range *vrs;
52 unsigned lo, dummy;
54 if (!mtrr_state.var_ranges) {
55 mtrr_state.var_ranges = xmalloc(num_var_ranges * sizeof (struct mtrr_var_range));
56 if (!mtrr_state.var_ranges)
57 return;
58 }
59 vrs = mtrr_state.var_ranges;
61 for (i = 0; i < num_var_ranges; i++)
62 get_mtrr_var_range(i, &vrs[i]);
63 get_fixed_ranges(mtrr_state.fixed_ranges);
65 rdmsr(MTRRdefType_MSR, lo, dummy);
66 mtrr_state.def_type = (lo & 0xff);
67 mtrr_state.enabled = (lo & 0xc00) >> 10;
68 }
70 /* Free resources associated with a struct mtrr_state */
71 void __init finalize_mtrr_state(void)
72 {
73 if (mtrr_state.var_ranges)
74 xfree(mtrr_state.var_ranges);
75 mtrr_state.var_ranges = NULL;
76 }
78 /* Some BIOS's are fucked and don't set all MTRRs the same! */
79 void __init mtrr_state_warn(void)
80 {
81 unsigned long mask = smp_changes_mask;
83 if (!mask)
84 return;
85 if (mask & MTRR_CHANGE_MASK_FIXED)
86 printk(KERN_WARNING "mtrr: your CPUs had inconsistent fixed MTRR settings\n");
87 if (mask & MTRR_CHANGE_MASK_VARIABLE)
88 printk(KERN_WARNING "mtrr: your CPUs had inconsistent variable MTRR settings\n");
89 if (mask & MTRR_CHANGE_MASK_DEFTYPE)
90 printk(KERN_WARNING "mtrr: your CPUs had inconsistent MTRRdefType settings\n");
91 printk(KERN_INFO "mtrr: probably your BIOS does not setup all CPUs.\n");
92 printk(KERN_INFO "mtrr: corrected configuration.\n");
93 }
96 int generic_get_free_region(unsigned long base, unsigned long size)
97 /* [SUMMARY] Get a free MTRR.
98 <base> The starting (base) address of the region.
99 <size> The size (in bytes) of the region.
100 [RETURNS] The index of the region on success, else -1 on error.
101 */
102 {
103 int i, max;
104 mtrr_type ltype;
105 unsigned long lbase;
106 unsigned lsize;
108 max = num_var_ranges;
109 for (i = 0; i < max; ++i) {
110 mtrr_if->get(i, &lbase, &lsize, &ltype);
111 if (lsize == 0)
112 return i;
113 }
114 return -ENOSPC;
115 }
117 void generic_get_mtrr(unsigned int reg, unsigned long *base,
118 unsigned int *size, mtrr_type * type)
119 {
120 unsigned int mask_lo, mask_hi, base_lo, base_hi;
122 rdmsr(MTRRphysMask_MSR(reg), mask_lo, mask_hi);
123 if ((mask_lo & 0x800) == 0) {
124 /* Invalid (i.e. free) range */
125 *base = 0;
126 *size = 0;
127 *type = 0;
128 return;
129 }
131 rdmsr(MTRRphysBase_MSR(reg), base_lo, base_hi);
133 /* Work out the shifted address mask. */
134 mask_lo = size_or_mask | mask_hi << (32 - PAGE_SHIFT)
135 | mask_lo >> PAGE_SHIFT;
137 /* This works correctly if size is a power of two, i.e. a
138 contiguous range. */
139 *size = -mask_lo;
140 *base = base_hi << (32 - PAGE_SHIFT) | base_lo >> PAGE_SHIFT;
141 *type = base_lo & 0xff;
142 }
144 static int set_fixed_ranges(mtrr_type * frs)
145 {
146 unsigned int *p = (unsigned int *) frs;
147 int changed = FALSE;
148 int i;
149 unsigned int lo, hi;
151 rdmsr(MTRRfix64K_00000_MSR, lo, hi);
152 if (p[0] != lo || p[1] != hi) {
153 wrmsr(MTRRfix64K_00000_MSR, p[0], p[1]);
154 changed = TRUE;
155 }
157 for (i = 0; i < 2; i++) {
158 rdmsr(MTRRfix16K_80000_MSR + i, lo, hi);
159 if (p[2 + i * 2] != lo || p[3 + i * 2] != hi) {
160 wrmsr(MTRRfix16K_80000_MSR + i, p[2 + i * 2],
161 p[3 + i * 2]);
162 changed = TRUE;
163 }
164 }
166 for (i = 0; i < 8; i++) {
167 rdmsr(MTRRfix4K_C0000_MSR + i, lo, hi);
168 if (p[6 + i * 2] != lo || p[7 + i * 2] != hi) {
169 wrmsr(MTRRfix4K_C0000_MSR + i, p[6 + i * 2],
170 p[7 + i * 2]);
171 changed = TRUE;
172 }
173 }
174 return changed;
175 }
177 /* Set the MSR pair relating to a var range. Returns TRUE if
178 changes are made */
179 static int set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr)
180 {
181 unsigned int lo, hi;
182 int changed = FALSE;
184 rdmsr(MTRRphysBase_MSR(index), lo, hi);
185 if ((vr->base_lo & 0xfffff0ffUL) != (lo & 0xfffff0ffUL)
186 || (vr->base_hi & 0xfUL) != (hi & 0xfUL)) {
187 wrmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi);
188 changed = TRUE;
189 }
191 rdmsr(MTRRphysMask_MSR(index), lo, hi);
193 if ((vr->mask_lo & 0xfffff800UL) != (lo & 0xfffff800UL)
194 || (vr->mask_hi & 0xfUL) != (hi & 0xfUL)) {
195 wrmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi);
196 changed = TRUE;
197 }
198 return changed;
199 }
201 static unsigned long set_mtrr_state(u32 deftype_lo, u32 deftype_hi)
202 /* [SUMMARY] Set the MTRR state for this CPU.
203 <state> The MTRR state information to read.
204 <ctxt> Some relevant CPU context.
205 [NOTE] The CPU must already be in a safe state for MTRR changes.
206 [RETURNS] 0 if no changes made, else a mask indication what was changed.
207 */
208 {
209 unsigned int i;
210 unsigned long change_mask = 0;
212 for (i = 0; i < num_var_ranges; i++)
213 if (set_mtrr_var_ranges(i, &mtrr_state.var_ranges[i]))
214 change_mask |= MTRR_CHANGE_MASK_VARIABLE;
216 if (set_fixed_ranges(mtrr_state.fixed_ranges))
217 change_mask |= MTRR_CHANGE_MASK_FIXED;
219 /* Set_mtrr_restore restores the old value of MTRRdefType,
220 so to set it we fiddle with the saved value */
221 if ((deftype_lo & 0xff) != mtrr_state.def_type
222 || ((deftype_lo & 0xc00) >> 10) != mtrr_state.enabled) {
223 deftype_lo |= (mtrr_state.def_type | mtrr_state.enabled << 10);
224 change_mask |= MTRR_CHANGE_MASK_DEFTYPE;
225 }
227 return change_mask;
228 }
231 static unsigned long cr4 = 0;
232 static u32 deftype_lo, deftype_hi;
233 static spinlock_t set_atomicity_lock = SPIN_LOCK_UNLOCKED;
235 static void prepare_set(void)
236 {
237 unsigned long cr0;
239 /* Note that this is not ideal, since the cache is only flushed/disabled
240 for this CPU while the MTRRs are changed, but changing this requires
241 more invasive changes to the way the kernel boots */
242 spin_lock(&set_atomicity_lock);
244 /* Enter the no-fill (CD=1, NW=0) cache mode and flush caches. */
245 cr0 = read_cr0() | 0x40000000; /* set CD flag */
246 wbinvd();
247 write_cr0(cr0);
248 wbinvd();
250 /* Save value of CR4 and clear Page Global Enable (bit 7) */
251 if ( cpu_has_pge ) {
252 cr4 = read_cr4();
253 write_cr4(cr4 & ~X86_CR4_PGE);
254 }
256 /* Flush all TLBs via a mov %cr3, %reg; mov %reg, %cr3 */
257 __flush_tlb();
259 /* Save MTRR state */
260 rdmsr(MTRRdefType_MSR, deftype_lo, deftype_hi);
262 /* Disable MTRRs, and set the default type to uncached */
263 wrmsr(MTRRdefType_MSR, deftype_lo & 0xf300UL, deftype_hi);
264 }
266 static void post_set(void)
267 {
268 /* Flush caches and TLBs */
269 wbinvd();
270 __flush_tlb();
272 /* Intel (P6) standard MTRRs */
273 wrmsr(MTRRdefType_MSR, deftype_lo, deftype_hi);
275 /* Enable caches */
276 write_cr0(read_cr0() & 0xbfffffff);
278 /* Restore value of CR4 */
279 if ( cpu_has_pge )
280 write_cr4(cr4);
281 spin_unlock(&set_atomicity_lock);
282 }
284 static void generic_set_all(void)
285 {
286 unsigned long mask, count;
288 prepare_set();
290 /* Actually set the state */
291 mask = set_mtrr_state(deftype_lo,deftype_hi);
293 post_set();
295 /* Use the atomic bitops to update the global mask */
296 for (count = 0; count < sizeof mask * 8; ++count) {
297 if (mask & 0x01)
298 set_bit(count, &smp_changes_mask);
299 mask >>= 1;
300 }
302 }
304 static void generic_set_mtrr(unsigned int reg, unsigned long base,
305 unsigned long size, mtrr_type type)
306 /* [SUMMARY] Set variable MTRR register on the local CPU.
307 <reg> The register to set.
308 <base> The base address of the region.
309 <size> The size of the region. If this is 0 the region is disabled.
310 <type> The type of the region.
311 <do_safe> If TRUE, do the change safely. If FALSE, safety measures should
312 be done externally.
313 [RETURNS] Nothing.
314 */
315 {
316 prepare_set();
318 if (size == 0) {
319 /* The invalid bit is kept in the mask, so we simply clear the
320 relevant mask register to disable a range. */
321 wrmsr(MTRRphysMask_MSR(reg), 0, 0);
322 } else {
323 wrmsr(MTRRphysBase_MSR(reg), base << PAGE_SHIFT | type,
324 (base & size_and_mask) >> (32 - PAGE_SHIFT));
325 wrmsr(MTRRphysMask_MSR(reg), -size << PAGE_SHIFT | 0x800,
326 (-size & size_and_mask) >> (32 - PAGE_SHIFT));
327 }
329 post_set();
330 }
332 int generic_validate_add_page(unsigned long base, unsigned long size, unsigned int type)
333 {
334 unsigned long lbase, last;
336 /* For Intel PPro stepping <= 7, must be 4 MiB aligned
337 and not touch 0x70000000->0x7003FFFF */
338 if (is_cpu(INTEL) && boot_cpu_data.x86 == 6 &&
339 boot_cpu_data.x86_model == 1 &&
340 boot_cpu_data.x86_mask <= 7) {
341 if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) {
342 printk(KERN_WARNING "mtrr: base(0x%lx000) is not 4 MiB aligned\n", base);
343 return -EINVAL;
344 }
345 if (!(base + size < 0x70000000 || base > 0x7003FFFF) &&
346 (type == MTRR_TYPE_WRCOMB
347 || type == MTRR_TYPE_WRBACK)) {
348 printk(KERN_WARNING "mtrr: writable mtrr between 0x70000000 and 0x7003FFFF may hang the CPU.\n");
349 return -EINVAL;
350 }
351 }
353 if (base + size < 0x100) {
354 printk(KERN_WARNING "mtrr: cannot set region below 1 MiB (0x%lx000,0x%lx000)\n",
355 base, size);
356 return -EINVAL;
357 }
358 /* Check upper bits of base and last are equal and lower bits are 0
359 for base and 1 for last */
360 last = base + size - 1;
361 for (lbase = base; !(lbase & 1) && (last & 1);
362 lbase = lbase >> 1, last = last >> 1) ;
363 if (lbase != last) {
364 printk(KERN_WARNING "mtrr: base(0x%lx000) is not aligned on a size(0x%lx000) boundary\n",
365 base, size);
366 return -EINVAL;
367 }
368 return 0;
369 }
372 int generic_have_wrcomb(void)
373 {
374 unsigned long config, dummy;
375 rdmsr(MTRRcap_MSR, config, dummy);
376 return (config & (1 << 10));
377 }
379 int positive_have_wrcomb(void)
380 {
381 return 1;
382 }
384 /* generic structure...
385 */
386 struct mtrr_ops generic_mtrr_ops = {
387 .use_intel_if = 1,
388 .set_all = generic_set_all,
389 .get = generic_get_mtrr,
390 .get_free_region = generic_get_free_region,
391 .set = generic_set_mtrr,
392 .validate_add_page = generic_validate_add_page,
393 .have_wrcomb = generic_have_wrcomb,
394 };