xen-unstable.hg

changeset 10738:42aa63188a88

IA64-specific code for new Qemu
Due to some ia64 patches aren't checked into xen-unstable.hg.
I reversed related logic.

Signed-off-by: Zhang xiantao <xiantao.zhang@intel.com>
Signed-off-by: Christian Limpach <Christian.Limpach@xensource.com>
author chris@kneesaa.uk.xensource.com
date Wed Jul 26 13:41:10 2006 +0100 (2006-07-26)
parents 7654157278f1
children 060025203f54
files tools/ioemu/cpu-all.h tools/ioemu/exec-all.h tools/ioemu/hw/iommu.c tools/ioemu/patches/domain-timeoffset tools/ioemu/patches/ioemu-ia64 tools/ioemu/patches/series tools/ioemu/patches/vnc-fixes tools/ioemu/patches/vnc-start-vncviewer tools/ioemu/target-i386-dm/cpu.h tools/ioemu/target-i386-dm/exec-dm.c tools/ioemu/vl.c
line diff
     1.1 --- a/tools/ioemu/cpu-all.h	Wed Jul 26 13:36:13 2006 +0100
     1.2 +++ b/tools/ioemu/cpu-all.h	Wed Jul 26 13:41:10 2006 +0100
     1.3 @@ -835,6 +835,31 @@ static __inline__ void atomic_clear_bit(
     1.4                  :"=m" (*(volatile long *)addr)
     1.5                  :"dIr" (nr));
     1.6  }
     1.7 +#elif defined(__ia64__)
     1.8 +#include "ia64_intrinsic.h"
     1.9 +#define atomic_set_bit(nr, addr) ({					\
    1.10 +	typeof(*addr) bit, old, new;					\
    1.11 +	volatile typeof(*addr) *m;					\
    1.12 +									\
    1.13 +	m = (volatile typeof(*addr)*)(addr + nr / (8*sizeof(*addr)));	\
    1.14 +	bit = 1 << (nr % (8*sizeof(*addr)));				\
    1.15 +	do {								\
    1.16 +		old = *m;						\
    1.17 +		new = old | bit;					\
    1.18 +	} while (cmpxchg_acq(m, old, new) != old);			\
    1.19 +})
    1.20 +
    1.21 +#define atomic_clear_bit(nr, addr) ({					\
    1.22 +	typeof(*addr) bit, old, new;					\
    1.23 +	volatile typeof(*addr) *m;					\
    1.24 +									\
    1.25 +	m = (volatile typeof(*addr)*)(addr + nr / (8*sizeof(*addr)));	\
    1.26 +	bit = ~(1 << (nr % (8*sizeof(*addr))));				\
    1.27 +	do {								\
    1.28 +		old = *m;						\
    1.29 +		new = old & bit;					\
    1.30 +	} while (cmpxchg_acq(m, old, new) != old);			\
    1.31 +})
    1.32  #endif
    1.33  
    1.34  /* memory API */
     2.1 --- a/tools/ioemu/exec-all.h	Wed Jul 26 13:36:13 2006 +0100
     2.2 +++ b/tools/ioemu/exec-all.h	Wed Jul 26 13:41:10 2006 +0100
     2.3 @@ -391,6 +391,15 @@ static inline int testandset (int *p)
     2.4  }
     2.5  #endif
     2.6  
     2.7 +#ifdef __ia64__
     2.8 +#include "ia64_intrinsic.h"
     2.9 +static inline int testandset (int *p)
    2.10 +{
    2.11 +    uint32_t o = 0, n = 1;
    2.12 +    return (int)cmpxchg_acq(p, o, n);
    2.13 +}
    2.14 +#endif
    2.15 +
    2.16  #ifdef __s390__
    2.17  static inline int testandset (int *p)
    2.18  {
    2.19 @@ -462,12 +471,13 @@ static inline int testandset (int *p)
    2.20  }
    2.21  #endif
    2.22  
    2.23 -#ifdef __ia64
    2.24 -#include <ia64intrin.h>
    2.25 +#ifdef __ia64__
    2.26 +#include "ia64_intrinsic.h"
    2.27  
    2.28  static inline int testandset (int *p)
    2.29  {
    2.30 -    return __sync_lock_test_and_set (p, 1);
    2.31 +    uint32_t o = 0, n = 1;
    2.32 +    return (int)cmpxchg_acq(p, o, n);
    2.33  }
    2.34  #endif
    2.35  
     3.1 --- a/tools/ioemu/hw/iommu.c	Wed Jul 26 13:36:13 2006 +0100
     3.2 +++ b/tools/ioemu/hw/iommu.c	Wed Jul 26 13:41:10 2006 +0100
     3.3 @@ -82,7 +82,11 @@ do { printf("IOMMU: " fmt , ##args); } w
     3.4  #define IOPTE_VALID         0x00000002 /* IOPTE is valid */
     3.5  #define IOPTE_WAZ           0x00000001 /* Write as zeros */
     3.6  
     3.7 +#if defined(__i386__) || defined(__x86_64__)
     3.8  #define PAGE_SHIFT      12
     3.9 +#elif defined(__ia64__)
    3.10 +#define PAGE_SHIFT      14
    3.11 +#endif 
    3.12  #define PAGE_SIZE       (1 << PAGE_SHIFT)
    3.13  #define PAGE_MASK	(PAGE_SIZE - 1)
    3.14  
     4.1 --- a/tools/ioemu/patches/domain-timeoffset	Wed Jul 26 13:36:13 2006 +0100
     4.2 +++ b/tools/ioemu/patches/domain-timeoffset	Wed Jul 26 13:41:10 2006 +0100
     4.3 @@ -1,7 +1,7 @@
     4.4  Index: ioemu/hw/mc146818rtc.c
     4.5  ===================================================================
     4.6 ---- ioemu.orig/hw/mc146818rtc.c	2006-07-26 13:18:13.783025944 +0100
     4.7 -+++ ioemu/hw/mc146818rtc.c	2006-07-26 13:20:34.934314196 +0100
     4.8 +--- ioemu.orig/hw/mc146818rtc.c	2006-07-26 13:39:11.256088974 +0100
     4.9 ++++ ioemu/hw/mc146818rtc.c	2006-07-26 13:39:18.026364657 +0100
    4.10  @@ -178,10 +178,27 @@
    4.11       }
    4.12   }
    4.13 @@ -46,8 +46,8 @@ Index: ioemu/hw/mc146818rtc.c
    4.14   static void rtc_copy_date(RTCState *s)
    4.15  Index: ioemu/hw/pc.c
    4.16  ===================================================================
    4.17 ---- ioemu.orig/hw/pc.c	2006-07-26 13:20:34.463363339 +0100
    4.18 -+++ ioemu/hw/pc.c	2006-07-26 13:20:34.935314092 +0100
    4.19 +--- ioemu.orig/hw/pc.c	2006-07-26 13:39:17.773391722 +0100
    4.20 ++++ ioemu/hw/pc.c	2006-07-26 13:39:18.027364550 +0100
    4.21  @@ -151,7 +151,7 @@
    4.22   }
    4.23   
    4.24 @@ -117,8 +117,8 @@ Index: ioemu/hw/pc.c
    4.25   QEMUMachine pc_machine = {
    4.26  Index: ioemu/vl.c
    4.27  ===================================================================
    4.28 ---- ioemu.orig/vl.c	2006-07-26 13:20:34.812326925 +0100
    4.29 -+++ ioemu/vl.c	2006-07-26 13:20:34.937313883 +0100
    4.30 +--- ioemu.orig/vl.c	2006-07-26 13:39:17.903377815 +0100
    4.31 ++++ ioemu/vl.c	2006-07-26 13:39:18.029364336 +0100
    4.32  @@ -164,6 +164,8 @@
    4.33   
    4.34   int xc_handle;
    4.35 @@ -162,7 +162,7 @@ Index: ioemu/vl.c
    4.36               }
    4.37           }
    4.38       }
    4.39 -@@ -5963,7 +5971,8 @@
    4.40 +@@ -5992,7 +6000,8 @@
    4.41   
    4.42       machine->init(ram_size, vga_ram_size, boot_device,
    4.43                     ds, fd_filename, snapshot,
    4.44 @@ -174,8 +174,8 @@ Index: ioemu/vl.c
    4.45       qemu_mod_timer(gui_timer, qemu_get_clock(rt_clock));
    4.46  Index: ioemu/vl.h
    4.47  ===================================================================
    4.48 ---- ioemu.orig/vl.h	2006-07-26 13:20:34.467362921 +0100
    4.49 -+++ ioemu/vl.h	2006-07-26 13:20:34.938313779 +0100
    4.50 +--- ioemu.orig/vl.h	2006-07-26 13:39:17.778391187 +0100
    4.51 ++++ ioemu/vl.h	2006-07-26 13:39:18.030364229 +0100
    4.52  @@ -556,7 +556,7 @@
    4.53                                    int boot_device,
    4.54                DisplayState *ds, const char **fd_filename, int snapshot,
     5.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     5.2 +++ b/tools/ioemu/patches/ioemu-ia64	Wed Jul 26 13:41:10 2006 +0100
     5.3 @@ -0,0 +1,471 @@
     5.4 +Index: ioemu/hw/iommu.c
     5.5 +===================================================================
     5.6 +--- ioemu.orig/hw/iommu.c	2006-07-14 13:43:45.000000000 +0100
     5.7 ++++ ioemu/hw/iommu.c	2006-07-26 13:34:50.039997837 +0100
     5.8 +@@ -82,7 +82,11 @@
     5.9 + #define IOPTE_VALID         0x00000002 /* IOPTE is valid */
    5.10 + #define IOPTE_WAZ           0x00000001 /* Write as zeros */
    5.11 + 
    5.12 ++#if defined(__i386__) || defined(__x86_64__)
    5.13 + #define PAGE_SHIFT      12
    5.14 ++#elif defined(__ia64__)
    5.15 ++#define PAGE_SHIFT      14
    5.16 ++#endif 
    5.17 + #define PAGE_SIZE       (1 << PAGE_SHIFT)
    5.18 + #define PAGE_MASK	(PAGE_SIZE - 1)
    5.19 + 
    5.20 +Index: ioemu/cpu-all.h
    5.21 +===================================================================
    5.22 +--- ioemu.orig/cpu-all.h	2006-07-26 13:33:45.946834283 +0100
    5.23 ++++ ioemu/cpu-all.h	2006-07-26 13:34:50.038997944 +0100
    5.24 +@@ -835,6 +835,31 @@
    5.25 +                 :"=m" (*(volatile long *)addr)
    5.26 +                 :"dIr" (nr));
    5.27 + }
    5.28 ++#elif defined(__ia64__)
    5.29 ++#include "ia64_intrinsic.h"
    5.30 ++#define atomic_set_bit(nr, addr) ({					\
    5.31 ++	typeof(*addr) bit, old, new;					\
    5.32 ++	volatile typeof(*addr) *m;					\
    5.33 ++									\
    5.34 ++	m = (volatile typeof(*addr)*)(addr + nr / (8*sizeof(*addr)));	\
    5.35 ++	bit = 1 << (nr % (8*sizeof(*addr)));				\
    5.36 ++	do {								\
    5.37 ++		old = *m;						\
    5.38 ++		new = old | bit;					\
    5.39 ++	} while (cmpxchg_acq(m, old, new) != old);			\
    5.40 ++})
    5.41 ++
    5.42 ++#define atomic_clear_bit(nr, addr) ({					\
    5.43 ++	typeof(*addr) bit, old, new;					\
    5.44 ++	volatile typeof(*addr) *m;					\
    5.45 ++									\
    5.46 ++	m = (volatile typeof(*addr)*)(addr + nr / (8*sizeof(*addr)));	\
    5.47 ++	bit = ~(1 << (nr % (8*sizeof(*addr))));				\
    5.48 ++	do {								\
    5.49 ++		old = *m;						\
    5.50 ++		new = old & bit;					\
    5.51 ++	} while (cmpxchg_acq(m, old, new) != old);			\
    5.52 ++})
    5.53 + #endif
    5.54 + 
    5.55 + /* memory API */
    5.56 +Index: ioemu/vl.c
    5.57 +===================================================================
    5.58 +--- ioemu.orig/vl.c	2006-07-26 13:33:45.996828953 +0100
    5.59 ++++ ioemu/vl.c	2006-07-26 13:34:50.044997304 +0100
    5.60 +@@ -5577,6 +5577,7 @@
    5.61 +         exit(-1);
    5.62 +     }
    5.63 + 
    5.64 ++#if defined(__i386__) || defined(__x86_64__)
    5.65 +     if (xc_get_pfn_list(xc_handle, domid, page_array, nr_pages) != nr_pages) {
    5.66 +         fprintf(logfile, "xc_get_pfn_list returned error %d\n", errno);
    5.67 +         exit(-1);
    5.68 +@@ -5597,6 +5598,34 @@
    5.69 +     fprintf(logfile, "shared page at pfn:%lx, mfn: %"PRIx64"\n", nr_pages - 1,
    5.70 +             (uint64_t)(page_array[nr_pages - 1]));
    5.71 + 
    5.72 ++#elif defined(__ia64__)
    5.73 ++    if (xc_ia64_get_pfn_list(xc_handle, domid,
    5.74 ++                             page_array, 0, nr_pages) != nr_pages) {
    5.75 ++        fprintf(logfile, "xc_ia64_get_pfn_list returned error %d\n", errno);
    5.76 ++        exit(-1);
    5.77 ++    }
    5.78 ++
    5.79 ++    phys_ram_base = xc_map_foreign_batch(xc_handle, domid,
    5.80 ++                                         PROT_READ|PROT_WRITE,
    5.81 ++                                         page_array, nr_pages);
    5.82 ++    if (phys_ram_base == 0) {
    5.83 ++        fprintf(logfile, "xc_map_foreign_batch returned error %d\n", errno);
    5.84 ++        exit(-1);
    5.85 ++    }
    5.86 ++
    5.87 ++    if (xc_ia64_get_pfn_list(xc_handle, domid, page_array,
    5.88 ++                             nr_pages + (GFW_SIZE >> PAGE_SHIFT), 1)!= 1){
    5.89 ++        fprintf(logfile, "xc_ia64_get_pfn_list returned error %d\n", errno);
    5.90 ++        exit(-1);
    5.91 ++    }
    5.92 ++
    5.93 ++    shared_page = xc_map_foreign_range(xc_handle, domid, PAGE_SIZE,
    5.94 ++                                       PROT_READ|PROT_WRITE,
    5.95 ++                                       page_array[0]);
    5.96 ++
    5.97 ++    fprintf(logfile, "shared page at pfn:%lx, mfn: %l016x\n",
    5.98 ++            IO_PAGE_START >> PAGE_SHIFT, page_array[0]);
    5.99 ++#endif
   5.100 + #else  /* !CONFIG_DM */
   5.101 + 
   5.102 + #ifdef CONFIG_SOFTMMU
   5.103 +Index: ioemu/target-i386-dm/exec-dm.c
   5.104 +===================================================================
   5.105 +--- ioemu.orig/target-i386-dm/exec-dm.c	2006-07-26 13:33:45.882841107 +0100
   5.106 ++++ ioemu/target-i386-dm/exec-dm.c	2006-07-26 13:34:50.040997731 +0100
   5.107 +@@ -340,6 +340,23 @@
   5.108 +     return io_mem_read[io_index >> IO_MEM_SHIFT];
   5.109 + }
   5.110 + 
   5.111 ++#ifdef __ia64__
   5.112 ++/* IA64 has seperate I/D cache, with coherence maintained by DMA controller.
   5.113 ++ * So to emulate right behavior that guest OS is assumed, we need to flush
   5.114 ++ * I/D cache here.
   5.115 ++ */
   5.116 ++static void sync_icache(unsigned long address, int len)
   5.117 ++{
   5.118 ++    int l;
   5.119 ++
   5.120 ++    for(l = 0; l < (len + 32); l += 32)
   5.121 ++        __ia64_fc(address + l);
   5.122 ++
   5.123 ++    ia64_sync_i();
   5.124 ++    ia64_srlz_i();
   5.125 ++}
   5.126 ++#endif 
   5.127 ++
   5.128 + /* physical memory access (slow version, mainly for debug) */
   5.129 + #if defined(CONFIG_USER_ONLY)
   5.130 + void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, 
   5.131 +@@ -455,6 +472,9 @@
   5.132 +                 ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) + 
   5.133 +                     (addr & ~TARGET_PAGE_MASK);
   5.134 +                 memcpy(buf, ptr, l);
   5.135 ++#ifdef __ia64__
   5.136 ++                sync_icache((unsigned long)ptr, l);
   5.137 ++#endif 
   5.138 +             }
   5.139 +         }
   5.140 +         len -= l;
   5.141 +Index: ioemu/exec-all.h
   5.142 +===================================================================
   5.143 +--- ioemu.orig/exec-all.h	2006-07-26 13:33:45.861843346 +0100
   5.144 ++++ ioemu/exec-all.h	2006-07-26 13:38:30.096491388 +0100
   5.145 +@@ -391,6 +391,15 @@
   5.146 + }
   5.147 + #endif
   5.148 + 
   5.149 ++#ifdef __ia64__
   5.150 ++#include "ia64_intrinsic.h"
   5.151 ++static inline int testandset (int *p)
   5.152 ++{
   5.153 ++    uint32_t o = 0, n = 1;
   5.154 ++    return (int)cmpxchg_acq(p, o, n);
   5.155 ++}
   5.156 ++#endif
   5.157 ++
   5.158 + #ifdef __s390__
   5.159 + static inline int testandset (int *p)
   5.160 + {
   5.161 +@@ -462,12 +471,13 @@
   5.162 + }
   5.163 + #endif
   5.164 + 
   5.165 +-#ifdef __ia64
   5.166 +-#include <ia64intrin.h>
   5.167 ++#ifdef __ia64__
   5.168 ++#include "ia64_intrinsic.h"
   5.169 + 
   5.170 + static inline int testandset (int *p)
   5.171 + {
   5.172 +-    return __sync_lock_test_and_set (p, 1);
   5.173 ++    uint32_t o = 0, n = 1;
   5.174 ++    return (int)cmpxchg_acq(p, o, n);
   5.175 + }
   5.176 + #endif
   5.177 + 
   5.178 +Index: ioemu/target-i386-dm/cpu.h
   5.179 +===================================================================
   5.180 +--- ioemu.orig/target-i386-dm/cpu.h	2006-07-26 13:33:45.882841107 +0100
   5.181 ++++ ioemu/target-i386-dm/cpu.h	2006-07-26 13:34:50.040997731 +0100
   5.182 +@@ -80,7 +80,11 @@
   5.183 + /* helper2.c */
   5.184 + int main_loop(void);
   5.185 + 
   5.186 ++#if defined(__i386__) || defined(__x86_64__)
   5.187 + #define TARGET_PAGE_BITS 12
   5.188 ++#elif defined(__ia64__)
   5.189 ++#define TARGET_PAGE_BITS 14
   5.190 ++#endif 
   5.191 + #include "cpu-all.h"
   5.192 + 
   5.193 + #endif /* CPU_I386_H */
   5.194 +Index: ioemu/ia64_intrinsic.h
   5.195 +===================================================================
   5.196 +--- /dev/null	1970-01-01 00:00:00.000000000 +0000
   5.197 ++++ ioemu/ia64_intrinsic.h	2006-07-26 13:34:50.038997944 +0100
   5.198 +@@ -0,0 +1,276 @@
   5.199 ++#ifndef IA64_INTRINSIC_H
   5.200 ++#define IA64_INTRINSIC_H
   5.201 ++
   5.202 ++/*
   5.203 ++ * Compiler-dependent Intrinsics
   5.204 ++ *
   5.205 ++ * Copyright (C) 2002,2003 Jun Nakajima <jun.nakajima@intel.com>
   5.206 ++ * Copyright (C) 2002,2003 Suresh Siddha <suresh.b.siddha@intel.com>
   5.207 ++ *
   5.208 ++ */
   5.209 ++extern long ia64_cmpxchg_called_with_bad_pointer (void);
   5.210 ++extern void ia64_bad_param_for_getreg (void);
   5.211 ++#define ia64_cmpxchg(sem,ptr,o,n,s) ({					\
   5.212 ++	uint64_t _o, _r;						\
   5.213 ++	switch(s) {							\
   5.214 ++		case 1: _o = (uint8_t)(long)(o); break;			\
   5.215 ++		case 2: _o = (uint16_t)(long)(o); break;		\
   5.216 ++		case 4: _o = (uint32_t)(long)(o); break;		\
   5.217 ++		case 8: _o = (uint64_t)(long)(o); break;		\
   5.218 ++		default: break;						\
   5.219 ++	}								\
   5.220 ++	switch(s) {							\
   5.221 ++		case 1:							\
   5.222 ++		_r = ia64_cmpxchg1_##sem((uint8_t*)ptr,n,_o); break;	\
   5.223 ++		case 2:							\
   5.224 ++		_r = ia64_cmpxchg2_##sem((uint16_t*)ptr,n,_o); break;	\
   5.225 ++		case 4:							\
   5.226 ++		_r = ia64_cmpxchg4_##sem((uint32_t*)ptr,n,_o); break;	\
   5.227 ++		case 8:							\
   5.228 ++		_r = ia64_cmpxchg8_##sem((uint64_t*)ptr,n,_o); break;	\
   5.229 ++		default:						\
   5.230 ++		_r = ia64_cmpxchg_called_with_bad_pointer(); break;	\
   5.231 ++	}								\
   5.232 ++	(__typeof__(o)) _r;						\
   5.233 ++})
   5.234 ++
   5.235 ++#define cmpxchg_acq(ptr,o,n) ia64_cmpxchg(acq,ptr,o,n,sizeof(*ptr))
   5.236 ++#define cmpxchg_rel(ptr,o,n) ia64_cmpxchg(rel,ptr,o,n,sizeof(*ptr))
   5.237 ++
   5.238 ++/*
   5.239 ++ * Register Names for getreg() and setreg().
   5.240 ++ *
   5.241 ++ * The "magic" numbers happen to match the values used by the Intel compiler's
   5.242 ++ * getreg()/setreg() intrinsics.
   5.243 ++ */
   5.244 ++
   5.245 ++/* Special Registers */
   5.246 ++
   5.247 ++#define _IA64_REG_IP		1016	/* getreg only */
   5.248 ++#define _IA64_REG_PSR		1019
   5.249 ++#define _IA64_REG_PSR_L		1019
   5.250 ++
   5.251 ++/* General Integer Registers */
   5.252 ++
   5.253 ++#define _IA64_REG_GP		1025	/* R1 */
   5.254 ++#define _IA64_REG_R8		1032	/* R8 */
   5.255 ++#define _IA64_REG_R9		1033	/* R9 */
   5.256 ++#define _IA64_REG_SP		1036	/* R12 */
   5.257 ++#define _IA64_REG_TP		1037	/* R13 */
   5.258 ++
   5.259 ++/* Application Registers */
   5.260 ++
   5.261 ++#define _IA64_REG_AR_KR0	3072
   5.262 ++#define _IA64_REG_AR_KR1	3073
   5.263 ++#define _IA64_REG_AR_KR2	3074
   5.264 ++#define _IA64_REG_AR_KR3	3075
   5.265 ++#define _IA64_REG_AR_KR4	3076
   5.266 ++#define _IA64_REG_AR_KR5	3077
   5.267 ++#define _IA64_REG_AR_KR6	3078
   5.268 ++#define _IA64_REG_AR_KR7	3079
   5.269 ++#define _IA64_REG_AR_RSC	3088
   5.270 ++#define _IA64_REG_AR_BSP	3089
   5.271 ++#define _IA64_REG_AR_BSPSTORE	3090
   5.272 ++#define _IA64_REG_AR_RNAT	3091
   5.273 ++#define _IA64_REG_AR_FCR	3093
   5.274 ++#define _IA64_REG_AR_EFLAG	3096
   5.275 ++#define _IA64_REG_AR_CSD	3097
   5.276 ++#define _IA64_REG_AR_SSD	3098
   5.277 ++#define _IA64_REG_AR_CFLAG	3099
   5.278 ++#define _IA64_REG_AR_FSR	3100
   5.279 ++#define _IA64_REG_AR_FIR	3101
   5.280 ++#define _IA64_REG_AR_FDR	3102
   5.281 ++#define _IA64_REG_AR_CCV	3104
   5.282 ++#define _IA64_REG_AR_UNAT	3108
   5.283 ++#define _IA64_REG_AR_FPSR	3112
   5.284 ++#define _IA64_REG_AR_ITC	3116
   5.285 ++#define _IA64_REG_AR_PFS	3136
   5.286 ++#define _IA64_REG_AR_LC		3137
   5.287 ++#define _IA64_REG_AR_EC		3138
   5.288 ++
   5.289 ++/* Control Registers */
   5.290 ++
   5.291 ++#define _IA64_REG_CR_DCR	4096
   5.292 ++#define _IA64_REG_CR_ITM	4097
   5.293 ++#define _IA64_REG_CR_IVA	4098
   5.294 ++#define _IA64_REG_CR_PTA	4104
   5.295 ++#define _IA64_REG_CR_IPSR	4112
   5.296 ++#define _IA64_REG_CR_ISR	4113
   5.297 ++#define _IA64_REG_CR_IIP	4115
   5.298 ++#define _IA64_REG_CR_IFA	4116
   5.299 ++#define _IA64_REG_CR_ITIR	4117
   5.300 ++#define _IA64_REG_CR_IIPA	4118
   5.301 ++#define _IA64_REG_CR_IFS	4119
   5.302 ++#define _IA64_REG_CR_IIM	4120
   5.303 ++#define _IA64_REG_CR_IHA	4121
   5.304 ++#define _IA64_REG_CR_LID	4160
   5.305 ++#define _IA64_REG_CR_IVR	4161	/* getreg only */
   5.306 ++#define _IA64_REG_CR_TPR	4162
   5.307 ++#define _IA64_REG_CR_EOI	4163
   5.308 ++#define _IA64_REG_CR_IRR0	4164	/* getreg only */
   5.309 ++#define _IA64_REG_CR_IRR1	4165	/* getreg only */
   5.310 ++#define _IA64_REG_CR_IRR2	4166	/* getreg only */
   5.311 ++#define _IA64_REG_CR_IRR3	4167	/* getreg only */
   5.312 ++#define _IA64_REG_CR_ITV	4168
   5.313 ++#define _IA64_REG_CR_PMV	4169
   5.314 ++#define _IA64_REG_CR_CMCV	4170
   5.315 ++#define _IA64_REG_CR_LRR0	4176
   5.316 ++#define _IA64_REG_CR_LRR1	4177
   5.317 ++
   5.318 ++/* Indirect Registers for getindreg() and setindreg() */
   5.319 ++
   5.320 ++#define _IA64_REG_INDR_CPUID	9000	/* getindreg only */
   5.321 ++#define _IA64_REG_INDR_DBR	9001
   5.322 ++#define _IA64_REG_INDR_IBR	9002
   5.323 ++#define _IA64_REG_INDR_PKR	9003
   5.324 ++#define _IA64_REG_INDR_PMC	9004
   5.325 ++#define _IA64_REG_INDR_PMD	9005
   5.326 ++#define _IA64_REG_INDR_RR	9006
   5.327 ++
   5.328 ++#ifdef __INTEL_COMPILER
   5.329 ++void  __fc(uint64_t *addr);
   5.330 ++void  __synci(void);
   5.331 ++void __isrlz(void);
   5.332 ++void __dsrlz(void);
   5.333 ++uint64_t __getReg(const int whichReg);
   5.334 ++uint64_t _InterlockedCompareExchange8_rel(volatile uint8_t *dest, uint64_t xchg, uint64_t comp);
   5.335 ++uint64_t _InterlockedCompareExchange8_acq(volatile uint8_t *dest, uint64_t xchg, uint64_t comp);
   5.336 ++uint64_t _InterlockedCompareExchange16_rel(volatile uint16_t *dest, uint64_t xchg, uint64_t comp);
   5.337 ++uint64_t _InterlockedCompareExchange16_acq(volatile uint16_t *dest, uint64_t xchg, uint64_t comp);
   5.338 ++uint64_t _InterlockedCompareExchange_rel(volatile uint32_t *dest, uint64_t xchg, uint64_t comp);
   5.339 ++uint64_t _InterlockedCompareExchange_acq(volatile uint32_t *dest, uint64_t xchg, uint64_t comp);
   5.340 ++uint64_t _InterlockedCompareExchange64_rel(volatile uint64_t *dest, uint64_t xchg, uint64_t comp);
   5.341 ++u64_t _InterlockedCompareExchange64_acq(volatile uint64_t *dest, uint64_t xchg, uint64_t comp);
   5.342 ++
   5.343 ++#define ia64_cmpxchg1_rel	_InterlockedCompareExchange8_rel
   5.344 ++#define ia64_cmpxchg1_acq	_InterlockedCompareExchange8_acq
   5.345 ++#define ia64_cmpxchg2_rel	_InterlockedCompareExchange16_rel
   5.346 ++#define ia64_cmpxchg2_acq	_InterlockedCompareExchange16_acq
   5.347 ++#define ia64_cmpxchg4_rel	_InterlockedCompareExchange_rel
   5.348 ++#define ia64_cmpxchg4_acq	_InterlockedCompareExchange_acq
   5.349 ++#define ia64_cmpxchg8_rel	_InterlockedCompareExchange64_rel
   5.350 ++#define ia64_cmpxchg8_acq	_InterlockedCompareExchange64_acq
   5.351 ++
   5.352 ++#define ia64_srlz_d		__dsrlz
   5.353 ++#define ia64_srlz_i		__isrlz
   5.354 ++#define __ia64_fc 		__fc
   5.355 ++#define ia64_sync_i		__synci
   5.356 ++#define __ia64_getreg		__getReg
   5.357 ++#else /* __INTEL_COMPILER */
   5.358 ++#define ia64_cmpxchg1_acq(ptr, new, old)						\
   5.359 ++({											\
   5.360 ++	uint64_t ia64_intri_res;							\
   5.361 ++	asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));					\
   5.362 ++	asm volatile ("cmpxchg1.acq %0=[%1],%2,ar.ccv":					\
   5.363 ++			      "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory");	\
   5.364 ++	ia64_intri_res;									\
   5.365 ++})
   5.366 ++
   5.367 ++#define ia64_cmpxchg1_rel(ptr, new, old)						\
   5.368 ++({											\
   5.369 ++	uint64_t ia64_intri_res;							\
   5.370 ++	asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));					\
   5.371 ++	asm volatile ("cmpxchg1.rel %0=[%1],%2,ar.ccv":					\
   5.372 ++			      "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory");	\
   5.373 ++	ia64_intri_res;									\
   5.374 ++})
   5.375 ++
   5.376 ++#define ia64_cmpxchg2_acq(ptr, new, old)						\
   5.377 ++({											\
   5.378 ++	uint64_t ia64_intri_res;							\
   5.379 ++	asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));					\
   5.380 ++	asm volatile ("cmpxchg2.acq %0=[%1],%2,ar.ccv":					\
   5.381 ++			      "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory");	\
   5.382 ++	ia64_intri_res;									\
   5.383 ++})
   5.384 ++
   5.385 ++#define ia64_cmpxchg2_rel(ptr, new, old)						\
   5.386 ++({											\
   5.387 ++	uint64_t ia64_intri_res;							\
   5.388 ++	asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));					\
   5.389 ++											\
   5.390 ++	asm volatile ("cmpxchg2.rel %0=[%1],%2,ar.ccv":					\
   5.391 ++			      "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory");	\
   5.392 ++	ia64_intri_res;									\
   5.393 ++})
   5.394 ++
   5.395 ++#define ia64_cmpxchg4_acq(ptr, new, old)						\
   5.396 ++({											\
   5.397 ++	uint64_t ia64_intri_res;							\
   5.398 ++	asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));					\
   5.399 ++	asm volatile ("cmpxchg4.acq %0=[%1],%2,ar.ccv":					\
   5.400 ++			      "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory");	\
   5.401 ++	ia64_intri_res;									\
   5.402 ++})
   5.403 ++
   5.404 ++#define ia64_cmpxchg4_rel(ptr, new, old)						\
   5.405 ++({											\
   5.406 ++	uint64_t ia64_intri_res;							\
   5.407 ++	asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));					\
   5.408 ++	asm volatile ("cmpxchg4.rel %0=[%1],%2,ar.ccv":					\
   5.409 ++			      "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory");	\
   5.410 ++	ia64_intri_res;									\
   5.411 ++})
   5.412 ++
   5.413 ++#define ia64_cmpxchg8_acq(ptr, new, old)						\
   5.414 ++({											\
   5.415 ++	uint64_t ia64_intri_res;							\
   5.416 ++	asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));					\
   5.417 ++	asm volatile ("cmpxchg8.acq %0=[%1],%2,ar.ccv":					\
   5.418 ++			      "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory");	\
   5.419 ++	ia64_intri_res;									\
   5.420 ++})
   5.421 ++
   5.422 ++#define ia64_cmpxchg8_rel(ptr, new, old)						\
   5.423 ++({											\
   5.424 ++	uint64_t ia64_intri_res;							\
   5.425 ++	asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));					\
   5.426 ++											\
   5.427 ++	asm volatile ("cmpxchg8.rel %0=[%1],%2,ar.ccv":					\
   5.428 ++			      "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory");	\
   5.429 ++	ia64_intri_res;									\
   5.430 ++})
   5.431 ++
   5.432 ++#define ia64_srlz_i()	asm volatile (";; srlz.i ;;" ::: "memory")
   5.433 ++#define ia64_srlz_d()	asm volatile (";; srlz.d" ::: "memory");
   5.434 ++#define __ia64_fc(addr)	asm volatile ("fc %0" :: "r"(addr) : "memory")
   5.435 ++#define ia64_sync_i()	asm volatile (";; sync.i" ::: "memory")
   5.436 ++
   5.437 ++register unsigned long ia64_r13 asm ("r13") __attribute_used__;
   5.438 ++#define __ia64_getreg(regnum)							\
   5.439 ++({										\
   5.440 ++	uint64_t ia64_intri_res;							\
   5.441 ++										\
   5.442 ++	switch (regnum) {							\
   5.443 ++	case _IA64_REG_GP:							\
   5.444 ++		asm volatile ("mov %0=gp" : "=r"(ia64_intri_res));		\
   5.445 ++		break;								\
   5.446 ++	case _IA64_REG_IP:							\
   5.447 ++		asm volatile ("mov %0=ip" : "=r"(ia64_intri_res));		\
   5.448 ++		break;								\
   5.449 ++	case _IA64_REG_PSR:							\
   5.450 ++		asm volatile ("mov %0=psr" : "=r"(ia64_intri_res));		\
   5.451 ++		break;								\
   5.452 ++	case _IA64_REG_TP:	/* for current() */				\
   5.453 ++		ia64_intri_res = ia64_r13;					\
   5.454 ++		break;								\
   5.455 ++	case _IA64_REG_AR_KR0 ... _IA64_REG_AR_EC:				\
   5.456 ++		asm volatile ("mov %0=ar%1" : "=r" (ia64_intri_res)		\
   5.457 ++				      : "i"(regnum - _IA64_REG_AR_KR0));	\
   5.458 ++		break;								\
   5.459 ++	case _IA64_REG_CR_DCR ... _IA64_REG_CR_LRR1:				\
   5.460 ++		asm volatile ("mov %0=cr%1" : "=r" (ia64_intri_res)		\
   5.461 ++				      : "i" (regnum - _IA64_REG_CR_DCR));	\
   5.462 ++		break;								\
   5.463 ++	case _IA64_REG_SP:							\
   5.464 ++		asm volatile ("mov %0=sp" : "=r" (ia64_intri_res));		\
   5.465 ++		break;								\
   5.466 ++	default:								\
   5.467 ++		ia64_bad_param_for_getreg();					\
   5.468 ++		break;								\
   5.469 ++	}									\
   5.470 ++	ia64_intri_res;								\
   5.471 ++})
   5.472 ++
   5.473 ++#endif /* __INTEL_COMPILER */
   5.474 ++#endif /* IA64_INTRINSIC_H */
     6.1 --- a/tools/ioemu/patches/series	Wed Jul 26 13:36:13 2006 +0100
     6.2 +++ b/tools/ioemu/patches/series	Wed Jul 26 13:41:10 2006 +0100
     6.3 @@ -10,6 +10,7 @@ qemu-hvm-banner
     6.4  xen-domain-name
     6.5  xen-domid
     6.6  xen-mm
     6.7 +ioemu-ia64
     6.8  qemu-smp
     6.9  qemu-no-apic
    6.10  qemu-nobios
     7.1 --- a/tools/ioemu/patches/vnc-fixes	Wed Jul 26 13:36:13 2006 +0100
     7.2 +++ b/tools/ioemu/patches/vnc-fixes	Wed Jul 26 13:41:10 2006 +0100
     7.3 @@ -1,8 +1,8 @@
     7.4  Index: ioemu/vl.c
     7.5  ===================================================================
     7.6 ---- ioemu.orig/vl.c	2006-07-14 15:56:03.043099185 +0100
     7.7 -+++ ioemu/vl.c	2006-07-14 15:56:03.123090082 +0100
     7.8 -@@ -5974,8 +5974,10 @@
     7.9 +--- ioemu.orig/vl.c	2006-07-26 13:39:18.439320475 +0100
    7.10 ++++ ioemu/vl.c	2006-07-26 13:39:18.499314057 +0100
    7.11 +@@ -6003,8 +6003,10 @@
    7.12                     kernel_filename, kernel_cmdline, initrd_filename,
    7.13                     timeoffset);
    7.14   
    7.15 @@ -17,8 +17,8 @@ Index: ioemu/vl.c
    7.16       if (use_gdbstub) {
    7.17  Index: ioemu/vnc.c
    7.18  ===================================================================
    7.19 ---- ioemu.orig/vnc.c	2006-07-14 15:56:03.040099527 +0100
    7.20 -+++ ioemu/vnc.c	2006-07-14 15:56:03.124089968 +0100
    7.21 +--- ioemu.orig/vnc.c	2006-07-26 13:39:18.437320689 +0100
    7.22 ++++ ioemu/vnc.c	2006-07-26 13:39:18.500313950 +0100
    7.23  @@ -3,6 +3,7 @@
    7.24    * 
    7.25    * Copyright (C) 2006 Anthony Liguori <anthony@codemonkey.ws>
     8.1 --- a/tools/ioemu/patches/vnc-start-vncviewer	Wed Jul 26 13:36:13 2006 +0100
     8.2 +++ b/tools/ioemu/patches/vnc-start-vncviewer	Wed Jul 26 13:41:10 2006 +0100
     8.3 @@ -1,7 +1,7 @@
     8.4  Index: ioemu/vnc.c
     8.5  ===================================================================
     8.6 ---- ioemu.orig/vnc.c	2006-07-14 18:29:36.810169908 +0100
     8.7 -+++ ioemu/vnc.c	2006-07-14 18:30:17.437628819 +0100
     8.8 +--- ioemu.orig/vnc.c	2006-07-26 13:39:18.500313950 +0100
     8.9 ++++ ioemu/vnc.c	2006-07-26 13:39:18.648298117 +0100
    8.10  @@ -999,3 +999,25 @@
    8.11   
    8.12       vnc_dpy_resize(vs->ds, 640, 400);
    8.13 @@ -30,8 +30,8 @@ Index: ioemu/vnc.c
    8.14  +}
    8.15  Index: ioemu/vl.c
    8.16  ===================================================================
    8.17 ---- ioemu.orig/vl.c	2006-07-14 18:29:36.809170020 +0100
    8.18 -+++ ioemu/vl.c	2006-07-14 18:30:17.435629043 +0100
    8.19 +--- ioemu.orig/vl.c	2006-07-26 13:39:18.499314057 +0100
    8.20 ++++ ioemu/vl.c	2006-07-26 13:39:18.650297903 +0100
    8.21  @@ -121,6 +121,7 @@
    8.22   int bios_size;
    8.23   static DisplayState display_state;
    8.24 @@ -82,7 +82,7 @@ Index: ioemu/vl.c
    8.25               case QEMU_OPTION_domainname:
    8.26                   strncat(domain_name, optarg, sizeof(domain_name) - 20);
    8.27                   break;
    8.28 -@@ -5881,6 +5889,8 @@
    8.29 +@@ -5910,6 +5918,8 @@
    8.30           dumb_display_init(ds);
    8.31       } else if (vnc_display != -1) {
    8.32   	vnc_display_init(ds, vnc_display);
    8.33 @@ -93,8 +93,8 @@ Index: ioemu/vl.c
    8.34           sdl_display_init(ds, full_screen);
    8.35  Index: ioemu/vl.h
    8.36  ===================================================================
    8.37 ---- ioemu.orig/vl.h	2006-07-14 18:29:36.810169908 +0100
    8.38 -+++ ioemu/vl.h	2006-07-14 18:30:17.436628931 +0100
    8.39 +--- ioemu.orig/vl.h	2006-07-26 13:39:18.030364229 +0100
    8.40 ++++ ioemu/vl.h	2006-07-26 13:39:18.651297796 +0100
    8.41  @@ -732,6 +732,7 @@
    8.42   
    8.43   /* vnc.c */
     9.1 --- a/tools/ioemu/target-i386-dm/cpu.h	Wed Jul 26 13:36:13 2006 +0100
     9.2 +++ b/tools/ioemu/target-i386-dm/cpu.h	Wed Jul 26 13:41:10 2006 +0100
     9.3 @@ -80,7 +80,11 @@ int cpu_x86_inl(CPUX86State *env, int ad
     9.4  /* helper2.c */
     9.5  int main_loop(void);
     9.6  
     9.7 +#if defined(__i386__) || defined(__x86_64__)
     9.8  #define TARGET_PAGE_BITS 12
     9.9 +#elif defined(__ia64__)
    9.10 +#define TARGET_PAGE_BITS 14
    9.11 +#endif 
    9.12  #include "cpu-all.h"
    9.13  
    9.14  #endif /* CPU_I386_H */
    10.1 --- a/tools/ioemu/target-i386-dm/exec-dm.c	Wed Jul 26 13:36:13 2006 +0100
    10.2 +++ b/tools/ioemu/target-i386-dm/exec-dm.c	Wed Jul 26 13:41:10 2006 +0100
    10.3 @@ -340,6 +340,23 @@ CPUReadMemoryFunc **cpu_get_io_memory_re
    10.4      return io_mem_read[io_index >> IO_MEM_SHIFT];
    10.5  }
    10.6  
    10.7 +#ifdef __ia64__
    10.8 +/* IA64 has seperate I/D cache, with coherence maintained by DMA controller.
    10.9 + * So to emulate right behavior that guest OS is assumed, we need to flush
   10.10 + * I/D cache here.
   10.11 + */
   10.12 +static void sync_icache(unsigned long address, int len)
   10.13 +{
   10.14 +    int l;
   10.15 +
   10.16 +    for(l = 0; l < (len + 32); l += 32)
   10.17 +        __ia64_fc(address + l);
   10.18 +
   10.19 +    ia64_sync_i();
   10.20 +    ia64_srlz_i();
   10.21 +}
   10.22 +#endif 
   10.23 +
   10.24  /* physical memory access (slow version, mainly for debug) */
   10.25  #if defined(CONFIG_USER_ONLY)
   10.26  void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf, 
   10.27 @@ -455,6 +472,9 @@ void cpu_physical_memory_rw(target_phys_
   10.28                  ptr = phys_ram_base + (pd & TARGET_PAGE_MASK) + 
   10.29                      (addr & ~TARGET_PAGE_MASK);
   10.30                  memcpy(buf, ptr, l);
   10.31 +#ifdef __ia64__
   10.32 +                sync_icache((unsigned long)ptr, l);
   10.33 +#endif 
   10.34              }
   10.35          }
   10.36          len -= l;
    11.1 --- a/tools/ioemu/vl.c	Wed Jul 26 13:36:13 2006 +0100
    11.2 +++ b/tools/ioemu/vl.c	Wed Jul 26 13:41:10 2006 +0100
    11.3 @@ -5754,6 +5754,7 @@ int main(int argc, char **argv)
    11.4          exit(-1);
    11.5      }
    11.6  
    11.7 +#if defined(__i386__) || defined(__x86_64__)
    11.8      if (xc_get_pfn_list(xc_handle, domid, page_array, nr_pages) != nr_pages) {
    11.9          fprintf(logfile, "xc_get_pfn_list returned error %d\n", errno);
   11.10          exit(-1);
   11.11 @@ -5774,6 +5775,34 @@ int main(int argc, char **argv)
   11.12      fprintf(logfile, "shared page at pfn:%lx, mfn: %"PRIx64"\n", nr_pages - 1,
   11.13              (uint64_t)(page_array[nr_pages - 1]));
   11.14  
   11.15 +#elif defined(__ia64__)
   11.16 +    if (xc_ia64_get_pfn_list(xc_handle, domid,
   11.17 +                             page_array, 0, nr_pages) != nr_pages) {
   11.18 +        fprintf(logfile, "xc_ia64_get_pfn_list returned error %d\n", errno);
   11.19 +        exit(-1);
   11.20 +    }
   11.21 +
   11.22 +    phys_ram_base = xc_map_foreign_batch(xc_handle, domid,
   11.23 +                                         PROT_READ|PROT_WRITE,
   11.24 +                                         page_array, nr_pages);
   11.25 +    if (phys_ram_base == 0) {
   11.26 +        fprintf(logfile, "xc_map_foreign_batch returned error %d\n", errno);
   11.27 +        exit(-1);
   11.28 +    }
   11.29 +
   11.30 +    if (xc_ia64_get_pfn_list(xc_handle, domid, page_array,
   11.31 +                             nr_pages + (GFW_SIZE >> PAGE_SHIFT), 1)!= 1){
   11.32 +        fprintf(logfile, "xc_ia64_get_pfn_list returned error %d\n", errno);
   11.33 +        exit(-1);
   11.34 +    }
   11.35 +
   11.36 +    shared_page = xc_map_foreign_range(xc_handle, domid, PAGE_SIZE,
   11.37 +                                       PROT_READ|PROT_WRITE,
   11.38 +                                       page_array[0]);
   11.39 +
   11.40 +    fprintf(logfile, "shared page at pfn:%lx, mfn: %l016x\n",
   11.41 +            IO_PAGE_START >> PAGE_SHIFT, page_array[0]);
   11.42 +#endif
   11.43  #else  /* !CONFIG_DM */
   11.44  
   11.45  #ifdef CONFIG_SOFTMMU