From ef005cc1f86de8db0880c7b1e233ef9d2b44b4ef Mon Sep 17 00:00:00 2001 From: Emanuel Czirai Date: Wed, 28 Sep 2016 17:04:13 +0200 Subject: [PATCH] x86/AMD: apply erratum 665 workaround AMD F12h machines have an erratum which can cause DIV/IDIV to behave unpredictably. The workaround is to set MSRC001_1029[31] but sometimes there is no BIOS update containing that workaround so let's do it ourselves unconditionally. It is simple enough. [ Borislav: Wrote commit message. ] Signed-off-by: Emanuel Czirai Signed-off-by: Borislav Petkov [Linux commit: d1992996753132e2dafe955cccb2fb0714d3cfc4] Make applicable to Xen. Signed-off-by: Jan Beulich Reviewed-by: Andrew Cooper master commit: 6bfee2038565a208f4ecef0911087ca10eecf25b master date: 2016-09-26 17:28:09 +0200 --- xen/arch/x86/cpu/amd.c | 12 ++++++++++++ xen/include/asm-x86/msr-index.h | 3 ++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index ad5fd0955c..7c2b241624 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -563,6 +563,18 @@ static void __devinit init_amd(struct cpuinfo_x86 *c) smp_processor_id()); wrmsrl(MSR_AMD64_LS_CFG, value | (1 << 15)); } + } else if (c->x86 == 0x12) { + rdmsrl(MSR_AMD64_DE_CFG, value); + if (!(value & (1U << 31))) { + static bool_t warned; + + if (c == &boot_cpu_data || opt_cpu_info || + !test_and_set_bool(warned)) + printk(KERN_WARNING + "CPU%u: Applying workaround for erratum 665\n", + smp_processor_id()); + wrmsrl(MSR_AMD64_DE_CFG, value | (1U << 31)); + } } /* AMD CPUs do not support SYSENTER outside of legacy mode. */ diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h index 781a2af6fb..d18860283a 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -203,10 +203,11 @@ /* AMD64 MSRs */ #define MSR_AMD64_NB_CFG 0xc001001f +#define AMD64_NB_CFG_CF8_EXT_ENABLE_BIT 46 #define MSR_AMD64_LS_CFG 0xc0011020 #define MSR_AMD64_IC_CFG 0xc0011021 #define MSR_AMD64_DC_CFG 0xc0011022 -#define AMD64_NB_CFG_CF8_EXT_ENABLE_BIT 46 +#define MSR_AMD64_DE_CFG 0xc0011029 #define MSR_AMD64_DR0_ADDRESS_MASK 0xc0011027 #define MSR_AMD64_DR1_ADDRESS_MASK 0xc0011019 -- 2.39.5