From db686bc7b006002d2c89df8dd6a5f5f6f4ee60c4 Mon Sep 17 00:00:00 2001 From: Ian Campbell Date: Fri, 22 Feb 2013 08:58:17 +0000 Subject: [PATCH] xen: arm: handle 32-bit guest CP register traps on 64-bit hypervisor Signed-off-by: Ian Campbell Acked-by: Tim Deegan --- xen/arch/arm/traps.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 6be70fa0fe..d1cf0e6ce4 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -700,16 +700,16 @@ static void do_cp15_32(struct cpu_user_regs *regs, "attempt to write to read-only register CLIDR\n"); domain_crash_synchronous(); } - *r = READ_CP32(CLIDR); + *r = READ_SYSREG32(CLIDR_EL1); break; case HSR_CPREG32(CCSIDR): if ( !cp32.read ) { dprintk(XENLOG_ERR, - "attempt to write to read-only register CSSIDR\n"); + "attempt to write to read-only register CCSIDR\n"); domain_crash_synchronous(); } - *r = READ_CP32(CCSIDR); + *r = READ_SYSREG32(CCSIDR_EL1); break; case HSR_CPREG32(DCCISW): if ( cp32.read ) @@ -718,7 +718,11 @@ static void do_cp15_32(struct cpu_user_regs *regs, "attempt to read from write-only register DCCISW\n"); domain_crash_synchronous(); } +#ifdef CONFIG_ARM_32 WRITE_CP32(*r, DCCISW); +#else + asm volatile("dc cisw, %0;" : : "r" (*r) : "memory"); +#endif break; case HSR_CPREG32(CNTP_CTL): case HSR_CPREG32(CNTP_TVAL): -- 2.39.5