From c3219b8d23a5e2c174e9c347cde9eb9ec50b0598 Mon Sep 17 00:00:00 2001 From: Yongan Liu Date: Tue, 17 Jan 2012 11:34:43 +0000 Subject: [PATCH] x86/vIRQ: IRR and TMR race condition bug fix In vlapic_set_irq, we set the IRR register before the TMR. And the IRR might be serviced before setting TMR, and even worse EOI might occur before TMR setting, in which case the vioapic_update_EOI won't be called, and further prevent all the subsequent interrupt injecting. Reorder setting the TMR and IRR will solve the problem. Besides, KVM has fixed a similar bug in: http://markmail.org/search/?q=APIC_TMR#query:APIC_TMR+page:1+mid:rphs4f7lkxjlldne+state:results Signed-off-by: Yongan Liu Signed-off-by: Jan Beulich Committed-by: Jan Beulich xen-unstable changeset: 24453:02b92d035f64 xen-unstable date: Thu Jan 05 09:29:59 2012 +0100 --- xen/arch/x86/hvm/vlapic.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/xen/arch/x86/hvm/vlapic.c b/xen/arch/x86/hvm/vlapic.c index 0b09aa9567..d7061f6d24 100644 --- a/xen/arch/x86/hvm/vlapic.c +++ b/xen/arch/x86/hvm/vlapic.c @@ -131,14 +131,11 @@ static int vlapic_find_highest_irr(struct vlapic *vlapic) int vlapic_set_irq(struct vlapic *vlapic, uint8_t vec, uint8_t trig) { - int ret; - - ret = !vlapic_test_and_set_irr(vec, vlapic); if ( trig ) vlapic_set_vector(vec, &vlapic->regs->data[APIC_TMR]); /* We may need to wake up target vcpu, besides set pending bit here */ - return ret; + return !vlapic_test_and_set_irr(vec, vlapic); } static int vlapic_find_highest_isr(struct vlapic *vlapic) -- 2.39.5