From c3173a35bc2a759dbfac4e76e9a7695b1d44e97a Mon Sep 17 00:00:00 2001 From: Huacai Chen Date: Sun, 3 May 2020 18:20:17 +0800 Subject: [PATCH] hw/mips: Add CPU IRQ3 delivery for KVM Currently, KVM/MIPS only deliver I/O interrupt via IP2, this patch add IP3 delivery as well, because Loongson-3 based machine use both IRQ2 (CPU's IP2) and IRQ3 (CPU's IP3). Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang Reviewed-by: Aleksandar Markovic Signed-off-by: Aleksandar Markovic Message-Id: <1588501221-1205-4-git-send-email-chenhc@lemote.com> --- hw/mips/mips_int.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c index 4a1bf846da..0f9c6f07c1 100644 --- a/hw/mips/mips_int.c +++ b/hw/mips/mips_int.c @@ -51,7 +51,7 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level) env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP)); } - if (kvm_enabled() && irq == 2) { + if (kvm_enabled() && (irq == 2 || irq == 3)) { kvm_mips_set_interrupt(cpu, irq, level); } -- 2.39.5