From c080e5b43dcc62d1c4d9a05fbb17e3b8d95f8eaa Mon Sep 17 00:00:00 2001 From: =?utf8?q?Roger=20Pau=20Monn=C3=A9?= Date: Thu, 5 Mar 2020 10:56:38 +0100 Subject: [PATCH] x86/apic: fix disabling LVT0 in disconnect_bsp_APIC MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The Intel SDM states: "When an illegal vector value (0 to 15) is written to a LVT entry and the delivery mode is Fixed (bits 8-11 equal 0), the APIC may signal an illegal vector error, without regard to whether the mask bit is set or whether an interrupt is actually seen on the input." And that's exactly what's currently done in disconnect_bsp_APIC when virt_wire_setup is true and LVT LINT0 is being masked. By writing only APIC_LVT_MASKED Xen is actually setting the vector to 0 and the delivery mode to Fixed (0), and hence it triggers an APIC error even when the LVT entry is masked. This would usually manifest when Xen is being shut down, as that's where disconnect_bsp_APIC is called: (XEN) APIC error on CPU0: 40(00) Fix this by calling clear_local_APIC prior to setting the LVT LINT registers which already clear LVT LINT0, and hence the troublesome write can be avoided as the register is already cleared. Reported-by: Andrew Cooper Signed-off-by: Roger Pau Monné Reviewed-by: Jan Beulich master commit: 782b48b7f7319c07b044606d67a60875e53dd05b master date: 2020-01-29 14:47:00 +0100 --- xen/arch/x86/apic.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/apic.c b/xen/arch/x86/apic.c index a8ee18636f..bf39937e9c 100644 --- a/xen/arch/x86/apic.c +++ b/xen/arch/x86/apic.c @@ -259,6 +259,8 @@ void disconnect_bsp_APIC(int virt_wire_setup) /* Go back to Virtual Wire compatibility mode */ unsigned long value; + clear_local_APIC(); + /* For the spurious interrupt use vector F, and enable it */ value = apic_read(APIC_SPIV); value &= ~APIC_VECTOR_MASK; @@ -276,10 +278,6 @@ void disconnect_bsp_APIC(int virt_wire_setup) value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); apic_write(APIC_LVT0, value); } - else { - /* Disable LVT0 */ - apic_write(APIC_LVT0, APIC_LVT_MASKED); - } /* For LVT1 make it edge triggered, active high, nmi and enabled */ value = apic_read(APIC_LVT1); -- 2.39.5