From 9bd0e75a2f31613e11455ea9cd4171741aecda68 Mon Sep 17 00:00:00 2001 From: Aravind Gopalakrishnan Date: Thu, 13 Feb 2014 10:17:40 +0100 Subject: [PATCH] x86/AMD: apply workaround for AMD F16h erratum 792 Workaround for the Erratum will be in BIOSes spun only after Jan 2014 onwards. But initial production parts shipped in 2013 itself. Since there is a coverage hole, we should carry this fix in software in case BIOS does not do the right thing or someone is using old BIOS. Description: Processor does not ensure DRAM scrub read/write sequence is atomic wrt accesses to CC6 save state area. Therefore if a concurrent scrub read/write access is to same address the entry may appear as if it is not written. This quirk applies to Fam16h models 00h-0Fh See "Revision Guide" for AMD F16h models 00h-0fh, document 51810 rev. 3.04, Nov 2013. Equivalent Linux patch link: http://marc.info/?l=linux-kernel&m=139066012217149&w=2 Tested the patch on Fam16h server platform and it works fine. Signed-off-by: Aravind Gopalakrishnan Reviewed-by: Suravee Suthikulpanit Reviewed-by: Andrew Cooper Corrected checking for boot CPU. Made warning message conditional. Compacted warning message text. Moved comment to commit message. Signed-off-by: Jan Beulich master commit: 4d3ebb84df43d90db4cc25a48f4658709bd11678 master date: 2014-02-07 11:12:22 +0100 --- xen/arch/x86/cpu/amd.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index e20771b1ef..3bb2dbde55 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -523,6 +523,25 @@ static void __devinit init_amd(struct cpuinfo_x86 *c) " all your (PV) guest kernels. ***\n"); if (c->x86 == 0x16 && c->x86_model <= 0xf) { + if (c == &boot_cpu_data) { + l = pci_conf_read32(0, 0, 0x18, 0x3, 0x58); + h = pci_conf_read32(0, 0, 0x18, 0x3, 0x5c); + if ((l & 0x1f) | (h & 0x1)) + printk(KERN_WARNING + "Applying workaround for erratum 792: %s%s%s\n", + (l & 0x1f) ? "clearing D18F3x58[4:0]" : "", + ((l & 0x1f) && (h & 0x1)) ? " and " : "", + (h & 0x1) ? "clearing D18F3x5C[0]" : ""); + + if (l & 0x1f) + pci_conf_write32(0, 0, 0x18, 0x3, 0x58, + l & ~0x1f); + + if (h & 0x1) + pci_conf_write32(0, 0, 0x18, 0x3, 0x5c, + h & ~0x1); + } + rdmsrl(MSR_AMD64_LS_CFG, value); if (!(value & (1 << 15))) { static bool_t warned; -- 2.39.5