From 86f3ff9fc4cc3cb69b96c1de74bcc51f738fe2b9 Mon Sep 17 00:00:00 2001 From: Quan Xu Date: Fri, 25 Sep 2015 09:08:22 +0200 Subject: [PATCH] vt-d: fix IM bit mask and unmask of Fault Event Control Register Bit 0:29 in Fault Event Control Register are 'Reserved and Preserved', software cannot write 0 to it unconditionally. Software must preserve the value read for writes. Signed-off-by: Quan Xu Acked-by: Yang Zhang --- xen/drivers/passthrough/vtd/iommu.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/xen/drivers/passthrough/vtd/iommu.c b/xen/drivers/passthrough/vtd/iommu.c index 4746a55ea8..1d8b561f38 100644 --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -991,10 +991,13 @@ static void dma_msi_unmask(struct irq_desc *desc) { struct iommu *iommu = desc->action->dev_id; unsigned long flags; + u32 sts; /* unmask it */ spin_lock_irqsave(&iommu->register_lock, flags); - dmar_writel(iommu->reg, DMAR_FECTL_REG, 0); + sts = dmar_readl(iommu->reg, DMAR_FECTL_REG); + sts &= ~DMA_FECTL_IM; + dmar_writel(iommu->reg, DMAR_FECTL_REG, sts); spin_unlock_irqrestore(&iommu->register_lock, flags); iommu->msi.msi_attrib.host_masked = 0; } @@ -1003,10 +1006,13 @@ static void dma_msi_mask(struct irq_desc *desc) { unsigned long flags; struct iommu *iommu = desc->action->dev_id; + u32 sts; /* mask it */ spin_lock_irqsave(&iommu->register_lock, flags); - dmar_writel(iommu->reg, DMAR_FECTL_REG, DMA_FECTL_IM); + sts = dmar_readl(iommu->reg, DMAR_FECTL_REG); + sts |= DMA_FECTL_IM; + dmar_writel(iommu->reg, DMAR_FECTL_REG, sts); spin_unlock_irqrestore(&iommu->register_lock, flags); iommu->msi.msi_attrib.host_masked = 1; } -- 2.39.5