From 76bdfe894ab2205f597e52448d620982b84565c4 Mon Sep 17 00:00:00 2001 From: Andrew Cooper Date: Thu, 8 Feb 2018 12:57:19 +0100 Subject: [PATCH] x86/cpuid: Offer Indirect Branch Controls to guests With all infrastructure in place, it is now safe to let guests see and use these features. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich Acked-by: Wei Liu master commit: 67c6838ddacfa646f9d1ae802bd0f16a935665b8 master date: 2018-01-26 14:10:21 +0000 --- xen/include/public/arch-x86/cpufeatureset.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index 5f96c1c23e..7457cb8a4c 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -233,11 +233,11 @@ XEN_CPUFEATURE(EFRO, 7*32+10) /* APERF/MPERF Read Only interface */ /* AMD-defined CPU features, CPUID level 0x80000008.ebx, word 8 */ XEN_CPUFEATURE(CLZERO, 8*32+ 0) /*A CLZERO instruction */ -XEN_CPUFEATURE(IBPB, 8*32+12) /* IBPB support only (no IBRS, used by AMD) */ +XEN_CPUFEATURE(IBPB, 8*32+12) /*A IBPB support only (no IBRS, used by AMD) */ /* Intel-defined CPU features, CPUID level 0x00000007:0.edx, word 9 */ -XEN_CPUFEATURE(IBRSB, 9*32+26) /* IBRS and IBPB support (used by Intel) */ -XEN_CPUFEATURE(STIBP, 9*32+27) /*! STIBP */ +XEN_CPUFEATURE(IBRSB, 9*32+26) /*A IBRS and IBPB support (used by Intel) */ +XEN_CPUFEATURE(STIBP, 9*32+27) /*A! STIBP */ #endif /* XEN_CPUFEATURE */ -- 2.39.5