From 7129b9e7264b2e992845ba84a5d871a4ef6bab8b Mon Sep 17 00:00:00 2001 From: Andrew Cooper Date: Tue, 22 Sep 2020 17:15:39 +0200 Subject: [PATCH] x86/pv: Handle the Intel-specific MSR_MISC_ENABLE correctly This MSR doesn't exist on AMD hardware, and switching away from the safe functions in the common MSR path was an erroneous change. Partially revert the change. This is XSA-333. Fixes: 4fdc932b3cc ("x86/Intel: drop another 32-bit leftover") Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich Reviewed-by: Wei Liu --- xen/arch/x86/pv/emul-priv-op.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c index c23822c675..8120ded330 100644 --- a/xen/arch/x86/pv/emul-priv-op.c +++ b/xen/arch/x86/pv/emul-priv-op.c @@ -924,7 +924,8 @@ static int read_msr(unsigned int reg, uint64_t *val, return X86EMUL_OKAY; case MSR_IA32_MISC_ENABLE: - rdmsrl(reg, *val); + if ( rdmsr_safe(reg, *val) ) + break; *val = guest_misc_enable(*val); return X86EMUL_OKAY; @@ -1079,7 +1080,8 @@ static int write_msr(unsigned int reg, uint64_t val, break; case MSR_IA32_MISC_ENABLE: - rdmsrl(reg, temp); + if ( rdmsr_safe(reg, temp) ) + break; if ( val != guest_misc_enable(temp) ) goto invalid; return X86EMUL_OKAY; -- 2.39.5