From 6e96dee93c60af4ee446f5e0fddf3b424824de18 Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Tue, 24 Sep 2024 14:40:03 +0200 Subject: [PATCH] x86/HVM: correct partial HPET_STATUS write emulation For partial writes the non-written parts of registers are folded into the full 64-bit value from what they're presently set to. That's wrong to do though when the behavior is write-1-to-clear: Writes not including to low 3 bits would unconditionally clear all ISR bits which are presently set. Re-calculate the value to use. Fixes: be07023be115 ("x86/vhpet: add support for level triggered interrupts") Signed-off-by: Jan Beulich Reviewed-by: Andrew Cooper master commit: 41d358d2f9607ba37c216effa39b9f1bc58de69d master date: 2024-08-29 10:02:20 +0200 --- xen/arch/x86/hvm/hpet.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/hvm/hpet.c b/xen/arch/x86/hvm/hpet.c index 87642575f9..f0e5f877f4 100644 --- a/xen/arch/x86/hvm/hpet.c +++ b/xen/arch/x86/hvm/hpet.c @@ -404,7 +404,8 @@ static int cf_check hpet_write( break; case HPET_STATUS: - /* write 1 to clear. */ + /* Write 1 to clear. Therefore don't use new_val directly here. */ + new_val = val << ((addr & 7) * 8); while ( new_val ) { bool active; -- 2.39.5