From 6db02328a7537fb62c282700f34d9b0c0a845854 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Tue, 18 Jan 2022 09:45:19 +0800 Subject: [PATCH] target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns Vector narrowing conversion instructions are provided to and from all supported integer EEWs for Zve32f extension. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-id: 20220118014522.13613-17-frank.chang@sifive.com Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index f2d3c9e8b9..7a040b3089 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2862,6 +2862,7 @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a) return opfv_narrow_check(s, a) && require_rvf(s) && (s->sew != MO_64) && + require_zve32f(s) && require_zve64f(s); } @@ -2870,6 +2871,7 @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a) return opfv_narrow_check(s, a) && require_scale_rvf(s) && (s->sew != MO_8) && + require_scale_zve32f(s) && require_scale_zve64f(s); } @@ -2920,6 +2922,7 @@ static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a) vext_check_isa_ill(s) && /* OPFV narrowing instructions ignore vs1 check */ vext_check_sd(s, a->rd, a->rs2, a->vm) && + require_scale_zve32f(s) && require_scale_zve64f(s); } -- 2.39.5