From 68a1ac19a1a24bc47c8c6db1bca7026e2199cc32 Mon Sep 17 00:00:00 2001 From: Petar Jovanovic Date: Fri, 29 Nov 2013 17:27:42 +0100 Subject: [PATCH] target-mips: fix 64-bit FPU config for user-mode emulation FR bit should be initialized to 1 for MIPS64, under condition that this bit is writable and that CPU has an FPU unit. It should be initialized to zero for MIPS32. This fixes different MIPS32 issues with FPU instructions whose behaviour defaulted to 64-bit FPU mode. Signed-off-by: Petar Jovanovic Signed-off-by: Aurelien Jarno (cherry picked from commit 4d66261f71f2efa31e1052e4041c5ee505572fe5) Signed-off-by: Michael Roth --- target-mips/translate.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index e2eb908cf..cf29e71e7 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -15988,10 +15988,13 @@ void cpu_state_reset(CPUMIPSState *env) if (env->CP0_Config3 & (1 << CP0C3_DSPP)) { env->CP0_Status |= (1 << CP0St_MX); } - /* Enable 64-bit FPU if the target cpu supports it. */ - if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { +# if defined(TARGET_MIPS64) + /* For MIPS64, init FR bit to 1 if FPU unit is there and bit is writable. */ + if ((env->CP0_Config1 & (1 << CP0C1_FP)) && + (env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) { env->CP0_Status |= (1 << CP0St_FR); } +# endif #else if (env->hflags & MIPS_HFLAG_BMASK) { /* If the exception was raised from a delay slot, -- 2.39.5