From 48d32458bcd453e31b458bca868a079a6d0a38af Mon Sep 17 00:00:00 2001 From: "H. Peter Anvin" Date: Tue, 9 Sep 2014 18:09:08 +0200 Subject: [PATCH] x86, idle: add barriers to CLFLUSH workaround ... since the documentation is explicit that CLFLUSH is only ordered with respect to MFENCE. Signed-off-by: H. Peter Anvin Signed-off-by: Jan Beulich --- xen/arch/x86/acpi/cpu_idle.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c index b05fb39182..136c0b6373 100644 --- a/xen/arch/x86/acpi/cpu_idle.c +++ b/xen/arch/x86/acpi/cpu_idle.c @@ -336,7 +336,11 @@ void mwait_idle_with_hints(unsigned int eax, unsigned int ecx) s_time_t expires = per_cpu(timer_deadline, cpu); if ( boot_cpu_has(X86_FEATURE_CLFLUSH_MONITOR) ) + { + mb(); clflush((void *)&mwait_wakeup(cpu)); + mb(); + } __monitor((void *)&mwait_wakeup(cpu), 0, 0); smp_mb(); -- 2.39.5