From 20716a4b1ceea298e4b31d6596403cbc7548ef9f Mon Sep 17 00:00:00 2001 From: Federico Serafini Date: Tue, 30 Jul 2024 11:53:26 +0200 Subject: [PATCH] x86/mce: address violations of MISRA C Rule 16.3 Add missing break statements to address violations of MISRA C Rule 16.3: "An unconditional `break' statement shall terminate every switch-clause". No functional change. Signed-off-by: Federico Serafini Reviewed-by: Stefano Stabellini Acked-by: Jan Beulich --- xen/arch/x86/cpu/mcheck/mce_amd.c | 1 + xen/arch/x86/cpu/mcheck/mce_intel.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/xen/arch/x86/cpu/mcheck/mce_amd.c b/xen/arch/x86/cpu/mcheck/mce_amd.c index 3318b8204f..4f06a3153b 100644 --- a/xen/arch/x86/cpu/mcheck/mce_amd.c +++ b/xen/arch/x86/cpu/mcheck/mce_amd.c @@ -201,6 +201,7 @@ static void mcequirk_amd_apply(enum mcequirk_amd_flags flags) default: ASSERT(flags == MCEQUIRK_NONE); + break; } } diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c b/xen/arch/x86/cpu/mcheck/mce_intel.c index dd812f4b8a..9574dedbfd 100644 --- a/xen/arch/x86/cpu/mcheck/mce_intel.c +++ b/xen/arch/x86/cpu/mcheck/mce_intel.c @@ -896,6 +896,8 @@ static void intel_init_ppin(const struct cpuinfo_x86 *c) ppin_msr = 0; else if ( c == &boot_cpu_data ) ppin_msr = MSR_PPIN; + + break; } } -- 2.39.5