From 1d48a595838c030efe34689b7a9781c60d1a52fc Mon Sep 17 00:00:00 2001 From: wulf Date: Thu, 12 Sep 2019 12:33:09 +0000 Subject: [PATCH] ig4(4): Fix SDA HOLD time set too low on Skylake controllers Execution of "Soft reset" command (IG4_REG_RESETS_SKL) at controller init stage sets SDA_HOLD register value to 0x0001 which is often too low for normal operation. Set SDA_HOLD back to 28 after reset to restore controller functionality. PR: 240339 Reported by: imp, GregV, et al. MFC after: 3 days --- sys/dev/ichiic/ig4_iic.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sys/dev/ichiic/ig4_iic.c b/sys/dev/ichiic/ig4_iic.c index 11beb743ed4..54dba7b9657 100644 --- a/sys/dev/ichiic/ig4_iic.c +++ b/sys/dev/ichiic/ig4_iic.c @@ -590,6 +590,8 @@ ig4iic_attach(ig4iic_softc_t *sc) reg_write(sc, IG4_REG_SS_SCL_LCNT, 125); reg_write(sc, IG4_REG_FS_SCL_HCNT, 100); reg_write(sc, IG4_REG_FS_SCL_LCNT, 125); + if (sc->version == IG4_SKYLAKE) + reg_write(sc, IG4_REG_SDA_HOLD, 28); /* * Use a threshold of 1 so we get interrupted on each character, -- 2.39.5