From 0c4e99317a7a95a80de17a83a6271c97e524f380 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Fri, 22 May 2020 19:25:04 +0200 Subject: [PATCH] target/riscv/cpu: Restrict CPU migration to system-mode MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Laurent Vivier Tested-by: Laurent Vivier Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20200522172510.25784-8-philmd@redhat.com> Signed-off-by: Laurent Vivier --- target/riscv/cpu.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 059d71f2c7..6c78337858 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -485,10 +485,12 @@ static void riscv_cpu_init(Object *obj) cpu_set_cpustate_pointers(cpu); } +#ifndef CONFIG_USER_ONLY static const VMStateDescription vmstate_riscv_cpu = { .name = "cpu", .unmigratable = 1, }; +#endif static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), @@ -544,13 +546,13 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) cc->do_transaction_failed = riscv_cpu_do_transaction_failed; cc->do_unaligned_access = riscv_cpu_do_unaligned_access; cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug; + /* For now, mark unmigratable: */ + cc->vmsd = &vmstate_riscv_cpu; #endif #ifdef CONFIG_TCG cc->tcg_initialize = riscv_translate_init; cc->tlb_fill = riscv_cpu_tlb_fill; #endif - /* For now, mark unmigratable: */ - cc->vmsd = &vmstate_riscv_cpu; device_class_set_props(dc, riscv_cpu_properties); } -- 2.39.5