Thomas Huth [Wed, 22 Dec 2021 08:30:54 +0000 (09:30 +0100)]
tests/qtest/virtio-net-failover: Use g_file_open_tmp() to create temporary file
g_test_rand_int() must not be called before g_test_init(), otherwise
the glib will show a "g_rand_int: assertion 'rand != NULL' failed"
message in the log. So we could change the order here, but actually,
it's safer to use g_file_open_tmp() anyway, so let's use that function
now instead.
Reported-by: Philippe Mathieu-Daudé <philmd@redhat.com> Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211222083652.776592-1-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
Thomas Huth [Mon, 20 Dec 2021 08:10:53 +0000 (09:10 +0100)]
tests/qtest/cdrom-test: Check whether devices are available before using them
Downstream users might want to disable legacy devices in their binaries,
so we should not blindly assume that they are available. Add some proper
checks before using them.
Message-Id: <20211220081054.151515-4-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
Thomas Huth [Mon, 20 Dec 2021 08:10:52 +0000 (09:10 +0100)]
tests/qtest: Improve endianness-test to work with missing machines and devices
The users might have built QEMU with less machines or without the
i82378 superio device. Add some checks to the endianess-test so that
it is able to deal with such stripped down QEMU versions, too.
Message-Id: <20211220081054.151515-3-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
Thomas Huth [Mon, 20 Dec 2021 08:10:51 +0000 (09:10 +0100)]
tests/qtest: Add a function that checks whether a device is available
Devices might not always be compiled into the QEMU target binaries.
We already have the libqos framework that is good for handling such
situations, but some of the qtests are not a real good fit for the
libqos framework. Let's add a qtest_has_device() function for such
tests instead.
Message-Id: <20211220081054.151515-2-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
Thomas Huth [Mon, 20 Dec 2021 10:30:25 +0000 (11:30 +0100)]
tests/qtest: Make the filter tests independent from a specific NIC
These filter tests need a NIC, no matter which one, so they use a common
NIC by default. However, these common NIC models might not always have
been compiled into the QEMU target binary, so assuming that a certain NIC
is available is a bad idea. Since the exact type of NIC does not really
matter for these tests, let's switch to "-nic" instead of "-netdev" so
that QEMU can simply pick a default NIC for us.
This way we can now run the tests on other targets that have a default
machine with an on-board/default NIC, too.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20211220103025.311759-1-thuth@redhat.com> Reviewed-by: Zhang Chen <chen.zhang@intel.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
Thomas Huth [Mon, 20 Dec 2021 16:40:42 +0000 (17:40 +0100)]
tests/qtest/boot-serial-test: Silence the warning about deprecated sga device
When running the qtests, there are currently a bunch of warnings about
the deprecated sga device during the boot-serial-test. Switch to
"-M graphics=off" to silence these warnings.
Message-Id: <20211220164042.397028-1-thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
Laurent Vivier [Mon, 20 Dec 2021 14:53:14 +0000 (15:53 +0100)]
failover: Silence warning messages during qtest
virtio-net-failover test tries several device combinations that produces
some expected warnings.
These warning can be confusing, so we disable them during the qtest
sequence.
Reported-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Message-Id: <20211220145314.390697-1-lvivier@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Jason Wang <jasowang@redhat.com>
[thuth: Fix memory leak by using error_free()] Signed-off-by: Thomas Huth <thuth@redhat.com>
Merge tag 'pull-loong-20211221-2' of https://gitlab.com/rth7680/qemu into staging
Initial commit of tcg/loongarch64
# gpg: Signature made Tue 21 Dec 2021 01:19:00 PM PST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
WANG Xuerui [Tue, 21 Dec 2021 05:41:04 +0000 (13:41 +0800)]
configure, meson.build: Mark support for loongarch64 hosts
Example output of `uname -a` on an initial Gentoo LA64 port, running
the upstream submission version of Linux (with some very minor patches
not influencing output here):
> Linux <hostname> 5.14.0-10342-g37a00851b145 #5 SMP PREEMPT Tue Aug 10 12:56:24 PM CST 2021 loongarch64 GNU/Linux
And the same on the vendor-supplied Loongnix 20 system, with an early
in-house port of Linux, and using the old-world ABI:
> Linux <hostname> 4.19.167-rc5.lnd.1-loongson-3 #1 SMP Sat Apr 17 07:32:32 UTC 2021 loongarch64 loongarch64 loongarch64 GNU/Linux
So a name of "loongarch64" matches both, fortunately.
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211221054105.178795-31-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
WANG Xuerui [Tue, 21 Dec 2021 05:41:03 +0000 (13:41 +0800)]
linux-user: Implement CPU-specific signal handler for loongarch64 hosts
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211221054105.178795-30-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
WANG Xuerui [Tue, 21 Dec 2021 05:41:02 +0000 (13:41 +0800)]
common-user: Add safe syscall handling for loongarch64 hosts
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211221054105.178795-29-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
WANG Xuerui [Tue, 21 Dec 2021 05:41:01 +0000 (13:41 +0800)]
tcg/loongarch64: Register the JIT
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211221054105.178795-28-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
WANG Xuerui [Tue, 21 Dec 2021 05:41:00 +0000 (13:41 +0800)]
tcg/loongarch64: Implement tcg_target_init
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211221054105.178795-27-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
WANG Xuerui [Tue, 21 Dec 2021 05:40:59 +0000 (13:40 +0800)]
tcg/loongarch64: Implement exit_tb/goto_tb
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211221054105.178795-26-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211221054105.178795-25-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211221054105.178795-24-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
WANG Xuerui [Tue, 21 Dec 2021 05:40:56 +0000 (13:40 +0800)]
tcg/loongarch64: Implement simple load/store ops
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211221054105.178795-23-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
WANG Xuerui [Tue, 21 Dec 2021 05:40:55 +0000 (13:40 +0800)]
tcg/loongarch64: Implement tcg_out_call
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211221054105.178795-22-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
WANG Xuerui [Tue, 21 Dec 2021 05:40:54 +0000 (13:40 +0800)]
tcg/loongarch64: Implement setcond ops
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211221054105.178795-21-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
WANG Xuerui [Tue, 21 Dec 2021 05:40:53 +0000 (13:40 +0800)]
tcg/loongarch64: Implement br/brcond ops
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211221054105.178795-20-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211221054105.178795-19-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
WANG Xuerui [Tue, 21 Dec 2021 05:40:51 +0000 (13:40 +0800)]
tcg/loongarch64: Implement add/sub ops
The neg_i{32,64} ops is fully expressible with sub, so omitted for
simplicity.
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211221054105.178795-18-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211221054105.178795-17-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
WANG Xuerui [Tue, 21 Dec 2021 05:40:49 +0000 (13:40 +0800)]
tcg/loongarch64: Implement clz/ctz ops
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211221054105.178795-16-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
WANG Xuerui [Tue, 21 Dec 2021 05:40:48 +0000 (13:40 +0800)]
tcg/loongarch64: Implement bswap{16,32,64} ops
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211221054105.178795-15-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
WANG Xuerui [Tue, 21 Dec 2021 05:40:47 +0000 (13:40 +0800)]
tcg/loongarch64: Implement deposit/extract ops
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211221054105.178795-14-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211221054105.178795-13-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211221054105.178795-12-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
WANG Xuerui [Tue, 21 Dec 2021 05:40:44 +0000 (13:40 +0800)]
tcg/loongarch64: Implement goto_ptr
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211221054105.178795-11-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
WANG Xuerui [Tue, 21 Dec 2021 05:40:43 +0000 (13:40 +0800)]
tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211221054105.178795-10-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
WANG Xuerui [Tue, 21 Dec 2021 05:40:42 +0000 (13:40 +0800)]
tcg/loongarch64: Implement the memory barrier op
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211221054105.178795-9-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211221054105.178795-8-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
WANG Xuerui [Tue, 21 Dec 2021 05:40:40 +0000 (13:40 +0800)]
tcg/loongarch64: Define the operand constraints
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211221054105.178795-7-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
WANG Xuerui [Tue, 21 Dec 2021 05:40:39 +0000 (13:40 +0800)]
tcg/loongarch64: Add register names, allocation order and input/output sets
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211221054105.178795-6-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
WANG Xuerui [Tue, 21 Dec 2021 05:40:38 +0000 (13:40 +0800)]
tcg/loongarch64: Add generated instruction opcodes and encoding helpers
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211221054105.178795-5-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
WANG Xuerui [Tue, 21 Dec 2021 05:40:37 +0000 (13:40 +0800)]
tcg/loongarch64: Add the tcg-target.h file
Support for all optional TCG ops are initially marked disabled; the bits
are to be set in individual commits later.
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211221054105.178795-4-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
WANG Xuerui [Tue, 21 Dec 2021 05:40:36 +0000 (13:40 +0800)]
MAINTAINERS: Add tcg/loongarch64 entry with myself as maintainer
I ported the initial code, so I should maintain it of course.
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211221054105.178795-3-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211221054105.178795-2-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Merge tag 'dbus-pull-request' of https://gitlab.com/marcandre.lureau/qemu into staging
Add D-Bus display backend
# gpg: Signature made Mon 20 Dec 2021 10:57:18 PM PST
# gpg: using RSA key 87A9BD933F87C606D276F62DDAE8E10975969CE5
# gpg: issuer "marcandre.lureau@redhat.com"
# gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>" [unknown]
# gpg: aka "Marc-André Lureau <marcandre.lureau@gmail.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 87A9 BD93 3F87 C606 D276 F62D DAE8 E109 7596 9CE5
* tag 'dbus-pull-request' of https://gitlab.com/marcandre.lureau/qemu: (36 commits)
MAINTAINERS: update D-Bus section
ui/dbus: register D-Bus VC handler
ui/dbus: add chardev backend & interface
option: add g_auto for QemuOpts
chardev: make socket derivable
chardev: teach socket to accept no addresses
ui/dbus: add clipboard interface
audio: add "dbus" audio backend
tests: start dbus-display-test
tests/qtests: add qtest_qmp_add_client()
ui/dbus: add p2p=on/off option
ui: add a D-Bus display backend
build-sys: set glib dependency version
docs: add dbus-display documentation
docs: move D-Bus VMState documentation to source XML
backends: move dbus-vmstate1.xml to backends/
docs/sphinx: add sphinx modules to include D-Bus documentation
scripts: teach modinfo to skip non-C sources
console: save current scanout details
ui: move qemu_spice_fill_device_address to ui/util.c
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Cover basic display interface usage. More cases to be added to cover
disconnections, multiple connections, corner cases. At this point, they
would be better written in Rust or Python though.
The proxy also covers reading the properties, since they are
automatically loaded at creation.
Add an option to use direct connections instead of via the bus. Clients
are accepted with QMP add_client.
This allows to provide the D-Bus display without a bus. It also
simplifies the testing setup (some CI have issues to setup a D-Bus bus
in a container).
The "dbus" display backend exports the QEMU consoles and other
UI-related interfaces over D-Bus.
By default, the connection is established on the session bus, but you
can specify a different bus with the "addr" option.
The backend takes the "org.qemu" service name, while still allowing
further instances to queue on the same name (so you can lookup all the
available instances too). It accepts any number of clients at this
point, although this is expected to evolve with options to restrict
clients, or only accept p2p via fd passing.
The interface is intentionally very close to the internal QEMU API,
and can be introspected or interacted with busctl/dfeet etc:
docs/sphinx: add sphinx modules to include D-Bus documentation
Add a new dbus-doc directive to import D-Bus interfaces documentation
from the introspection XML. The comments annotations follow the
gtkdoc/kerneldoc style, and should be formatted with reST.
Note: I realize after the fact that I was implementing those modules
with sphinx 4, and that we have much lower requirements. Instead of
lowering the features and code (removing type annotations etc), let's
have a warning in the documentation when the D-Bus modules can't be
used, and point to the source XML file in that case.
For now, only one listener can receive GL events. Let's dispatch to all
listeners. (preliminary check ensure there is a single listener now
during regitration, and in next patches, compatible listeners only)
GraphicHw.gl_flushed was introduced to notify the
device (vhost-user-gpu) that the GL resources (the display scanout) are
no longer needed.
It was decoupled from QEMU own gl-blocking mechanism, but that
difference isn't helping. Instead, we can reuse QEMU gl-blocking and
notify virtio_gpu_gl_flushed() when unblocking (to unlock
vhost-user-gpu).
An extra block/unblock is added arount dpy_gl_update() so existing
backends that don't block will have the flush event handled. It will
also help when there are no backends associated.
The Spice agent implements a simple serial mechanism to avoid clipboard
races between client & guest. See:
https://gitlab.freedesktop.org/spice/spice-protocol/-/commit/045a6978d6dbbf7046affc5c321fa8177c8cce56
Merge tag 'pull-user-20211220' of https://gitlab.com/rth7680/qemu into staging
Move errno processing from safe_syscall() to safe_syscall_base().
Move safe_syscall() from linux-user to common-user.
Add FreeBSD support to safe_syscall_base().
Tidy top-level meson.build wrt {bsd,linux}-user.
# gpg: Signature made Mon 20 Dec 2021 11:46:11 AM PST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-user-20211220' of https://gitlab.com/rth7680/qemu:
meson: Move bsd_user_ss to bsd-user/
meson: Move linux_user_ss to linux-user/
linux-user: Move thunk.c from top-level
common-user: Adjust system call return on FreeBSD
common-user: Move safe-syscall.* from linux-user
bsd-user: Create special-errno.h
linux-user: Create special-errno.h
linux-user: Rename TARGET_QEMU_ESIGRETURN to QEMU_ESIGRETURN
bsd-user: Rename TARGET_ERESTARTSYS to QEMU_ERESTARTSYS
linux-user: Rename TARGET_ERESTARTSYS to QEMU_ERESTARTSYS
linux-user: Remove HAVE_SAFE_SYSCALL and hostdep.h
linux-user/host/sparc64: Add safe-syscall.inc.S
linux-user/host/mips: Add safe-syscall.inc.S
linux-user: Move syscall error detection into safe_syscall_base
linux-user: Untabify all safe-syscall.inc.S
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Merge tag 'pull-riscv-to-apply-20211220-1' of github.com:alistair23/qemu into staging
First RISC-V PR for QEMU 7.0
- Add support for ratified 1.0 Vector extension
- Drop support for draft 0.7.1 Vector extension
- Support Zfhmin and Zfh extensions
- Improve kernel loading for non-Linux platforms
# gpg: Signature made Sun 19 Dec 2021 08:56:08 PM PST
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* tag 'pull-riscv-to-apply-20211220-1' of github.com:alistair23/qemu: (88 commits)
hw/riscv: Use load address rather than entry point for fw_dynamic next_addr
target/riscv: Enable bitmanip Zb[abcs] instructions
riscv: Set 5.4 as minimum kernel version for riscv32
target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions
target/riscv: rvv-1.0: update opivv_vadc_check() comment
target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm
target/riscv: rvv-1.0: add vector unit-stride mask load/store insns
target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()
target/riscv: rvv-1.0: add vsetivli instruction
target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
target/riscv: rvv-1.0: floating-point reciprocal estimate instruction
target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction
target/riscv: gdb: support vector registers for rv64 & rv32
target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid
target/riscv: rvv-1.0: implement vstart CSR
target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
target/riscv: rvv-1.0: narrowing floating-point/integer type-convert
target/riscv: add "set round to odd" rounding mode helper function
target/riscv: rvv-1.0: widening floating-point/integer type-convert
target/riscv: rvv-1.0: floating-point/integer type-convert instructions
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
We have no need to reference bsd_user_ss outside of bsd-user.
Go ahead and merge it directly into specific_ss.
Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
We have no need to reference linux_user_ss outside of linux-user.
Go ahead and merge it directly into specific_ss.
Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
So far, linux-user is the only user of these functions.
Clean up the build machinery by restricting it to linux-user.
Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Move linux-user safe-syscall.S and safe-syscall-error.c to common-user
so that bsd-user can also use it. Also move safe-syscall.h to
include/user/. Since there is nothing here that is related to the guest,
as opposed to the host, build it once.
Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Jessica Clarke [Tue, 14 Dec 2021 03:24:56 +0000 (03:24 +0000)]
hw/riscv: Use load address rather than entry point for fw_dynamic next_addr
The original BBL boot method had the kernel embedded as an opaque blob
that was blindly jumped to, which OpenSBI implemented as fw_payload.
OpenSBI then implemented fw_jump, which allows the payload to be loaded
elsewhere, but still blindly jumps to a fixed address at which the
kernel is to be loaded. Finally, OpenSBI introduced fw_dynamic, which
allows the previous stage to inform it where to jump to, rather than
having to blindly guess like fw_jump, or embed the payload as part of
the build like fw_payload. When used with an opaque binary (i.e. the
output of objcopy -O binary), it matches the behaviour of the previous
methods. However, when used with an ELF, QEMU currently passes on the
ELF's entry point address, which causes a discrepancy compared with all
the other boot methods if that entry point is not the first instruction
in the binary.
This difference specific to fw_dynamic with an ELF is not apparent when
booting Linux, since its entry point is the first instruction in the
binary. However, FreeBSD has a separate ELF entry point, following the
calling convention used by its bootloader, that differs from the first
instruction in the binary, used for the legacy SBI entry point, and so
the specific combination of QEMU's default fw_dynamic firmware with
booting FreeBSD as an ELF rather than a raw binary does not work.
Thus, align the behaviour when loading an ELF with the behaviour when
loading a raw binary; namely, use the base address of the loaded kernel
in place of the entry point.
The uImage code is left as-is in using the U-Boot header's entry point,
since the calling convention for that entry point is the same as the SBI
one and it mirrors what U-Boot will do.
Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211214032456.70203-1-jrtc27@jrtc27.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
The bitmanip extension has now been ratified [1] and upstream tooling
(gcc/binutils) support it too, so move them out of experimental and also
enable by default (for better test exposure/coverage)
Frank Chang [Fri, 10 Dec 2021 07:57:03 +0000 (15:57 +0800)]
target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions
SEW has the limitation which cannot exceed ELEN.
Widening instructions have a destination group with EEW = 2*SEW
and narrowing instructions have a source operand with EEW = 2*SEW.
Both of the instructions have the limitation of: 2*SEW <= ELEN.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-78-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions is
moved to Section 11.4 in RVV v1.0 spec. Update the comment, no
functional changes.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-77-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:57:01 +0000 (15:57 +0800)]
target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-76-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-75-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:59 +0000 (15:56 +0800)]
target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()
Add supports of Vector unit-stride mask load/store instructions
(vlm.v, vsm.v), which has:
evl (effective vector length) = ceil(env->vl / 8).
The new instructions operate the same as unmasked byte loads and stores.
Add evl parameter to reuse vext_ldst_us().
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-74-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:58 +0000 (15:56 +0800)]
target/riscv: rvv-1.0: add vsetivli instruction
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-73-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:57 +0000 (15:56 +0800)]
target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
Rename r2_zimm to r2_zimm11 for the upcoming vsetivli instruction.
vsetivli has 10-bits of zimm but vsetvli has 11-bits of zimm.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-72-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Implement the floating-point reciprocal estimate to 7 bits instruction.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-71-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Implement the floating-point reciprocal square-root estimate to 7 bits
instruction.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-70-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Hsiangkai Wang [Fri, 10 Dec 2021 07:56:54 +0000 (15:56 +0800)]
target/riscv: gdb: support vector registers for rv64 & rv32
Signed-off-by: Hsiangkai Wang <kai.wang@sifive.com> Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-69-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:53 +0000 (15:56 +0800)]
target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid
If the frm field contains an invalid rounding mode (101-111),
attempting to execute any vector floating-point instruction, even
those that do not depend on the rounding mode, will raise an illegal
instruction exception.
Call gen_set_rm() with DYN rounding mode to check and trigger illegal
instruction exception if frm field contains invalid value at run-time
for vector floating-point instructions.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-68-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:52 +0000 (15:56 +0800)]
target/riscv: rvv-1.0: implement vstart CSR
* Update and check vstart value for vector instructions.
* Add whole register move instruction helper functions as we have to
call helper function for case where vstart is not zero.
* Remove probe_pages() calls in vector load/store instructions
(except fault-only-first loads) to raise the memory access exception
at the exact processed vector element.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-67-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:51 +0000 (15:56 +0800)]
target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-66-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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