x86: refactor psr: L3 CAT: implement get hw info flow.

This patch implements get HW info flow including L3 CAT callback
function.

It also changes sysctl interface to make it more general.

With this patch, 'psr-hwinfo' can work for L3 CAT.

Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>

x86: refactor psr: L3 CAT: implement Domain init/free and schedule flows.

This patch implements the Domain init/free and schedule flows.
- When domain init, its psr resource should be allocated.
- When domain free, its psr resource should be freed too.
- When domain is scheduled, its COS ID on the socket should be
  set into ASSOC register to make corresponding COS MSR value
  work.

Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>

x86: refactor psr: L3 CAT: implement main data structures, CPU init and free flows.

To construct an extendible framework, we need analyze PSR features
and abstract the common things and feature specific things. Then,
encapsulate them into different data structures.

By analyzing PSR features, we can get below map.
                +------+------+------+
      --------->| Dom0 | Dom1 | ...  |
      |         +------+------+------+
      |            |
      |Dom ID      | cos_id of domain
      |            V
      |        +-----------------------------------------------------------------------------+
User --------->| PSR                                                                         |
     Socket ID |  +--------------+---------------+---------------+                           |
               |  | Socket0 Info | Socket 1 Info |    ...        |                           |
               |  +--------------+---------------+---------------+                           |
               |    |                   cos_id=0               cos_id=1          ...         |
               |    |          +-----------------------+-----------------------+-----------+ |
               |    |->Ref   : |         ref 0         |         ref 1         | ...       | |
               |    |          +-----------------------+-----------------------+-----------+ |
               |    |          +-----------------------+-----------------------+-----------+ |
               |    |->L3 CAT: |         cos 0         |         cos 1         | ...       | |
               |    |          +-----------------------+-----------------------+-----------+ |
               |    |          +-----------------------+-----------------------+-----------+ |
               |    |->L2 CAT: |         cos 0         |         cos 1         | ...       | |
               |    |          +-----------------------+-----------------------+-----------+ |
               |    |          +-----------+-----------+-----------+-----------+-----------+ |
               |    |->CDP   : | cos0 code | cos0 data | cos1 code | cos1 data | ...       | |
               |               +-----------+-----------+-----------+-----------+-----------+ |
               +-----------------------------------------------------------------------------+

So, we need define a socket info data structure, 'struct
psr_socket_info' to manage information per socket. It contains a
reference count array according to COS ID and a feature array to
manage all features enabled. Every entry of the reference count
array is used to record how many domains are using the COS registers
according to the COS ID. For example, L3 CAT and L2 CAT are enabled,
Dom1 uses COS_ID=1 registers of both features to save CBM values, like
below.
        +-------+-------+-------+-----+
        | COS 0 | COS 1 | COS 2 | ... |
        +-------+-------+-------+-----+
L3 CAT  | 0x7ff | 0x1ff | ...   | ... |
        +-------+-------+-------+-----+
L2 CAT  | 0xff  | 0xff  | ...   | ... |
        +-------+-------+-------+-----+

If Dom2 has same CBM values, it can reuse these registers which COS_ID=1.
That means, both Dom1 and Dom2 use same COS registers(ID=1) to keep same
L3/L2 values. So, the value of ref[1] is 2 which means 2 domains are using
COS_ID 1.

To manage a feature, we need define a feature node data structure,
'struct feat_node', to manage feature's specific HW info, and an array of all
COS registers values of this feature.

To manage feature properties, we need define a feature property data structure,
'struct feat_props', to manage common properties (callback functions - all
feature's specific behaviors are encapsulated into these callback functions,
and generic values - e.g. the cos_max), the feature independent values.

CDP is a special feature which uses two entries of the array
for one COS ID. So, the number of CDP COS registers is the half of L3
CAT. E.g. L3 CAT has 16 COS registers, then CDP has 8 COS registers if
it is enabled. CDP uses the COS registers array as below.

                         +-----------+-----------+-----------+-----------+-----------+
CDP cos_reg_val[] index: |     0     |     1     |     2     |     3     |    ...    |
                         +-----------+-----------+-----------+-----------+-----------+
                  value: | cos0 code | cos0 data | cos1 code | cos1 data |    ...    |
                         +-----------+-----------+-----------+-----------+-----------+

For more details, please refer SDM and patches to implement 'get value' and
'set value'.

This patch also implements the CPU init and free flow including L3 CAT
initialization and some resources free. It includes below flows:
1. presmp init:
    - parse command line parameter.
    - allocate socket info for every socket.
    - allocate feature resource.
    - initialize socket info, get feature info and add feature into feature
      array per cpuid result.
    - free resources allocated if error happens.
    - register cpu notifier to handle cpu events.
2. cpu notifier:
    - handle cpu online events, if initialization work has been done before,
      do nothing.
    - handle cpu offline events, if it is the last cpu offline, free some
      socket resources.

Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>

x86: refactor psr: remove L3 CAT/CDP codes.

The current cache allocation codes in psr.c do not consider
future features addition and are not friendly to extend.

To make psr.c be more flexible to add new features and fulfill
the program principle, open for extension but closed for
modification, we have to refactor the psr.c:
1. Analyze cache allocation features and abstract general data
   structures.
2. Analyze the init and all other functions flow, abstract all
   steps that different features may have different implementations.
   Make these steps be callback functions and register feature
   specific fuctions. Then, the main processes will not be changed
   when introducing a new feature.

Because the quantity of refactor codes is big and the logics are
changed a lot, it will cause reviewers confused if just change
old codes. Reviewers have to understand both old codes and new
implementations. After review iterations from V1 to V3, Jan has
proposed to remove all old cache allocation codes firstly, then
implement new codes step by step. This will help to make codes
be more easily reviewable.

There is no construction without destruction. So, this patch
removes all current L3 CAT/CDP codes in psr.c. The following
patches will introduce the new mechanism.

Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Reviewed-by: Wei Liu <wei.liu2@citrix.com>

x86: move cpuid_count_leaf from cpuid.c to processor.h.

This patch moves 'cpuid_count_leaf' from cpuid.c to processor.h to
make it available to external codes.

Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
Acked-by: Jan Beulich <jbeulich@suse.com>

docs: create Cache Allocation Technology (CAT) and Code and Data Prioritization (CDP) feature document

This patch creates CAT and CDP feature document in doc/features/. It describes
key points to implement L3 CAT/CDP and L2 CAT which is described in details in
Intel SDM "INTEL® RESOURCE DIRECTOR TECHNOLOGY (INTEL® RDT) ALLOCATION FEATURES".

Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Reviewed-by: Wei Liu <wei.liu2@citrix.com>

move PAGE_*_* macros to xen/page-defs.h

Move pre-existing PAGE_(SHIFT|SIZE|MASK|ALIGN)_(4K|64K) and
introduce corresponding defines for 16K page granularity to/in a
common place in xen/page-defs.h to allow later commits to use the
consolidated defines.

Signed-off-by: Sergej Proskurin <proskurin@sec.in.tum.de>
Acked-by: Jan Beulich <jbeulich@suse.com>

rbtree: changes to align the code with Linux tree

The patch aligns the code of rbtree related files with Linux tree.
This will minimize the conflicts during any future porting from Linux tree.

Linux commit till f4b477c47332367d35686bd2b808c2156b96d7c7 for rbtree.h
This includes addition of commented inline functions in rbtree.h, to have
complete replica from Linux tree.

Linux commit till 4c60117811171d867d4f27f17ea07d7419d45dae for rbtree.c
This includes updates in comments in header note in rbtree.c.

Signed-off-by: Praveen Kumar <kpraveen.lkml@gmail.com>
Acked-by: Jan Beulich <jbeulich@suse.com>

IOMMU/PCI: make a few functions static

Add forward declarations in order to not move things around.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Wei Liu <wei.liu2@citrix.com>
Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>

xen:arm: earlyprintk configuration for R-Car Gen3 boards

Introduce an earlyprintk configuration for R-Car Gen3 SoC based development
boards, like:
 - Salvator-X [http://elinux.org/R-Car/Boards/Salvator-X]
 - M3ULCB [http://elinux.org/R-Car/Boards/M3SK]
 - H3ULCB [http://elinux.org/R-Car/Boards/H3SK]

Signed-off-by: Iurii Konovalenko <iurii.konovalenko@globallogic.com>
Signed-off-by: Iurii Mykhalskyi <iurii.mykhalskyi@globallogic.com>
Signed-off-by: Andrii Anisov <andrii_anisov@epam.com>
Acked-by: Julien Grall <julien.grall@arm.com>
Acked-by: Stefano Stabellini <sstabellini@kernel.org>

xen:arm64: Add SCIF UART support for earlyprintk

Add support for a SCIF compatible UART found in Renesas R-Car Gen3 SoCs.

Signed-off-by: Iurii Konovalenko <iurii.konovalenko@globallogic.com>
Signed-off-by: Iurii Mykhalskyi <iurii.mykhalskyi@globallogic.com>
Signed-off-by: Andrii Anisov <andrii_anisov@epam.com>
Acked-by: Julien Grall <julien.grall@arm.com>
Acked-by: Stefano Stabellini <sstabellini@kernel.org>

xen/arm: Fix comments coding style in assembler files

Signed-off-by: Andrii Anisov <andrii_anisov@epam.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>

docs: add pod variant of xl-numa-placement

Convert source for xl-numa-placement.7 from markdown to pod.
This removes the buildtime requirement for pandoc, and subsequently the
need for ghc, in the chain for BuildRequires of xen.rpm.

Signed-off-by: Olaf Hering <olaf@aepfle.de>
Reviewed-by: Dario Faggioli <dario.faggioli@citrix.com>
Acked-by: Wei Liu <wei.liu2@citrix.com>

docs: add pod variant of xl-network-configuration.5

Convert source for xl-network-configuration.5 from markdown to pod.
This removes the buildtime requirement for pandoc, and subsequently the
need for ghc, in the chain for BuildRequires of xen.rpm.

Signed-off-by: Olaf Hering <olaf@aepfle.de>
Acked-by: Wei Liu <wei.liu2@citrix.com>

docs: add pod variant of xen-pv-channel.7

Convert source for xen-pv-channel.7 from markdown to pod.
This removes the buildtime requirement for pandoc, and subsequently the
need for ghc, in the chain for BuildRequires of xen.rpm.

Signed-off-by: Olaf Hering <olaf@aepfle.de>
Acked-by: Wei Liu <wei.liu2@citrix.com>

Makefile: Fix uninstall target

Running "make uninstall" does not remove all installed files, a
situation which might cause link related issues if xen is re-installed
in a different location.
In order to make uninstall correctly remove the files it is best
the process should be done recursively by mirroring each "install"
target with an "uninstall" who removes the installed files.

An exception to this rule is uninstalling the files produced by
"qemu-xen-dir-remote" and "qemu-xen-traditional-dir", which are external
to the project. These projects do not implement an "uninstall" target so
the files have to be removed manually.

Signed-off-by: Petre Pircalabu <ppircalabu@bitdefender.com>
Acked-by: Wei Liu <wei.liu2@citrix.com>

libvchan: Fix cleanup when xc_gntshr_open failed

If xc_gntshr_open failed the only thing to cleanup is free allocated
memory. So instead of calling libxenvchan_close (which assume
valid calculated buffers being mmaped already) free memory and return.

Signed-off-by: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com>
Acked-by: Wei Liu <wei.liu2@citrix.com>

scripts/get_maintainers.pl: Don't blindly drop "THE REST" maintainers

"THE REST" maintainers should always be CCed for any modification that
don't fall under the responsability of a specific component maintainer.

However, the script get_maintainers.pl will remove "THE REST"
maintainers as soon as one maintainer of a specific component will be
present.

Fix the script once for all.

Signed-off-by: Julien Grall <julien.grall@arm.com>
Acked-by: Wei Liu <wei.liu2@citrix.com>

x86/cpuid: Rename *_policy to *_cpuid_policy

In the future, there will be other policy objects, e.g. MSR.

No functional change.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Wei Liu <wei.liu2@citrix.com>

x86/svm: Drop unused SVM_REG_* definitions

These are entirely unused, and are actually the general x86 register encoding,
rather than being SVM specific.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>

x86/svm: Alias the VMCB segment registers as an array

This allows svm_{get,set}_segment_register() to access the user segments by
array index, as the x86_seg_* constants match the hardware encoding.

While making this alteration, add some newlines for clarity, switch an int for
a bool, and make the functions fail safe in a release build, rather than
crashing Xen.

Bloat-o-meter reports some modest improvements:

  add/remove: 0/0 grow/shrink: 0/2 up/down: 0/-130 (-130)
  function                                     old     new   delta
  svm_set_segment_register                     662     653      -9
  svm_get_segment_register                     409     288    -121

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>

x86/vvmx: Fix auditing of MSR_BITMAP parameter

The MSR_BITMAP field is required to be page aligned.  Also switch gpa to be a
uint64_t, as the MSR_BITMAP is strictly a 64bit VMCS field.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>

x86/vvmx: Fix handing of the MSR_BITMAP field with VMCS shadowing

Currently, the following sequence of actions:

 * VMPTRLD (creates a mapping, likely pointing at gfn 0 for an empty vmcs)
 * VMWRITE CPU_BASED_VM_EXEC_CONTROL (completed by hardware)
 * VMWRITE MSR_BITMAP (completed by hardware)
 * VMLAUNCH

results in an L2 guest running with ACTIVATE_MSR_BITMAP set, but Xen using a
stale mapping (likely gfn 0) when reading the interception bitmap.  The
MSR_BITMAP field needs unconditionally intercepting even with VMCS shadowing,
so Xen's mapping of the bitmap can be updated.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Sergey Dyasli <sergey.dyasli@citrix.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>

x86/vvmx: Switch nested MSR intercept handling to use struct vmx_msr_bitmap

Rename vmx_check_msr_bitmap() to vmx_msr_is_intercepted() in order to more
clearly identify what the boolean return value means.  Change the int
access_type to bool is_write.

The NULL pointer check is moved out, as it doesn't pertain to whether the MSR
is intercepted or not.  The check is moved into nvmx_n2_vmexit_handler(),
where it becomes a hard error in the case that ACTIVATE_MSR_BITMAP is set.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>

x86/vmx: Introduce and use struct vmx_msr_bitmap

This avoids opencoding the bitmap bases in accessor functions.  Introduce a
build_assertions() function to check the structure layout against the manual
definiton.  In addition, drop some stale comments and ASSERT() that callers
pass an in-range MSR.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>

x86/vpmu: Use vmx_{clear,set}_msr_intercept() rather than opencoding them

No functional change.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>

x86/vmx: Improvements to vmx_{dis,en}able_intercept_for_msr()

 * Shorten the names to vmx_{clear,set}_msr_intercept()
 * Use an enumeration for MSR_TYPE rather than a plain integer
 * Introduce VMX_MSR_RW, as most callers alter both the read and write
   intercept at the same time.

No functional change.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>

x86/hvm: Fix boundary check in hvmemul_insn_fetch()

c/s 0943a03037 added some extra protection for overflowing the emulation
instruction cache, but Coverity points out that boundary condition is off by
one when memcpy()'ing out of the buffer.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Paul Durrant <paul.durrant@citrix.com>

libxc: bail immediately when PV superpage is discovered

The original code was added with the hope that PV superpage migration
might work. But it was never proven that the code actually worked.

Now that PV superpage is gone, simplify the code by returning error
immediately.

Suggested-by: Andrew Cooper <andrew.cooper3@citrix.com>
Signed-off-by: Wei Liu <wei.liu2@citrix.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
Acked-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>

tools: nuke superpage parameters in code

Also fix manpage because there is no superpages options in xl.cfg.

Signed-off-by: Wei Liu <wei.liu2@citrix.com>
Acked-by: Ian Jackson <ian.jackson@eu.citrix.com>
Acked-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>

x86: nuke PV superpage option and code

Delete the user visible option and code for PV superpage support. The
mm code is modified as if the option is set to false (the default
value).

Return the address space occupied by spage_info back to the reserved
address space.

Signed-off-by: Wei Liu <wei.liu2@citrix.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
Acked-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>

xen:arm earlyprintk configuration for Hikey 960 boards

Introduce an earlyprintk configuration of Hikey 960 boards.

Tested with:
 https://github.com/96boards-hikey/edk2.git #testing/hikey960_v2.5
 https://github.com/96boards-hikey/OpenPlatformPkg.git #testing/hikey960_v1.3.4
 https://git.savannah.gnu.org/git/grub.git #master
 https://github.com/96boards-hikey/linux.git #hikey960-upstream-rebase

For GRUB, the following stanza was used:

GRUB_MODULES="boot chain configfile echo efinet eval ext2 fat font gettext gfxterm gzio help linux loadenv lsefi normal part_gpt par
t_msdos read regexp search search_fs_file search_fs_uuid search_label terminal terminfo test tftp time xen_boot"

grub-install/usr/bin/grub-mkimage \
                --config grub.config \
                --dtb linux/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dtb \
                --directory=grub/usr/lib64/grub/arm64-efi \
                --output=grubaa64.efi \
                --format=arm64-efi \
                --prefix="/boot/grub" \
                $GRUB_MODULES

And grub.config:
search.fs_label rootfs root

set prefix=($root)/boot/grub
configfile $prefix/grub.cfg

Signed-off-by: Konrad Rzeszutek Wilk <konrad@kernel.org>
Signed-off-by: Stefano Stabellini <sstabellini@kernel.org>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
Acked-by: Julien Grall <julien.grall@arm.com>

tools: tracing: handle null scheduler's events

In both xentrace and xenalyze.

Signed-off-by: Dario Faggioli <dario.faggioli@citrix.com>
Acked-by: George Dunlap <george.dunlap@citrix.com>

xen: sched_null: add some tracing

In line with what is there in all the other schedulers.

Signed-off-by: Dario Faggioli <dario.faggioli@citrix.com>

xen: sched-null: support soft-affinity

The null scheduler does not really use hard-affinity for
scheduling, it uses it for 'placement', i.e., for deciding
to what pCPU to statically assign a vCPU.

Let's use soft-affinity in the same way, of course with the
difference that, if there's no free pCPU within the vCPU's
soft-affinity, we go checking the hard-affinity, instead of
putting the vCPU in the waitqueue.

This does has no impact on the scheduling overhead, because
soft-affinity is only considered in cold-path (like when a
vCPU joins the scheduler for the first time, or is manually
moved between pCPUs by the user).

Signed-off-by: Dario Faggioli <dario.faggioli@citrix.com>
Reviewed-by: George Dunlap <george.dunlap@citrix.com>

xen: sched_null: check for pending tasklet work a bit earlier

Whether or not there's pending tasklet work to do, it's
something we know from the tasklet_work_scheduled parameter.

Deal with that as soon as possible, like all other schedulers
do.

Signed-off-by: Dario Faggioli <dario.faggioli@citrix.com>
Reviewed-by: George Dunlap <george.dunlap@citrix.com>

xen: sched: factor affinity helpers out of sched_credit.c

In fact, we want to be able to use them from any scheduler.

While there, make the moved code use 'v' for struct_vcpu*
variable, like it should be done everywhere.

No functional change intended.

Signed-off-by: Dario Faggioli <dario.faggioli@citrix.com>
Signed-off-by: Justin T. Weaver <jtweaver@hawaii.edu>
Reviewed-by: George Dunlap <george.dunlap@citrix.com>

x86/emul: Drop segment_attributes_t

The amount of namespace resolution is unnecessarily large, as all code deals
in terms of struct segment_register.  This removes the attr.fields part of all
references, and alters attr.bytes to just attr.

Three areas of code using initialisers for segment_register are tweaked to
compile with older versions of GCC.  arch_set_info_hvm_guest() has its SEG()
macros altered to use plain comma-based initialisation, while
{rm,vm86}_{cs,ds}_attr are simplified to plain numbers which matches their
description in the manuals.

No functional change.  (For some reason, the old {rm,vm86}_{cs,ds}_attr causes
GCC to create variable in .rodata, whereas the new code uses immediate
operands.  As a result, vmx_{get,set}_segment_register() are slightly
shorter.)

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>

x86/hvm: Rearange check_segment() to use a switch statement

This simplifies the logic by separating the x86_segment check from the type
check.  No functional change.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>

x86/svm: Drop svm_segment_register_t

Most SVM code already uses struct segment_register.  Drop the typedef and
adjust the definitions in struct vmcb_struct, and svm_dump_sel().  Introduce
some build-time assertions that struct segment_register from the common
emulation code is usable in struct vmcb_struct.

While making these adjustments, fix some comments to not mix decimal and
hexidecimal offsets, and drop all trailing whitespace in vmcb.h

No functional change.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>

x86/pagewalk: Remove opt_allow_superpage check from guest_can_use_l2_superpages()

The purpose of guest_walk_tables() is to match the behaviour of real hardware.

A PV guest can have 2M superpages in its pagetables, via the M2P (and for dom0
via the initial P2M), even if the guest isn't permitted to create arbitrary 2M
superpage mappings.

guest_can_use_l2_superpages() checking opt_allow_superpage is a piece of PV
guest policy enforcement, rather than its intended purpose of meaning "would
hardware tolerate finding an L2 superpage with these control settings?"

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Tim Deegan <tim@xen.org>
Reviewed-by: Wei Liu <wei.liu2@citrix.com>

x86/mm: Rename get_page_and_type_from_pagenr() to get_page_and_type_from_mfn()

'pagenr' is actually an mfn.  Rename the function to use consistent
terminology, switching it to use a typesafe mfn_t.

No functional change.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Wei Liu <wei.liu2@citrix.com>

x86/mm: Rename get_page_from_pagenr() to get_page_from_mfn()

'pagenr' is actually an mfn.  Rename the function to use consistent
terminology, switching it to use a typesafe mfn_t and boolean return type.

No functional change.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Wei Liu <wei.liu2@citrix.com>

Revert "VT-d: fix VF of RC integrated PF matched to wrong VT-d unit"

This reverts commit 89df98b77d28136c4d7aade13a1c8bc154d2919f, which
incurs Xen crash when loading VF driver. The reason seems that
pci_get_pdev() can't be called when interrupt is disabled. I don't have a
quick solution to fix this; therefore revert this patch to let common cases
work well. As to the corner case I intended to fix, I will propose another
solution later.

Below is the call trace of Xen crash:
(XEN) Xen BUG at spinlock.c:47
(XEN) ----[ Xen-4.10-unstable  x86_64  debug=y   Tainted:  C   ]----
(XEN) CPU:    2
(XEN) RIP:    e008:[<ffff82d08023513c>] spinlock.c#check_lock+0x3c/0x40
(XEN) RFLAGS: 0000000000010046   CONTEXT: hypervisor (d0v2)
(XEN) rax: 0000000000000000   rbx: ffff82d08043b9c8   rcx: 0000000000000001
(XEN) rdx: 0000000000000000   rsi: 0000000000000000   rdi: ffff82d08043b9ce
(XEN) rbp: ffff83043c47fa50   rsp: ffff83043c47fa50   r8:  0000000000000000
(XEN) r9:  0000000000000000   r10: 0000000000000000   r11: 0000ffff0000ffff
(XEN) r12: 0000000000000001   r13: 0000000000000000   r14: 0000000000000072
(XEN) r15: ffff83043c006c00   cr0: 0000000080050033   cr4: 00000000003526e0
(XEN) cr3: 000000081b39a000   cr2: ffff88016c058548
(XEN) ds: 0000   es: 0000   fs: 0000   gs: 0000   ss: e010   cs: e008
(XEN) Xen code around <ffff82d08023513c> (spinlock.c#check_lock+0x3c/0x40):
(XEN)  98 83 f2 01 39 d0 75 02 <0f> 0b 5d c3 55 48 89 e5 f0 ff 05 a1 f6 1e 00 5d
(XEN) Xen stack trace from rsp=ffff83043c47fa50:
(XEN)    ffff83043c47fa68 ffff82d080235234 0000000000000005 ffff83043c47fa78
(XEN)    ffff82d080251df3 ffff83043c47fab8 ffff82d080251e80 ffff83043c47fac8
(XEN)    ffff83043c422580 ffff83042e973cd0 0000000000000005 ffff83042e9609e0
(XEN)    0000000000000072 ffff83043c47fae8 ffff82d08025795a ffff83043c47fb18
(XEN)    ffff83043c47fc18 ffff83043c47fc18 ffff83042e9609e0 ffff83043c47fba8
(XEN)    ffff82d080259be1 ffff83043c47fb10 ffff82d08023516b 0000000000000246
(XEN)    ffff83043c47fb28 0000000000000206 0000000000000002 ffff83043c47fb58
(XEN)    ffff82d080290e38 ffff83042e973cd0 ffff83043c532000 ffff83043c532000
(XEN)    ffff83042e973db0 ffff83043c47fb68 ffff82d080354dd0 ffff83043c47fc18
(XEN)    ffff82d080274e07 0000000000000040 ffff83042e9609e0 ffff83043c47fc18
(XEN)    ffff83043c47fc18 0000000000000072 ffff83043c006c00 ffff83043c47fbb8
(XEN)    ffff82d0802526f7 ffff83043c47fc08 ffff82d080273c17 ffff83043ff99d90
(XEN)    ffff83043c006c00 ffff83043c47fc08 ffff83043c006c00 ffff83042e9609e0
(XEN)    ffff83043c47fc18 0000000000000072 ffff83043c006c00 ffff83043c47fc48
(XEN)    ffff82d0802754d1 00000000feeff00c 00000fff000041ca 0000000000000002
(XEN)    ffff83042e9609e0 ffff83042e973cd0 0000000000000002 ffff83043c47fc88
(XEN)    ffff82d0802755a8 ffff83043c47fc70 0000000000000246 ffff83043c532000
(XEN)    000000000000006c ffff83043c006c00 0000000000000000 ffff83043c47fd28
(XEN)    ffff82d080279b4f ffff83043c532000 ffff83043c47fe00 ffff83043c47fcd8
(XEN)    ffff83042e973d20 ffff83043c47fcf0 ffff830400000325 0000000000000246
(XEN) Xen call trace:
(XEN)    [<ffff82d08023513c>] spinlock.c#check_lock+0x3c/0x40
(XEN)    [<ffff82d080235234>] _spin_is_locked+0x11/0x4d
(XEN)    [<ffff82d080251df3>] pcidevs_locked+0x10/0x17
(XEN)    [<ffff82d080251e80>] pci_get_pdev+0x2f/0xfd
(XEN)    [<ffff82d08025795a>] acpi_find_matched_drhd_unit+0x4d/0x11a
(XEN)    [<ffff82d080259be1>] msi_msg_write_remap_rte+0x2f/0x749
(XEN)    [<ffff82d0802526f7>] iommu_update_ire_from_msi+0x36/0x38
(XEN)    [<ffff82d080273c17>] msi.c#write_msi_msg+0x3f/0x188
(XEN)    [<ffff82d0802754d1>] __setup_msi_irq+0x3a/0x5c
(XEN)    [<ffff82d0802755a8>] setup_msi_irq+0xb5/0xf7
(XEN)    [<ffff82d080279b4f>] map_domain_pirq+0x445/0x653
(XEN)    [<ffff82d08027aa99>] allocate_and_map_msi_pirq+0x10d/0x184
(XEN)    [<ffff82d080291258>] physdev_map_pirq+0x1f8/0x26b
(XEN)    [<ffff82d0802919a6>] do_physdev_op+0x595/0x110f
(XEN)    [<ffff82d080352db0>] pv_hypercall+0x1ef/0x42c
(XEN)    [<ffff82d080356606>] entry.o#test_all_events+0/0x30
(XEN)
(XEN)
(XEN) ****************************************
(XEN) Panic on CPU 2:
(XEN) Xen BUG at spinlock.c:47
(XEN) ****************************************
(XEN)
(XEN) Reboot in five seconds...

Signed-off-by: Chao Gao <chao.gao@intel.com>
Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>

xen: Drop repeated semicolons

No functional change.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Acked-by: Julien Grall <julien.grall@arm.com>
Reviewed-by: Wei Liu <wei.liu2@citrix.com>
Acked-by: George Dunlap <george.dunlap@citrix.com>

xen/link: Move .data.rel.ro sections into .rodata for final link

This includes stuff like the hypercall tables which we really kind of want
to be read-only. And they were going into .data.read-mostly.

Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Wei Liu <wei.liu2@citrix.com>
Acked-by: Julien Grall <julien.grall@arm.com>
Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>

xen:Kconfig: Make SCIF built by default for ARM

Both Renesas R-Car Gen2(ARM32) and Gen3(ARM64) are utilizing SCIF IP,
so make its serial driver built by default for ARM.

Signed-off-by: Andrii Anisov <andrii_anisov@epam.com>
Acked-by: Julien Grall <julien.grall@arm.com>

docs: correct paragraph indention in xen-tscmode

Signed-off-by: Olaf Hering <olaf@aepfle.de>
Acked-by: Ian Jackson <ian.jackson@eu.citrix.com>
Acked-by: Wei Liu <wei.liu2@citrix.com>

docs: replace xm with xl in xen-tscmode

Signed-off-by: Olaf Hering <olaf@aepfle.de>
Acked-by: Ian Jackson <ian.jackson@eu.citrix.com>
Acked-by: Wei Liu <wei.liu2@citrix.com>

xen: RTDS: rearrange members of control structures

Nothing changed in `pahole` output, in terms of holes
and padding, but some fields have been moved, to put
related members in same cache line.

Signed-off-by: Dario Faggioli <dario.faggioli@citrix.com>
Acked-by: George Dunlap <george.dunlap@citrix.com>

xen: credit2: rearrange members of control structures

With the aim of improving memory size and layout, and
at the same time trying to put related fields reside
in the same cacheline.

Here's a summary of the output of `pahole`, with and
without this patch, for the affected data structures.

csched2_runqueue_data:
 * Before:
    size: 216, cachelines: 4, members: 14
    sum members: 208, holes: 2, sum holes: 8
    last cacheline: 24 bytes
 * After:
    size: 208, cachelines: 4, members: 14
    last cacheline: 16 bytes

csched2_private:
 * Before:
    size: 120, cachelines: 2, members: 8
    sum members: 112, holes: 1, sum holes: 4
    padding: 4
    last cacheline: 56 bytes
 * After:
    size: 112, cachelines: 2, members: 8
    last cacheline: 48 bytes

csched2_vcpu:
 * Before:
    size: 112, cachelines: 2, members: 14
    sum members: 108, holes: 1, sum holes: 4
    last cacheline: 48 bytes
 * After:
    size: 112, cachelines: 2, members: 14
    padding: 4
    last cacheline: 48 bytes

While there, improve the wording, style and alignment
of comments too.

Signed-off-by: Dario Faggioli <dario.faggioli@citrix.com>
Acked-by: George Dunlap <george.dunlap@citrix.com>

xen: credit: rearrange members of control structures

With the aim of improving memory size and layout, and
at the same time trying to put related fields reside
in the same cacheline.

Here's a summary of the output of `pahole`, with and
without this patch, for the affected data structures.

csched_pcpu:
 * Before:
    size: 88, cachelines: 2, members: 6
    sum members: 80, holes: 1, sum holes: 4
    padding: 4
    paddings: 1, sum paddings: 5
    last cacheline: 24 bytes
 * After:
    size: 80, cachelines: 2, members: 6
    paddings: 1, sum paddings: 5
    last cacheline: 16 bytes

csched_vcpu:
 * Before:
    size: 72, cachelines: 2, members: 9
    padding: 2
    last cacheline: 8 bytes
 * After:
    same numbers, but move some fields to put
    related fields in same cache line.

csched_private:
 * Before:
    size: 152, cachelines: 3, members: 17
    sum members: 140, holes: 2, sum holes: 8
    padding: 4
    paddings: 1, sum paddings: 5
    last cacheline: 24 bytes
 * After:
    same numbers, but move some fields to put
    related fields in same cache line.

Signed-off-by: Dario Faggioli <dario.faggioli@citrix.com>
Acked-by: George Dunlap <george.dunlap@citrix.com>

xen: credit2: make the cpu to runqueue map per-cpu

Instead of keeping an NR_CPUS big array of int-s,
directly inside csched2_private, use a per-cpu
variable.

That's especially beneficial (in terms of saved
memory) when there are more instance of Credit2 (in
different cpupools), and also helps fitting
csched2_private itself into CPU caches.

Signed-off-by: Dario Faggioli <dario.faggioli@citrix.com>
Acked-by: George Dunlap <george.dunlap@citrix.com>

xen: credit2: allocate runqueue data structure dynamically

Instead of keeping an NR_CPUS big array of csched2_runqueue_data
elements, directly inside the csched2_private structure, allocate
it dynamically.

This has two positive effects:
- reduces the size of csched2_private sensibly, which is
  especially good in case there are more instance of Credit2
  (in different cpupools), and is also good from the point
  of view of fitting the struct into CPU caches;
- we can use nr_cpu_ids as array size, which may be sensibly
  smaller than NR_CPUS

Signed-off-by: Dario Faggioli <dario.faggioli@citrix.com>
Acked-by: George Dunlap <george.dunlap@citrix.com>

tools: Drop xc_cpuid_check() and bindings

There are no current users which I can locate.  One piece of xend which didn't
move forwards into xl/libxl is this:

  #   Configure host CPUID consistency checks, which must be satisfied for this
  #   VM to be allowed to run on this host's processor type:
  #cpuid_check=[ '1:ecx=xxxxxxxxxxxxxxxxxxxxxxxxxx1xxxxx' ]
  # - Host must have VMX feature flag set

The implementation of xc_cpuid_check() is conceptually broken.  Dom0's view of
CPUID is not the approprite view to check, and will be wrong in the presence
of CPUID masking/faulting, and for HVM-based toolstack domains.

If it turns out that the functionality is required, it should be implemented
in terms of XEN_SYSCTL_get_cpuid_policy to use the proper CPUID view.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Acked-by: Wei Liu <wei.liu2@citrix.com>

xenconsole: Add option to xenconsole to always forward console input

Currently the default behaviour of the xenconsole client is to
ignore any input to stdin, unless stdin and stdout are both
ttys. The new option allows to manually overwrite this, causing the
client to forward input regardless.

Signed-off-by: Felix Schmoll <eggi.innovations@gmail.com>
Acked-by: Wei Liu <wei.liu2@citrix.com>
Acked-by: Ian Jackson <ian.jackson@eu.citrix.com>

xen: credit2: enable per cpu runqueue creation

The patch introduces a new command line option 'cpu' that when used will create
runqueue per logical pCPU. This may be useful for small systems, and also for
development, performance evalution and comparison.

Signed-off-by: Praveen Kumar <kpraveen.lkml@gmail.com>
Reviewed-by: Dario Faggioli <dario.faggioli@citrix.com>

kbdif: Define "feature-raw-pointer" and "request-raw-pointer"

Backends set "feature-raw-pointer" if its capable of reporting
absolute positions without scaling the coordinates to screen
size. This should be set during the backend init.
Frontends set "request-raw-pointer" to request that backends
do not rescale absolute coordinates to screen size, and the
coordinates remain in the range [0, 0x7fff]. This request is
only applicable if "request-abs-pointer" is also set. Frontends
should set this value before setting Connected.

Signed-off-by: Owen Smith <owen.smith@citrix.com>
Reviewed-by: Paul Durrant <paul.durrant@citrix.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>

x86/hvm: Drop more remains of the PVHv1 implementation

These functions don't need is_hvm_{vcpu,domain}() predicates.

hvmop_set_evtchn_upcall_vector() does need the predicate to prevent a PV
caller accessing the hvm union, but swap the copy_from_guest() and
is_hvm_domain() predicate to avoid reading the hypercall parameter if we not
going to use it.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Paul Durrant <paul.durrant@citrix.com>
Reviewed-by: Wei Liu <wei.liu2@citrix.com>
Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>

x86/hvm: Fixes to hvmemul_insn_fetch()

Force insn_off to a single byte, as offset can wrap around or truncate with
respect to sh_ctxt->insn_buf_eip under a number of normal circumstances.

Furthermore, don't use an ASSERT() for bounds checking the write into
hvmemul_ctxt->insn_buf[].

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Paul Durrant <paul.durrant@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>

x86/evtchn: Restrict the ops usable in do_event_channel_op_compat()

This hypercall is unused by guests these days, but there was no prevention of
usable subops.  The following ops have been restricted, as there is no
suitable structure in the evntchn_op union.

  EVTCHNOP_reset
  EVTCHNOP_init_control
  EVTCHNOP_expand_array
  EVTCHNOP_set_priority

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Wei Liu <wei.liu2@citrix.com>

docs: Fix the markdown for the com{1,2} keyword command line documentation

No change in content.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Acked-by: Wei Liu <wei.liu2@citrix.com>

arm/p2m: Cleanup access to the host's p2m

This commit substitutes the direct access of the host's p2m
(&d->arch.p2m) for the macro "p2m_get_hostp2m". This macro simplifies
readability and also the differentiation between the host's p2m and
alternative p2m's, i.e., as part of the altp2m subsystem that will be
submitted in the future.

Signed-off-by: Sergej Proskurin <proskurin@sec.in.tum.de>
Acked-by: Julien Grall <julien.grall@arm.com>

tools/xen-mceinj: add support of injecting LMCE

If option '-l' or '--lmce' is specified and the host supports LMCE,
xen-mceinj will inject LMCE to CPU specified by '-c' (or CPU0 if '-c'
is not present).

Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com>
Acked-by: Wei Liu <wei.liu2@citrix.com>

tools/libxc: add support of injecting MC# to specified CPUs

Though XEN_MC_inject_v2 allows injecting MC# to specified CPUs, the
current xc_mca_op() does not use this feature and not provide an
interface to callers. This commit add a new xc_mca_op_inject_v2() that
receives a cpumap providing the set of target CPUs.

Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com>
Acked-by: Wei Liu <wei.liu2@citrix.com>

x86/mce: add support of vLMCE injection to XEN_MC_inject_v2

Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>

x86/vmce, tools/libxl: expose LMCE capability in guest MSR_IA32_MCG_CAP

If LMCE is supported by host and ' mca_caps = [ "lmce" ] ' is present
in xl config, the LMCE capability will be exposed in guest MSR_IA32_MCG_CAP.
By default, LMCE is not exposed to guest so as to keep the backwards migration
compatibility.

Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com> for hypervisor side
Acked-by: Wei Liu <wei.liu2@citrix.com>

x86/vmce: enable injecting LMCE to guest on Intel host

Inject LMCE to guest if the host MCE is LMCE and the affected vcpu is
known. Otherwise, broadcast MCE to all vcpus on Intel host.

Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>

x86/vmce: emulate MSR_IA32_MCG_EXT_CTL

If MCG_LMCE_P is present in guest MSR_IA32_MCG_CAP, then allow guest
to read/write MSR_IA32_MCG_EXT_CTL.

Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>

x86/domctl: generalize the restore of vMCE parameters

vMCE parameters in struct xen_domctl_ext_vcpucontext were extended in
the past, and is likely to be extended in the future. When migrating a
PV domain from old Xen, XEN_DOMCTL_set_ext_vcpucontext should handle
the differences.

Instead of adding ad-hoc handling code at each extension, we introduce
an array to record sizes of the current and all past versions of vMCE
parameters, and search for the largest one that does not expire the
size of passed-in parameters to determine vMCE parameters that will be
restored. If vMCE parameters are extended in the future, we only need
to adapt the array to reflect the extension.

Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>

tools/libxl: Fix a segment fault when mmio_hole is set in hvm.cfg

When valid mmio_hole is set in hvm.cfg, segment fault happens at accessing
localents pointer.

Because the size of localents pointer isn't enough to store appended
mmio_hole_size parameter.

Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com>
Acked-by: Wei Liu <wei.liu2@citrix.com>

VT-d: fix VF of RC integrated PF matched to wrong VT-d unit

The problem is for a VF of RC integrated PF (e.g. PF's BDF is 00:02.0),
we would wrongly use 00:00.0 to search VT-d unit.

If a PF is an extended function, the BDF of a traditional function within the
same device should be used to search VT-d unit. Otherwise, the real BDF of PF
should be used. According PCI-e spec, an extended function is a function
within an ARI device and Function Number is greater than 7. The original code
tried to tell apart them through checking PCI_SLOT(), missing counterpart of
pci_ari_enabled() (this function exists in linux kernel) compared to linux
kernel. Without checking whether ARI is enabled, it incurs a RC integrated PF
with PCI_SLOT() >0 is wrongly classified to an extended function. Note that a
RC integrated function isn't within an ARI device and thus cannot be extended
function and in this case the real BDF should be used.

Considering 'is_extfn' field of struct pci_dev has been passed down from
Domain0 to indicate whether the function is an extended function, this patch
just looks up the 'is_extfn' field of PF's struct pci_dev and set 'devfn' to 0
when 'is_extfn' is true.

Reported-by: Crawford, Eric R <Eric.R.Crawford@intel.com>
Signed-off-by: Chao Gao <chao.gao@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>

x86emul: shifts/rotates don't allow LOCK prefix

... just like e.g. SHLD/SHRD don't (see commit dee231b5a8 [x86emul:
improve LOCK handling]).

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>

gitignore: add tools/misc/xen-diag to .gitignore

Signed-off-by: Dongli Zhang <dongli.zhang@oracle.com>
Acked-by: Wei Liu <wei.liu2@citrix.com>

CODING_STYLE: removing trailing whitespaces

Signed-off-by: Julien Grall <julien.grall@arm.com>
Acked-by: Wei Liu <wei.liu2@citrix.com>

x86/psr.c: use plain bool

Signed-off-by: Wei Liu <wei.liu2@citrix.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>

x86/msi.c: use plain bool

Signed-off-by: Wei Liu <wei.liu2@citrix.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>

x86/numa.c: use plain bool

Signed-off-by: Wei Liu <wei.liu2@citrix.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>

x86/mpparse.c: use plain bool

Signed-off-by: Wei Liu <wei.liu2@citrix.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>

x86/io_apic.c: use plain bool

Signed-off-by: Wei Liu <wei.liu2@citrix.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>

x86/smpboot.c: use plain bool

Signed-off-by: Wei Liu <wei.liu2@citrix.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>

x86/srat.c: use plain bool

Signed-off-by: Wei Liu <wei.liu2@citrix.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>

x86/xstate.c: use plain bool

Signed-off-by: Wei Liu <wei.liu2@citrix.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>

x86/monitor.c: use plain bool

Signed-off-by: Wei Liu <wei.liu2@citrix.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
Acked-by: Razvan Cojocaru <rcojocaru@bitdefender.com>

x86/i8259.c: use plain bool

Signed-off-by: Wei Liu <wei.liu2@citrix.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>

x86/i387.c: use plain bool

Signed-off-by: Wei Liu <wei.liu2@citrix.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>

x86/e820.c: use plan bool

Note that e820_mtrr_clip remains s8 although the command line
parameter is bool, because it is a tristate variable.

Signed-off-by: Wei Liu <wei.liu2@citrix.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>

x86/hpet.c: use plain bool

Signed-off-by: Wei Liu <wei.liu2@citrix.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>

x86/domctl: use plain bool

Signed-off-by: Wei Liu <wei.liu2@citrix.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>

x86/dmi.c: use plain bool

Signed-off-by: Wei Liu <wei.liu2@citrix.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>

x86/debug.c: use plain bool

Signed-off-by: Wei Liu <wei.liu2@citrix.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>

x86/apic.c: use plain bool

Signed-off-by: Wei Liu <wei.liu2@citrix.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>

x86/acpi: use plain bool

Signed-off-by: Wei Liu <wei.liu2@citrix.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>

Config.mk: update mini-os changeset

The changes contain implementations for some termios functions.

Signed-off-by: Wei Liu <wei.liu2@citrix.com>

tools/libxl/libxl_pci.c: Judge igd through class code instead of device ID

IGD passthrough couldn't work on Skylake and Kabylake, because their
Device ID aren't in fixup_ids[]. Currently we need to add every intel
graphic ID into fixup_ids[], it is hard to maintain.

This patch judge intel graphics through vendor id (0x8086) and class
code(0x030000), this could support both the old and new intel graphics,
and reduce maintain work in future.

Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com>
Acked-by: Wei Liu <wei.liu2@citrix.com>

tools/libxl/libxl_pci.c: Extract sysfs_dev_get_class from libxl__grant_vga_iomem_permission

No functional change. Just extract this function for next patch and avoid
code repetition.

Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com>
Acked-by: Wei Liu <wei.liu2@citrix.com>

tools: utility to dump guest grant table info

As both xen-netfront and xen-blkfront support multi-queue, they would
consume a lot of grant table references when there are many paravirtual
devices and vcpus assigned to guest. Guest domU might panic or hang due to
grant allocation failure when nr_grant_frames in guest has reached its max
value.

This utility would help the administrators to diagnose xen issue. There is
only one command gnttab_query_size so far to monitor the guest grant table
frame usage on dom0 side so that it is not required to debug on guest
kernel side for crash/hang analysis anymore.

It is extensible for adding new commands for more diagnostic functions and
the framework of xen-diag.c is from xen-livepatch.c.

Signed-off-by: Dongli Zhang <dongli.zhang@oracle.com>
Acked-by: Wei Liu <wei.liu2@citrix.com>

tools/libxc: add interface for GNTTABOP_query_size

This patch adds new interface for GNTTABOP_query_size in libxc to help
query the current grant table frames and maximum grant table frames for a
specific domain.

Signed-off-by: Dongli Zhang <dongli.zhang@oracle.com>
Acked-by: Wei Liu <wei.liu2@citrix.com>

oxenstored: trim history in the frequent_ops function

We were trimming the history of commits only at the end of each
transaction (regardless of how it ended).

Therefore if non-transactional writes were being made but no
transactions were being ended, the history would grow
indefinitely. Now we trim the history at regular intervals.

Signed-off-by: Thomas Sanders <thomas.sanders@citrix.com>

x86/vmx: expose LMCE feature via guest MSR_IA32_FEATURE_CONTROL

If MCG_LMCE_P is present in guest MSR_IA32_MCG_CAP, then set LMCE and
LOCK bits in guest MSR_IA32_FEATURE_CONTROL. Intel SDM requires those
bits are set before SW can enable LMCE.

Signed-off-by: Haozhong Zhang <haozhong.zhang@intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>