David Woodhouse [Thu, 13 Jun 2019 15:25:13 +0000 (16:25 +0100)]
csm: Sanitise alignment constraint in Legacy16GetTableAddress
The alignment constraint is defined in the CSM specifications as
"Bit mapped. First non-zero bit from the right is the alignment."
Use __fls() to sanitise the alignment given that definition, since
passing a non-power-of-two alignment to _malloc() isn't going to work
well. And cope with being passed zero, which was happening for the
E820 table allocation from EDK2.
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Gerd Hoffmann [Tue, 20 Nov 2018 07:06:55 +0000 (08:06 +0100)]
optionrom: disallow int19 redirect for pnp roms.
Check whenever pnp roms attempt to redirect int19, and in case it does
log a message and undo the redirect.
A pnp rom should not need this, we have BEVs and BCVs for that.
Nevertheless there are roms in the wild which are redirecting int19.
At least some BIOS implementations for physical hardware have a config
option in the setup to allow/disallow int19 redirections, so just not
allowing this seems to be the way to deal with this situation.
Gerd Hoffmann [Tue, 19 Mar 2019 10:09:33 +0000 (11:09 +0100)]
vbe: add edid support.
VBE subfunction 0x15, read ddc data.
Add VBE_edid where drivers can fill in a EDID data blob.
If we find valid data there (checking the first two header
bytes), then report the function as supported and hand out
the data.
Sam Eiderman [Wed, 24 Apr 2019 14:04:09 +0000 (17:04 +0300)]
smbios: Add missing zero byte to Type 0
According to SMBIOS Specification, section 6.1.3 Text Strings:
"Text strings associated with a given SMBIOS structure are returned in
the dmiStructBuffer, appended directly after the formatted portion of the
structure. This method of returning string information eliminates the
need for application software to deal with pointers embedded in the
SMBIOS structure. Each string is terminated with a null (00h) BYTE and
the set of strings is terminated with an additional null (00h) BYTE”
Furthermore:
"If the formatted portion of the structure contains string-reference
fields and all the string fields are set to 0 (no string references),
the formatted section of the structure is followed by two null (00h)
BYTES"
From the above it can be seen that any SMBIOS type which contains string
references should end with an additional zero byte.
This is currently handled in all SMBIOS types which use
load_str_field_with_default() besides type0.
Therefore, add the missing zero byte to SMBIOS Type 0.
Running QEMU with:
-machine pc-i440fx-2.0 (for legacy smbios)
-smbios type=0,vendor=,version=,date= (for zero str_index)
Will cause SMBIOS type0 entry to overrun type1 entry.
Reviewed-by: Mark Kanda <mark.kanda@oracle.com> Reviewed-by: Ross Philipson <ross.philipson@oracle.com> Reviewed-By: Liran Alon <liran.alon@oracle.com> Signed-off-by: Sam Eiderman <shmuel.eiderman@oracle.com>
Gerd Hoffmann [Mon, 25 Feb 2019 09:51:37 +0000 (10:51 +0100)]
vga: add atiext driver
Supports qemu emulated ati cards. They have been added in qemu 4.0.
Acceleration support (in qemu) is pretty rough still. A simple
framebuffer works fine though.
Stefan Berger [Wed, 30 Jan 2019 19:06:07 +0000 (14:06 -0500)]
tcgbios: Implement TPM 2.0 menu item to activate and deactivate PCR banks
Implement a TPM 2.0 menu item that allows a user to toggle the activation
of PCR banks of the TPM 2.0. After successful activation we shut down the
TPM 2.0 and reset the machine.
Background:
A TPM 2.0 may have multiple PCR banks, such as for SHA1, SHA256, SHA384,
SHA512, and SM3-256. One or multiple of those banks may be active (by
factory for example) and modifying the set of active PCR banks is only
possible while in the firmware since it requires platform authorization.
Platform authorization is not possible for a user when in the OS since
the firmware generates a random password for the platform authorization
before booting the system and it throws that password away.
Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
bootsplash: Added support for 16/24/32bpp in one function
Specifically added support for 16 and 32bpp files, in addition to
24bpp. The function bmp_show() in bmp.c has had the hardcoded check
for 24bpp replaced with a general bpp check that uses a % to check for
remainder, and returns 1 if the remainder is >0. The previous method
for adjusting the BMP data (raw_data_format_adjust_24bpp) relied on a
preset 3*bytes_per_line_src, this has been changed and the
multiplication is now performed in the function's arguments. This
change still allows someone else to reuse the same function for
1/2/4bpp support if necessary. The file util.h has been modified to
reflect this decision.
The changes to raw_data_format_adjust() is based on an abandoned patch
by Gert Menke (submitted March 14, 2017), credit to them for that
change and the addition of *bpp to bmp_get_info().
Signed-off-by: Joseph S. Pacheco-Corwin <hammersamatom@gmail.com>
Kevin O'Connor [Mon, 17 Dec 2018 15:23:49 +0000 (10:23 -0500)]
output: Avoid thunking to 16bit mode in printf() if no vgabios
It is not necessary to call the vgabios if no vgabios has been
installed. This reduces the amount of hardware accesses on qemu when
the bios is not initializing the display hardware, and it can reduce
the boot time by a couple of milliseconds.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
qemu: avoid debug prints if debugcon is not enabled
In order to speed up the boot phase, we can check the QEMU
debugcon device, and disable the writes if it is not recognized.
This patch allow us to save around 10 msec (time measured
between SeaBIOS entry point and "linuxboot" entry point)
when CONFIG_DEBUG_LEVEL=1 and debugcon is not enabled.
Signed-off-by: Stefano Garzarella <sgarzare@redhat.com> Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Liran Alon [Tue, 13 Nov 2018 15:53:40 +0000 (17:53 +0200)]
pvscsi: ring_desc do not have to be page aligned
In contrast to other allocations made by pvscsi_init_rings(),
ring_desc is only used internally by SeaBIOS (not passed to
device-controller) and there is not restriction which force
it to be page aligned.
Reviewed-by: Mark Kanda <mark.kanda@oracle.com> Signed-off-by: Liran Alon <liran.alon@oracle.com>
Shmuel Eiderman [Thu, 1 Nov 2018 15:14:42 +0000 (17:14 +0200)]
pvscsi: Scan all 64 possible targets
The max number of targets per PVSCSI controller is 64, not 7.
This can easily be seen in QEMU PVSCSI emulation code
(hw/scsi/vmw_pvscsi.c) as PVSCSI_MAX_DEVS, which defines the
number of targets, have value of 64.
Fixes: 83d60b3c474b ("Add pvscsi boot support") Reviewed-by: Liran Alon <liran.alon@oracle.com> Reviewed-by: Mark Kanda <mark.kanda@oracle.com> Signed-off-by: Shmuel Eiderman <shmuel.eiderman@oracle.com>
Matt DeVillier [Tue, 11 Sep 2018 21:54:53 +0000 (16:54 -0500)]
SeaVGABios/cbvga: Fix bpp for coreboot framebuffer
Commit 4b42cc4 [SeaVGABios/cbvga: Advertise correct pixel format] neglected
to wrap the cbfb mask size components in GET_FARVAR(), which resulted in a
bogus value for bpp, breaking output on most/all devices. Fix this by
adding GET_FARVAR() as appropriate.
Additionally, some newer ChromeOS devices still fail even with this fix,
so fall back to using the coreboot reported bit depth if the calculated
valid is invalid.
TEST: build/boot a variety of devices (google/[reef,eve], purism/librem_skl)
using coreboot framebuffer init, verify SeaBIOS boot menu prompt visible.
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Enable the firmware recognizing RedHat legacy PCI bridge device ID,
so QEMU can reserve additional PCI bridge resource capability.
Change the debug level lower to 3 when it is non-QEMU bridge.
Matt DeVillier [Tue, 21 Aug 2018 15:00:53 +0000 (10:00 -0500)]
nvme: fix I/O queue length calculation overflow
Commit cd47172 changed the I/O queue length calculation to use the
Maximum Queue Entries Supported (MQES) value from the capabilities
register, plus one, with a maximum value of NVME_PAGE_SIZE.
An unintended effect from this is that due to length being an unsigned
16-bit int, a MQES value of 0xFFFF yields a length of zero, resulting
in the queue allocation failing. Fix this by changing length to a u32.
TEST: build/boot on a Purism Librem13v2 with a MyDigitalSSD BPX NVMe
drive, which reports a MQES of 0xFFFF. Verify NVMe drive present in
boot menu and OS boots successfully.
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Kevin O'Connor [Sun, 15 Jul 2018 14:05:14 +0000 (10:05 -0400)]
ssdt: Fix building of legacy acpi tables on current iasl compiler
Recent versions of the iasl compiler raise an error if the table id is
longer than 8 characters. Older versions of iasl would silently
truncate the table id to 8 characters. Change the ssdt-misc and
ssdt-pcihp files to use an 8 character id - this should not directly
impact the generated aml code as the table id was already being
truncated - but may help those wishing to manually compile the tables.
Reported by Michael Tokarev, Vivia Nikolaidou, and several others.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Gerd Hoffmann [Wed, 15 Nov 2017 13:43:10 +0000 (14:43 +0100)]
qemu: add qemu ramfb support
Add support for qemu ramfb. This is a simple boot framebuffer device,
with normal ram being used to back the framebuffer and fw_cfg being used
to configure the device.
Use case (on x86): boot display for vgpu devices (which neither emulate
vga nor have a vgabios).
Sharing fw_cfg code with seabios turned out to be difficuilt due to
various dependencies the code has on infrastructure which only seabios
has. So include a copy of the code here, with those dependencies
removed and also stripped down because we don't need a non-dma fallback
here.
Gerd Hoffmann [Wed, 15 Nov 2017 13:43:10 +0000 (14:43 +0100)]
qemu: add bochs-display support
Use coreboot text mode emulation to also support the qemu bochs-display
device. This is a new display device supporting simple linear
framebuffers, using the bochs register interface. No support for legacy
vga (text modes, planar modes, cga modes, 8bpp palette modes all
dropped). The bochs interface is compatible with the qemu stdvga.
Stefan Berger [Mon, 19 Mar 2018 16:00:29 +0000 (12:00 -0400)]
tpm: when CRB is active, select, lock it, and check addresses
Do not just indicate that the probing for the CRB interface was successful
if we find it active. Instead, select it, lock it, and test the addresses
for whether they can be used (must be 32 bit).
Signed-off-by: Stefan Berger <stefanb@linux.vnet.ibm.com>
Stephen Douthit [Tue, 27 Feb 2018 19:17:11 +0000 (14:17 -0500)]
tpm: Handle unimplemented TIS_REG_IFACE_ID in tis_get_tpm_version()
If a device reports 0xf in the InterfaceType field of the TPM_INTERFACE_ID,
then the rest of the fields are invalid, and the InterfaceVersion field of
the TPM_INTF_CAPABILITY register must be checked instead.
Signed-off-by: Stephen Douthit <stephend@silicom-usa.com> Tested-by: Stefan Berger <stefanb@linux.vnet.ibm.com> Reviewed-by: Stefan Berger <stefanb@linux.vnet.ibm.com>
Stephen Douthit [Tue, 27 Feb 2018 19:17:10 +0000 (14:17 -0500)]
tpm: Wait for interface startup when probing
This is based on wait_startup() from the Linux tpm_tis driver.
Signed-off-by: Stephen Douthit <stephend@silicom-usa.com> Tested-by: Stephen Douthit <stephend@silicom-usa.com> Reviewed-by: Stefan Berger <stefanb@linux.vnet.ibm.com>
Stephen Douthit [Tue, 27 Feb 2018 19:17:09 +0000 (14:17 -0500)]
tpm: Refactor duplicated wait code in tis_wait_sts() & crb_wait_reg()
Signed-off-by: Stephen Douthit <stephend@silicom-usa.com> Tested-by: Stephen Douthit <stephend@silicom-usa.com> Reviewed-by: Stefan Berger <stefanb@linux.vnet.ibm.com>
The CRB device was introduced with TPM 2.0 to be physical-bus agnostic
and defined in TCG PC Client Platform TPM Profile (PTP) Specification
Family “2.0” Level 00 Revision 01.03 v22
It seems to be required with Windows 10. It is also a simpler device
than FIFO/TIS.
This patch only support locality 0 since also the CRB device in QEMU
only supports this locality.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Stefan Berger <stefanb@linux.vnet.ibm.com> Tested-by: Stefan Berger <stefanb@linux.vnet.ibm.com>
Kevin O'Connor [Tue, 27 Feb 2018 16:27:59 +0000 (11:27 -0500)]
build: Use git describe --always
Add --always flag to "git describe" command to get a build identifier
even if one checks out the repo with a depth parameter that prunes out
the last tagged version.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Kevin O'Connor [Fri, 23 Feb 2018 01:29:27 +0000 (20:29 -0500)]
shadow: Don't invoke a shutdown on reboot unless in a reboot loop
Old versions of KVM would map the same writable copy of the BIOS at
both 0x000f0000 and 0xffff0000. As a result, a reboot on these
machines would result in a reboot loop. So, the code attempts to
check for that situation and invoke a shutdown instead.
Commit b837e68d changed the check to run prior to the first reboot.
However, this broke reboots on the QEMU isapc machine type. Change
the reboot loop check to only be invoked after at least one reboot has
been attempted.
Reported-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Nikolay Nikolov [Sat, 10 Feb 2018 11:52:17 +0000 (13:52 +0200)]
floppy: Send 4 sense interrupt commands during controller initialization
During initialization, real floppy controllers need 4 sense interrupt commands
to clear the interrupt status (this represents the transition from "not ready"
to "ready" for each of the four virtual floppy drives), instead of just one.
This is described in detail in section 7.4 - Drive Polling of the Intel 82077AA
datasheet.
Signed-off-by: Nikolay Nikolov <nickysn@users.sourceforge.net>
Nikolay Nikolov [Sat, 10 Feb 2018 11:52:16 +0000 (13:52 +0200)]
floppy: Wait for the floppy motor to reach a stable speed, after starting
When starting up the floppy motor, wait for a certain amount of time, so
that it can spin up and reach a stable speed. This delay is skipped, if the
motor was already running (which can happen, since the floppy motor is
intentionally kept spinning for 2 seconds after the previous floppy
operation completes).
Signed-off-by: Nikolay Nikolov <nickysn@users.sourceforge.net>
Nikolay Nikolov [Sun, 4 Feb 2018 15:27:01 +0000 (17:27 +0200)]
floppy: Use timer_check() in floppy_wait_irq()
Use timer_check() instead of using floppy_motor_counter in BDA for the
timeout check in floppy_wait_irq().
The problem with using floppy_motor_counter was that, after it reaches
0, it immediately stops the floppy motors, which is not what is
supposed to happen on real hardware. Instead, after a timeout (like in
the end of every floppy operation, regardless of the result - success,
timeout or error), the floppy motors must be kept spinning for
additional 2 seconds (the FLOPPY_MOTOR_TICKS). So, now the
floppy_motor_counter is initialized to 255 (the max value) in the
beginning of the floppy operation. For IRQ timeouts, a different
timeout is used, specified by the new FLOPPY_IRQ_TIMEOUT constant
(currently set to 5 seconds - a fairly conservative value, but should
work reliably on most floppies).
After the floppy operation, floppy_drive_pio() resets the
floppy_motor_counter to 2 seconds (FLOPPY_MOTOR_TICKS).
This is also consistent with what other PC BIOSes do.
Signed-off-by: Nikolay Nikolov <nickysn@users.sourceforge.net>
Nikolay Nikolov [Sun, 4 Feb 2018 15:26:59 +0000 (17:26 +0200)]
floppy: Preserve motor and drive sel bits when resetting the floppy controller
In case of read or write errors, the floppy system is usually reset and the
operation is retried. In that case, the floppy motor state must be preserved
in order to avoid creating jitter and keep the floppy motor spinning smoothly
at a constant speed. Additionally, the drive select bits should probably also
be preserved, because some systems might need a small delay after selecting a
new drive. In that case, the operation would be retried, without changing
the currently selected drive.
In floppy_enable_controller(), the IRQ bit is now enabled first, before the
reset bit is set. I'm not completely sure whether this is necessary. It is
done just in case some hardware introduces a delay between setting this bit
and actually enabling the IRQ, which would cause us to miss the IRQ, sent by
the controller immediately after reset.
Signed-off-by: Nikolay Nikolov <nickysn@users.sourceforge.net>
Marcel Apfelbaum [Thu, 11 Jan 2018 20:15:12 +0000 (22:15 +0200)]
pci: fix 'io hints' capability for RedHat PCI bridges
Commit ec6cb17f (pci: enable RedHat PCI bridges to reserve additional
resources on PCI init)
added a new vendor specific PCI capability for RedHat PCI bridges
allowing them to reserve additional buses and/or IO/MEM space.
When adding the IO hints PCI capability to the pcie-root-port
without specifying a value for bus reservation, the subordinate bus
computation is wrong and the guest kernel gets messed up.
Fix it by returning to prev code if the value for bus
reservation is not set.
Removed also a wrong debug print "PCI: invalid QEMU resource reserve
cap offset" which appears if the 'IO hints' capability is not present.
Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Marcel Apfelbaum <marcel@redhat.com>
Stefan Berger [Tue, 14 Nov 2017 20:03:47 +0000 (15:03 -0500)]
tpm: Add support for TPM2 ACPI table
Add support for the TPM2 ACPI table. If we find it and its
of the appropriate size, we can get the log_area_start_address
and log_area_minimum_size from it.
Kevin O'Connor [Thu, 2 Nov 2017 15:21:14 +0000 (11:21 -0400)]
timer: Avoid integer overflows in usec and nsec calculations
When timer_calc_usec() is used with large timeout values, such as 60s,
the integer math can overflow and produce different results than when
using timer_calc(time / 1000) for the same timeout.
Signed-off-by: Stefan Berger <stefanb@linux.vnet.ibm.com> Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Filippo Sironi [Wed, 11 Oct 2017 22:42:34 +0000 (00:42 +0200)]
nvme: Use the Maximum Queue Entries Supported (MQES) to initialize I/O queues
Use the Maximum Queue Entries Supported (MQES) to initialize I/O queues
depth rather than picking a fixed number (256) which might not be
supported by some NVMe controllers (the NVMe specification says that an
NVMe controller may support any number between 2 to 4096).
Still cap the I/O queues depth to 256 since, during my testing, SeaBIOS
was running out of memory when using something higher than 256 (4096 on
the NVMe controller that I've had a chance to try).
Kevin O'Connor [Tue, 3 Oct 2017 15:29:12 +0000 (11:29 -0400)]
xhci: Verify the device is still present in xhci_cmd_submit()
Make sure the USB device is still present before altering the xhci
"slot" for it. It appears some controllers will hang if a request is
sent to a port no longer connected.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
If the allocation of I/O queues ran out of memory, the code would fail to detect
that and happily use these queues at address zero. For me this happens for
systems with more than 7 NVMe controllers.
Fix the out of memory handling to gracefully handle this case.
Kevin O'Connor [Tue, 3 Oct 2017 14:45:24 +0000 (10:45 -0400)]
xhci: Build TRBs directly in xhci_trb_queue()
Use the logic for building a 'struct xhci_trb' that was in
xhci_xfer_queue() up so that command and ring TRBs can also use that
functionality. This eliminates the need to manually generate the
xhci_trb struct from those code paths.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Redirect int10 calls to serial console output.
Parse serial input and queue key events.
The serial console can work both as primary display
and in parallel to another vga display (splitmode).
kbd: make enqueue_key public, add ascii_to_keycode
serial console wants queue key events and needs to map ascii chars to
the keycode, so make enqueue_key public and also exports a helper
function so sercon can use the scan_to_keycode mapping table.
pci: enable RedHat PCI bridges to reserve additional resources on PCI init
In case of Red Hat Generic PCIE Root Port reserve additional buses
and/or IO/MEM/PREF space, which values are provided in a vendor-specific capability.
Signed-off-by: Aleksandr Bezzubikov <zuban32s@gmail.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
On PCI init PCI bridge devices may need some
extra info about bus number to reserve, IO, memory and
prefetchable memory limits. QEMU can provide this
with special vendor-specific PCI capability.
This capability is intended to be used only
for Red Hat PCI bridges, i.e. QEMU cooperation.
Signed-off-by: Aleksandr Bezzubikov <zuban32s@gmail.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
projects / seabios.git / log