Frank Chang [Fri, 10 Dec 2021 07:57:03 +0000 (15:57 +0800)]
target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions
SEW has the limitation which cannot exceed ELEN.
Widening instructions have a destination group with EEW = 2*SEW
and narrowing instructions have a source operand with EEW = 2*SEW.
Both of the instructions have the limitation of: 2*SEW <= ELEN.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-78-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions is
moved to Section 11.4 in RVV v1.0 spec. Update the comment, no
functional changes.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-77-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:57:01 +0000 (15:57 +0800)]
target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-76-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-75-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:59 +0000 (15:56 +0800)]
target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()
Add supports of Vector unit-stride mask load/store instructions
(vlm.v, vsm.v), which has:
evl (effective vector length) = ceil(env->vl / 8).
The new instructions operate the same as unmasked byte loads and stores.
Add evl parameter to reuse vext_ldst_us().
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-74-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:58 +0000 (15:56 +0800)]
target/riscv: rvv-1.0: add vsetivli instruction
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-73-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:57 +0000 (15:56 +0800)]
target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
Rename r2_zimm to r2_zimm11 for the upcoming vsetivli instruction.
vsetivli has 10-bits of zimm but vsetvli has 11-bits of zimm.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-72-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Implement the floating-point reciprocal estimate to 7 bits instruction.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-71-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Implement the floating-point reciprocal square-root estimate to 7 bits
instruction.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-70-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Hsiangkai Wang [Fri, 10 Dec 2021 07:56:54 +0000 (15:56 +0800)]
target/riscv: gdb: support vector registers for rv64 & rv32
Signed-off-by: Hsiangkai Wang <kai.wang@sifive.com> Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-69-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:53 +0000 (15:56 +0800)]
target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid
If the frm field contains an invalid rounding mode (101-111),
attempting to execute any vector floating-point instruction, even
those that do not depend on the rounding mode, will raise an illegal
instruction exception.
Call gen_set_rm() with DYN rounding mode to check and trigger illegal
instruction exception if frm field contains invalid value at run-time
for vector floating-point instructions.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-68-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:52 +0000 (15:56 +0800)]
target/riscv: rvv-1.0: implement vstart CSR
* Update and check vstart value for vector instructions.
* Add whole register move instruction helper functions as we have to
call helper function for case where vstart is not zero.
* Remove probe_pages() calls in vector load/store instructions
(except fault-only-first loads) to raise the memory access exception
at the exact processed vector element.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-67-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:51 +0000 (15:56 +0800)]
target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-66-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-65-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:49 +0000 (15:56 +0800)]
target/riscv: add "set round to odd" rounding mode helper function
helper_set_rounding_mode() is responsible for SIGILL, and "round to odd"
should be an interface private to translation, so add a new independent
helper_set_rod_rounding_mode().
Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-64-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Also adjust GEN_OPFV_WIDEN_TRANS() to accept multiple floating-point
rounding modes.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-63-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Also adjust GEN_OPFV_TRANS() to accept multiple floating-point rounding
modes.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-62-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-61-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-60-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-59-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:43 +0000 (15:56 +0800)]
target/riscv: rvv-1.0: remove vmford.vv and vmford.vf
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-58-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-57-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-56-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-55-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-54-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-53-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-52-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:36 +0000 (15:56 +0800)]
target/riscv: rvv-1.0: slide instructions
* Remove clear function from helper functions as the tail elements
are unchanged in RVV 1.0.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-51-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-50-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-49-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* Sign-extend vmselu.vi and vmsgtu.vi immediate values.
* Remove "set tail elements to zeros" as tail elements can be unchanged
for either VTA to have undisturbed or agnostic setting.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-48-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:32 +0000 (15:56 +0800)]
target/riscv: rvv-1.0: single-width saturating add and subtract instructions
Sign-extend vsaddu.vi immediate value.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-47-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-46-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:30 +0000 (15:56 +0800)]
target/riscv: rvv-1.0: narrowing integer right shift instructions
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-45-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
* Only do carry-in or borrow-in if is masked (vm=0).
* Remove clear function from helper functions as the tail elements
are unchanged in RVV 1.0.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-44-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:28 +0000 (15:56 +0800)]
target/riscv: rvv-1.0: single-width bit shift instructions
Truncate vsll.vi, vsrl.vi, vsra.vi's immediate values to lg2(SEW) bits.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-43-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:27 +0000 (15:56 +0800)]
target/riscv: rvv-1.0: single-width averaging add and subtract instructions
Add the following instructions:
* vaaddu.vv
* vaaddu.vx
* vasubu.vv
* vasubu.vx
Remove the following instructions:
* vadd.vi
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-42-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211210075704.23951-41-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-40-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
NaN-boxed the scalar floating-point register based on RVV 1.0's rules.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-39-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
NaN-boxed the scalar floating-point register based on RVV 1.0's rules.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-38-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-37-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-36-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:20 +0000 (15:56 +0800)]
target/riscv: rvv-1.0: allow load element with sign-extended
For some vector instructions (e.g. vmv.s.x), the element is loaded with
sign-extended.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-35-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:19 +0000 (15:56 +0800)]
target/riscv: rvv-1.0: element index instruction
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-34-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:18 +0000 (15:56 +0800)]
target/riscv: rvv-1.0: iota instruction
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-33-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:17 +0000 (15:56 +0800)]
target/riscv: rvv-1.0: set-X-first mask bit instructions
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-32-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:16 +0000 (15:56 +0800)]
target/riscv: rvv-1.0: find-first-set mask bit instruction
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-31-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:15 +0000 (15:56 +0800)]
target/riscv: rvv-1.0: count population in mask instruction
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-30-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-29-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-28-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:12 +0000 (15:56 +0800)]
target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation
Update vext_get_vlmax() and MAXSZ() to take fractional LMUL into
calculation for RVV 1.0.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-27-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:11 +0000 (15:56 +0800)]
target/riscv: rvv-1.0: update vext_max_elems() for load/store insns
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-26-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-25-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:09 +0000 (15:56 +0800)]
target/riscv: rvv-1.0: fault-only-first unit stride load
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-24-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:08 +0000 (15:56 +0800)]
target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns
Replace ETYPE from signed int to unsigned int to prevent index overflow
issue, which would lead to wrong index address.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-23-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:07 +0000 (15:56 +0800)]
target/riscv: rvv-1.0: index load and store instructions
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-22-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:06 +0000 (15:56 +0800)]
target/riscv: rvv-1.0: stride load and store instructions
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-21-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:05 +0000 (15:56 +0800)]
target/riscv: rvv-1.0: configure instructions
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-20-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:04 +0000 (15:56 +0800)]
target/riscv: rvv-1.0: remove amo operations instructions
Vector AMOs are removed from standard vector extensions. Will be added
later as separate Zvamo extension, but will need a different encoding
from earlier proposal.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-19-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:03 +0000 (15:56 +0800)]
target/riscv: rvv:1.0: add translation-time nan-box helper function
* Add fp16 nan-box check generator function, if a 16-bit input is not
properly nanboxed, then the input is replaced with the default qnan.
* Add do_nanbox() helper function to utilize gen_check_nanbox_X() to
generate the NaN-boxed floating-point values based on SEW setting.
* Apply nanbox helper in opfvf_trans().
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-18-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:02 +0000 (15:56 +0800)]
target/riscv: introduce more imm value modes in translator functions
Immediate value in translator function is extended not only
zero-extended and sign-extended but with more modes to be applicable
with multiple formats of vector instructions.
* IMM_ZX: Zero-extended
* IMM_SX: Sign-extended
* IMM_TRUNC_SEW: Truncate to log(SEW) bit
* IMM_TRUNC_2SEW: Truncate to log(2*SEW) bit
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-17-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:01 +0000 (15:56 +0800)]
target/riscv: rvv-1.0: update check functions
Update check functions with RVV 1.0 rules.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-16-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:56:00 +0000 (15:56 +0800)]
target/riscv: rvv-1.0: add VMA and VTA
Introduce vma and vta fields in vtype register.
According to RVV 1.0 spec (section 3.3.3):
When a set is marked agnostic, the corresponding set of destination
elements in any vector or mask destination operand can either retain
the value they previously held, or are overwritten with 1s.
So, either vta/vma is set to undisturbed or agnostic, it's legal to
retain the inactive masked-off elements and tail elements' original
values unchanged. Therefore, besides declaring vta/vma fields in vtype
register, also remove all the tail elements clean functions in this
commit.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-15-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:55:59 +0000 (15:55 +0800)]
target/riscv: rvv-1.0: add fractional LMUL
Introduce the concepts of fractional LMUL for RVV 1.0.
In RVV 1.0, LMUL bits are contiguous in vtype register.
Also rearrange rvv bits in TB_FLAGS to skip MSTATUS_VS (0x600)
and MSTATUS_FS (0x6000) bits.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-14-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:55:58 +0000 (15:55 +0800)]
target/riscv: rvv-1.0: remove MLEN calculations
As in RVV 1.0 design, MLEN is hardcoded with value 1 (Section 4.5).
Thus, remove all MLEN related calculations.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-13-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:55:57 +0000 (15:55 +0800)]
target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers
If VS field is off, accessing vector csr registers should raise an
illegal-instruction exception.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-12-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Greentime Hu [Fri, 10 Dec 2021 07:55:56 +0000 (15:55 +0800)]
target/riscv: rvv-1.0: add vlenb register
Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-11-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
LIU Zhiwei [Fri, 10 Dec 2021 07:55:55 +0000 (15:55 +0800)]
target/riscv: rvv-1.0: add vcsr register
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-10-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:55:54 +0000 (15:55 +0800)]
target/riscv: rvv-1.0: remove rvv related codes from fcsr registers
* Remove VXRM and VXSAT fields from FCSR register as they are only
presented in VCSR register.
* Remove RVV loose check in fs() predicate function.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-9-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:55:53 +0000 (15:55 +0800)]
target/riscv: rvv-1.0: add translation-time vector context status
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-8-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:55:52 +0000 (15:55 +0800)]
target/riscv: rvv-1.0: introduce writable misa.v field
Implementations may have a writable misa.v field. Analogous to the way
in which the floating-point unit is handled, the mstatus.vs field may
exist even if misa.v is clear.
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-7-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
LIU Zhiwei [Fri, 10 Dec 2021 07:55:51 +0000 (15:55 +0800)]
target/riscv: rvv-1.0: add sstatus VS field
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-6-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:55:50 +0000 (15:55 +0800)]
target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-5-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
LIU Zhiwei [Fri, 10 Dec 2021 07:55:49 +0000 (15:55 +0800)]
target/riscv: rvv-1.0: add mstatus VS field
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-4-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:55:48 +0000 (15:55 +0800)]
target/riscv: Use FIELD_EX32() to extract wd field
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-3-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:55:47 +0000 (15:55 +0800)]
target/riscv: drop vector 0.7.1 and add 1.0 support
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20211210075704.23951-2-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:43:27 +0000 (15:43 +0800)]
target/riscv: zfh: add Zfhmin cpu property
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211210074329.5775-9-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:43:26 +0000 (15:43 +0800)]
target/riscv: zfh: implement zfhmin extension
Zfhmin extension is a subset of Zfh extension, consisting only of data
transfer and conversion instructions.
If enabled, only the following instructions from Zfh extension are
included:
* flh, fsh, fmv.x.h, fmv.h.x, fcvt.s.h, fcvt.h.s
* If D extension is present: fcvt.d.h, fcvt.h.d
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211210074329.5775-8-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Frank Chang [Fri, 10 Dec 2021 07:43:25 +0000 (15:43 +0800)]
target/riscv: zfh: add Zfh cpu property
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211210074329.5775-7-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* configure and meson cleanups and fixes
* remove unnecessary #ifdef
* SCSI and i386 fixes
# gpg: Signature made Sat 18 Dec 2021 02:00:22 AM PST
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [unknown]
# gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu:
hw/i386/vmmouse: Require 'i8042' property to be set
tests/qtest/fuzz-megasas-test: Add test for GitLab issue #521
hw/scsi/megasas: Fails command if SGL buffer overflows
hw/scsi: Fix scsi_bus_init_named() docstring
meson: add "check" argument to run_command
cpu: remove unnecessary #ifdef CONFIG_TCG
meson: reenable test-fdmon-epoll
configure: remove DIRS
configure: remove unnecessary symlinks
configure, meson: move ARCH to meson.build
meson: rename "arch" variable
configure: unify x86_64 and x32
configure: unify ppc64 and ppc64le
configure: unify two case statements on $cpu
configure: move target detection before CPU detection
configure: make $targetos lowercase, use windows instead of MINGW32
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
hw/i386/vmmouse: Require 'i8042' property to be set
If the 'i8042' property is not set, mouse events handled by
vmmouse_mouse_event() end calling i8042_isa_mouse_fake_event()
with a NULL argument, resulting in ps2_mouse_fake_event() being
called with invalid PS2MouseState pointer. Fix by requiring
the 'i8042' property to be always set:
$ qemu-system-x86_64 -device vmmouse
qemu-system-x86_64: -device vmmouse: 'i8042' link is not set
Fixes: 91c9e09147b ("vmmouse: convert to qdev") Reported-by: Calvin Buckley <calvin@cmpct.info>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/752 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211201223253.36080-1-f4bug@amsat.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
tests/qtest/fuzz-megasas-test: Add test for GitLab issue #521
Without the previous commit, this test triggers:
$ make check-qtest-x86_64
[...]
Running test qtest-x86_64/fuzz-megasas-test
qemu-system-x86_64: softmmu/physmem.c:3229: address_space_unmap: Assertion `mr != NULL' failed.
Broken pipe
ERROR qtest-x86_64/fuzz-megasas-test - too few tests run (expected 2, got 1)
Suggested-by: Alexander Bulekov <alxndr@bu.edu> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Darren Kenny <darren.kenny@oracle.com>
Message-Id: <20211119201141.532377-3-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
hw/scsi/megasas: Fails command if SGL buffer overflows
If we detect an overflow on the SGL buffer, do not
keep processing the command: discard it. TARGET_FAILURE
sense code will be returned (MFI_STAT_SCSI_DONE_WITH_ERROR).
Reported-by: Alexander Bulekov <alxndr@bu.edu>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/521 Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Darren Kenny <darren.kenny@oracle.com>
Message-Id: <20211119201141.532377-2-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit 739e95f5741 ("scsi: Replace scsi_bus_new() with
scsi_bus_init(), scsi_bus_init_named()") forgot to rename
scsi_bus_init() in the function documentation string.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211122104744.1051554-1-f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Fri, 8 Oct 2021 11:33:08 +0000 (13:33 +0200)]
cpu: remove unnecessary #ifdef CONFIG_TCG
"if (tcg_enabled())" allows elision of the code inside it; we only need
the prototype to exist, so that the code compile even for the --disable-tcg
case.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Wed, 13 Oct 2021 11:56:24 +0000 (13:56 +0200)]
configure: remove DIRS
DIRS is used to create the directory in which the LINKS symbolic links
reside, or to create directories for object files. The former can
be done directly in the symlinking loop, while the latter is done
by Meson already, so DIRS is not necessary.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Mon, 8 Nov 2021 14:44:39 +0000 (15:44 +0100)]
meson: rename "arch" variable
Avoid confusion between the ARCH variable of configure/config-host.mak
and the same-named variable of meson.build.
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Tue, 9 Nov 2021 08:36:10 +0000 (09:36 +0100)]
configure: unify x86_64 and x32
The only difference between the two, as far as either configure or
Meson are concerned, is in the multilib flags passed to the compiler.
For QEMU, this fixes the handling of TYPE_OLDDEVT in
include/exec/user/thunk.h and enables testing of dirty ring buffer,
because both are using HOST_X86_64.
For tests/tcg, this means that on a hypothetical x32 host the
cross compiler will not be used to build the tests.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Tue, 9 Nov 2021 08:18:20 +0000 (09:18 +0100)]
configure: unify ppc64 and ppc64le
The only difference between the two, as far as either configure or
Meson are concerned, is the default endianness of the compiler.
For tests/tcg, specify the endianness explicitly on the command line;
for configure, do the same so that it is possible to have --cpu=ppc64le
on a bigendian system or vice versa. Apart from this, cpu=ppc64le can
be normalized to ppc64 also in configure and not just in the meson
cross file.
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
projects / qemu-xen.git / log