Tom St Denis [Wed, 7 Sep 2022 14:18:01 +0000 (10:18 -0400)]
drm/amd/amdgpu: Add missing CGTS*TCC_DISABLE to 10.3 headers
The TCC_DISABLE registers were not included in the 10.3 headers and
instead just placed directly in the gfx_v10_0.c source. This patch
adds them to the headers so tools like umr can scan them and support them.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: correct doorbell range/size value for CSDMA_DOORBELL_RANGE
current function mixes CSDMA_DOORBELL_RANGE and SDMA0_DOORBELL_RANGE
range/size manipulation, while these 2 registers have difference size
field mask. Remove range/size manipulation for SDMA0_DOORBELL_RANGE.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Xiaojian Du <Xiaojian.Du@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: fix memory leak when using debugfs_lookup()
When calling debugfs_lookup() the result must have dput() called on it,
otherwise the memory will leak over time. Fix this up by properly
calling dput().
Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Wayne Lin <Wayne.Lin@amd.com> Cc: hersen wu <hersenxs.wu@amd.com> Cc: Wenjing Liu <wenjing.liu@amd.com> Cc: Patrik Jakobsson <patrik.r.jakobsson@gmail.com> Cc: Thelford Williams <tdwilliamsiv@gmail.com> Cc: Fangzhi Zuo <Jerry.Zuo@amd.com> Cc: Yongzhi Liu <lyz_cs@pku.edu.cn> Cc: Mikita Lipski <mikita.lipski@amd.com> Cc: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Cc: Bhanuprakash Modem <bhanuprakash.modem@intel.com> Cc: Sean Paul <seanpaul@chromium.org> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Cc: stable@vger.kernel.org Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
YiPeng Chai [Thu, 18 Aug 2022 08:46:59 +0000 (16:46 +0800)]
drm/amdgpu: TA unload messages are not actually sent to psp when amdgpu is uninstalled
V1:
The psp_cmd_submit_buf function is called by psp_hw_fini to send
TA unload messages to psp to terminate ras, asd and tmr. But when
amdgpu is uninstalled, drm_dev_unplug is called earlier than
psp_hw_fini in amdgpu_pci_remove, the calling order as follows:
static void amdgpu_pci_remove(struct pci_dev *pdev) {
drm_dev_unplug
......
amdgpu_driver_unload_kms->amdgpu_device_fini_hw->...
->.hw_fini->psp_hw_fini->...
->psp_ta_unload->psp_cmd_submit_buf
......
}
The program will return when calling drm_dev_enter in psp_cmd_submit_buf.
So the call to drm_dev_enter in psp_cmd_submit_buf should be
removed, so that the TA unload messages can be sent to the psp
when amdgpu is uninstalled.
V2:
1. Restore psp_cmd_submit_buf to its original code.
2. Move drm_dev_unplug call after amdgpu_driver_unload_kms in
amdgpu_pci_remove.
3. Since amdgpu_device_fini_hw is called by amdgpu_driver_unload_kms,
remove the unplug check to release device mmio resource in
amdgpu_device_fini_hw before calling drm_dev_unplug.
Hamza Mahfooz [Thu, 1 Sep 2022 14:15:10 +0000 (10:15 -0400)]
drm/amd/display: fix indentation in commit_planes_for_stream()
Address the following warning:
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:3508:9: warning: this ‘if’ clause does not guard... [-Wmisleading-indentation]
3508 | if (update_type != UPDATE_TYPE_FAST)
| ^~
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:3510:17: note: ...this statement, but the latter is misleadingly indented as if it were guarded by the ‘if’
3510 | if (update_type != UPDATE_TYPE_FAST)
| ^~
Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jane Jian [Mon, 22 Aug 2022 07:21:04 +0000 (15:21 +0800)]
drm/amdgpu/vcn: Add MMSCH v4_0 support for sriov
These structures are basically ported from MMSCH v3_0,
besides, added RB and RB4 enablement flag to support
unified queue
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jane Jian <Jane.Jian@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jane Jian [Mon, 22 Aug 2022 07:20:24 +0000 (15:20 +0800)]
drm/amdgpu/vcn: Add sriov VCN v4_0 unified queue support
Enable unified queue support for sriov, abandon all previous
multi-queue settings
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jane Jian <Jane.Jian@amd.com> Reviewed-by: Ruijing Dong <ruijing.dong@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jane Jian [Mon, 22 Aug 2022 07:19:11 +0000 (15:19 +0800)]
drm/amdgpu/vcn: Add vcn/vcn1 in white list to load its firmware under sriov
Previously since vcn0/vcn1 are not enabled, loading firmware
is skipped. Now add firmware loading back since vcn0/vcn1
has already been enabled on sriov
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jane Jian <Jane.Jian@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jane Jian [Mon, 22 Aug 2022 07:15:32 +0000 (15:15 +0800)]
drm/amdgpu/vcn: Disable CG/PG for SRIOV
For sriov, CG and MG are controlled from hypervisor side,
no need to manage them again in ip init
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Jane Jian <Jane.Jian@amd.com> Reviewed-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yifan Zha [Fri, 19 Aug 2022 03:02:19 +0000 (11:02 +0800)]
drm/admgpu: Skip CG/PG on SOC21 under SRIOV VF
[Why]
There is no CG(Clock Gating)/PG(Power Gating) requirement on SRIOV VF.
For multi VF, VF should not enable any CG/PG features.
For one VF, PF will program CG/PG related registers.
[How]
Do not set any cg/pg flag bit at early init under sriov.
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Yifan Zha <Yifan.Zha@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yifan Zha [Wed, 17 Aug 2022 09:25:15 +0000 (17:25 +0800)]
drm/amdgpu: Use RLCG to program GRBM_GFX_CNTL during full access time
[Why]
KIQ register init requires GRBM_GFX_CNTL to select KIQ.
[How]
As RLCG accessing registers will save the data of GRBM_GFX_CNTL and restore it.
Use RLCG indirect accessing register method to select grbm instead of mmio directly access.
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Yifan Zha <Yifan.Zha@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yifan Zha [Mon, 1 Aug 2022 03:11:20 +0000 (11:11 +0800)]
drm/amdgpu: skip "Issue additional private vm invalidation to MMHUB" on SRIOV
[Why]
vm_l2_bank_select_reserved_cid2 is a PF_only register
that cannot be programmed by VF. This feature is only
support HDP using GPUVM page tables to access FB memory
which should be disabled on SRIOV.
[How]
Disable the feature on VF.
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Yifan Zha <Yifan.Zha@amd.com> Signed-off-by: Horace Chen <horace.chen@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
SR-IOV may need to load different firmwares for different ASIC inside
VF.
So create a new function in amdgpu_virt to check whether FW load needs
to be skipped.
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Horace Chen <horace.chen@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: enable WPTR_POLL_ENABLE for sriov on sdma_v6_0
[Why]
Under SR-IOV, if VF is switched out then its doorbell will be disabled,
SDMA rely on WPTR_POLL to get doorbells which was sent during VF
switched-out time.
[How]
For SR-IOV, set SDMA WPTR_POLL_ENABLE to 1.
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Horace Chen <horace.chen@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Under SR-IOV, we are not sure whether pipe status is
good or not when doing initialization. The compute engine
maybe fail to bringup if pipe status is bad.
[How]
Do an RS64 pipe reset for MEC before we do initialization.
Also apply to bare-metal.
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Horace Chen <horace.chen@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
under SR-IOV, the nbio doorbell range will be defined by PF. So VF
nbio doorbell range registers will be blocked. It will cause violation
if VF access those registers directly.
[How]
create an nbio_v4_3_sriov_funcs for sriov nbio_v4_3 initialization to
skip the setting for the doorbell range registers.
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Horace Chen <horace.chen@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yifan Zhang [Tue, 30 Aug 2022 15:18:47 +0000 (23:18 +0800)]
drm/amdgpu/mes: zero the sdma_hqd_mask of 2nd SDMA engine for SDMA 6.0.1
there is only one SDMA engine in SDMA 6.0.1, the sdma_hqd_mask has to be
zeroed for the 2nd engine, otherwise MES scheduler will consider 2nd
engine exists and map/unmap SDMA queues to the non-existent engine.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 30 Aug 2022 21:57:52 +0000 (17:57 -0400)]
drm/amd/display: fix documentation for amdgpu_dm_update_freesync_caps()
Document missing parameter.
Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Fixes: 8889a13f99e5 ("drm/amd/display: Add some extra kernel doc to amdgpu_dm") Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rodrigo Siqueira [Thu, 11 Aug 2022 15:48:19 +0000 (11:48 -0400)]
Documentation/gpu: Add Multiplane Overlay doc
Multiple plane overlay is a feature supported by AMD hardware, but it
has specific details that deserve proper documentation. This commit
introduces a documentation that describes some of the features,
limitations, and use cases for this feature. Part of this documentation
came from some discussion in the public upstream [1][2].
Cc: Harry Wentland <harry.wentland@amd.com> Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Cc: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Cc: Hersen Wu <hersenxs.wu@amd.com> Cc: Alex Hung <alex.hung@amd.com> Cc: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Cc: Simon Ser <contact@emersion.fr> Cc: Pekka Paalanen <pekka.paalanen@collabora.com> Cc: Sean Paul <seanpaul@chromium.org> Cc: Mark Yacoub <markyacoub@chromium.org> Cc: Leo Li <sunpeng.li@amd.com> Cc: Pierre-Loup <pgriffais@valvesoftware.com> Cc: Michel Dänzer <michel.daenzer@mailbox.org> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rodrigo Siqueira [Thu, 11 Aug 2022 15:48:18 +0000 (11:48 -0400)]
Documentation/gpu: Add an explanation about the DCN pipeline
In the DCN code, we constantly talk about hardware pipeline, pipeline,
or even just pipes, which is a concept that is not obvious to everyone.
For this reason, this commit expands the DCN overview explanation by
adding a new section that describes what a pipeline is from the DCN
perspective.
Changes since V1:
- Rewrite the first paragraph that describes AMD hardware pipeline.
Cc: Harry Wentland <harry.wentland@amd.com> Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Cc: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Cc: Hersen Wu <hersenxs.wu@amd.com> Cc: Alex Hung <alex.hung@amd.com> Cc: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: Simon Ser <contact@emersion.fr> Cc: Pekka Paalanen <pekka.paalanen@collabora.com> Cc: Sean Paul <seanpaul@chromium.org> Cc: Mark Yacoub <markyacoub@chromium.org> Cc: Pierre-Loup <pgriffais@valvesoftware.com> Cc: Michel Dänzer <michel.daenzer@mailbox.org> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rodrigo Siqueira [Thu, 11 Aug 2022 15:48:17 +0000 (11:48 -0400)]
Documentation/gpu: Add info table for ASICs
Amdgpu driver is used in an extensive range of devices, and each ASIC
has some specific configuration. As a result of this variety, sometimes
it is hard to identify the correct block that might cause the issue.
This commit expands the amdgpu kernel-doc to alleviate this issue by
introducing one ASIC table that describes dGPU and another one that
shares the APU info.
Cc: Harry Wentland <harry.wentland@amd.com> Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Cc: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Cc: Hersen Wu <hersenxs.wu@amd.com> Cc: Alex Hung <alex.hung@amd.com> Cc: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: Simon Ser <contact@emersion.fr> Cc: Pekka Paalanen <pekka.paalanen@collabora.com> Cc: Sean Paul <seanpaul@chromium.org> Cc: Mark Yacoub <markyacoub@chromium.org> Cc: Pierre-Loup <pgriffais@valvesoftware.com> Cc: Michel Dänzer <michel.daenzer@mailbox.org> Cc: Kent Russell <Kent.Russell@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 25 Aug 2022 21:04:22 +0000 (17:04 -0400)]
drm/amdgpu: add new ip block for MES 11.0.3
Add ip block support for mes v11_0_3.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 25 Aug 2022 21:02:47 +0000 (17:02 -0400)]
drm/amdgpu: add new ip block for GFX 11.0
Add ip block support for gfx v11_0_3.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 25 Aug 2022 21:05:24 +0000 (17:05 -0400)]
drm/amdgpu: Set GC family for GC 11.0.3
Set AMDGPU_FAMILY_GC_11_0_0.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: enable imu_rlc_ram programming for v11_0_3
All gc v11_0_3 registers in gcvml2 range have different
register offset from the ones in gc v11_0_0. v11_0_3
imu_rlc_ram programming has to be separated from v11_0_0
implementation
v2: fix checkpatch errors (Alex)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Yang Wang <KevinYang.Wang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
David Belanger [Tue, 26 Jul 2022 13:54:51 +0000 (09:54 -0400)]
drm/amdkfd: Added GFX 11.0.3 Support
Added missing cases for GFX 11.0.3 code in a few switch statements.
Signed-off-by: David Belanger <david.belanger@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 27 Jun 2022 16:33:14 +0000 (00:33 +0800)]
drm/amdgpu: init gfx config for gfx v11_0_3
initialize some gfx config for gfx v11_0_3
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 25 Aug 2022 20:57:57 +0000 (16:57 -0400)]
drm/amdgpu: declare firmware for new MES 11.0.3
To support new mes ip block
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 25 Aug 2022 20:56:52 +0000 (16:56 -0400)]
drm/amdgpu: declare firmware for new GC 11.0.3
To support new gfx ip block
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 25 Aug 2022 21:01:52 +0000 (17:01 -0400)]
drm/amdgpu: add new ip block for GMC 11.0
Add ip block support for gmc v11_0_3.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 27 Jun 2022 16:35:07 +0000 (00:35 +0800)]
drm/amdgpu: initialize gmc sw config for v11_0_3
initialize gmc sw config for v11_0_3
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yang Li [Mon, 29 Aug 2022 08:36:27 +0000 (16:36 +0800)]
drm/amd/display: clean up some inconsistent indentings
The indentation of statements in the same curly bracket should be
consistent.
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1892 Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yang Li [Mon, 29 Aug 2022 08:36:25 +0000 (16:36 +0800)]
drm/amd/display: clean up some inconsistent indentings
The indentation of statements in the same curly bracket should be
consistent.
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1886 Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 25 Aug 2022 21:06:21 +0000 (17:06 -0400)]
drm/amdgpu: add new ip block for LSDMA 6.0
Add ip block support for lsdma v6_0_3.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 25 Aug 2022 21:03:29 +0000 (17:03 -0400)]
drm/amdgpu: add new ip block for sdma 6.0
Add ip block support for sdma v6_0_3.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 25 Aug 2022 20:58:27 +0000 (16:58 -0400)]
drm/amdgpu: declare firmware for new SDMA 6.0.3
To support new sdma ip block
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yang Wang [Fri, 18 Mar 2022 12:05:32 +0000 (20:05 +0800)]
drm/amd/pm: add smu_v13_0_10 driver if version
add smu_v13_0_10 driver if version
Signed-off-by: Yang Wang <KevinYang.Wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yang Wang [Thu, 25 Aug 2022 21:13:05 +0000 (17:13 -0400)]
drm/amd/pm: add smu_v13_0_10 support
add smu_v13_0_10 support.
Signed-off-by: Yang Wang <KevinYang.Wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 25 Aug 2022 21:00:13 +0000 (17:00 -0400)]
drm/amdgpu: add new ip block for SOC21
Add ip block support for soc21_common.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Sonny Jiang [Thu, 4 Aug 2022 20:56:58 +0000 (16:56 -0400)]
drm/amdgpu: Enable pg/cg flags on GC11_0_3 for VCN
This enable VCN PG, CG, DPG and JPEG PG, CG
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 27 Jun 2022 16:41:52 +0000 (00:41 +0800)]
drm/amdgpu: initialize common sw config for v11_0_3
init cp/pg_flags and extenal_rev_id
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Martin Tsai [Thu, 18 Aug 2022 08:01:24 +0000 (16:01 +0800)]
drm/amd/display: Correct cursor position on horizontal mirror
[Why]
Incorrect cursor position will induce system hang on pipe split.
[How]
1.Handle horizontal mirror on rotation,
2.Correct cursor set on piep split.
Reviewed-by: Ariel Bernstein <Eric.Bernstein@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Martin Tsai <martin.tsai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Vladimir Stempen [Fri, 19 Aug 2022 22:32:01 +0000 (18:32 -0400)]
drm/amd/display: Fix black flash when switching from ODM2to1 to ODMBypass
[Why]
On secondary display hotplug we switch primary
stream from ODM2to1 to ODMBypass mode. Current
logic will trigger disabling front end for this
stream.
[How]
We need to check if prev_odm_pipe is equal to NULL
in order to disable dangling planes in this scenario.
Reviewed-by: Ariel Bernstein <Eric.Bernstein@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Vladimir Stempen <vladimir.stempen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[WHY]
Function wasn't returning false when it had a no stream
[HOW]
Made it return false when it had no stream.
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Ethan Wellenreiter <Ethan.Wellenreiter@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Re-initialize viewport after pipe merge
[Why]
Pipes get merged in preparation for SubVP but if they don't get used, and
are in ODM or some other multi pipe config, it would calculate the
voltage level with a viewport of just one pipe from when they were split
resulting in too low of a voltage level.
[How]
Made it so that the viewport and other timing settings get rebuilt and re-
initialized after the pipe merge, before calculating the voltage level so it
would calculate it correctly.
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Ethan Wellenreiter <Ethan.Wellenreiter@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Fri, 19 Aug 2022 19:11:19 +0000 (15:11 -0400)]
drm/amd/display: Use correct plane for CAB cursor size allocation
[Why&How]
plane and stream variables used for cursor size allocation calculation
were stale from previous iteration. Redo the iteration to find the
correct cursor plane for the calculation.
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Sierra [Thu, 25 Aug 2022 20:42:08 +0000 (15:42 -0500)]
drm/amdgpu: ensure no PCIe peer access for CPU XGMI iolinks
[Why] Devices with CPU XGMI iolink do not support PCIe peer access.
Signed-off-by: Alex Sierra <alex.sierra@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add visual confirm color support for SubVP
[Why && How]
We would like to have visual confirm color support for SubVP.
1. Set visual confirm color to red: SubVP is enable on this
display;
2. Set visual confirm color to green: SubVP is enable on
other display and DRR is on this display;
3. Set visual confirm color to blue: SubVP is enable on
other display and DRR is off on this display;
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Sat, 20 Aug 2022 13:04:06 +0000 (09:04 -0400)]
drm/amd/display: [FW Promotion] Release 0.0.132.0
- Fix comment to indicate correct visual confirm option
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ian Chen [Tue, 16 Aug 2022 07:47:02 +0000 (15:47 +0800)]
drm/amd/display: Add comments.
Reviewed-by: Dennis Chan <dennis.chan@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Ian Chen <ian.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Fri, 19 Aug 2022 17:11:30 +0000 (13:11 -0400)]
drm/amd/display: Revert "program k1/k2 divider for virtual signal for DCN32"
[Why & How]
This reverts commit e6cf22ef5fae493a99e162c3f2e7233448d2b970 since it
causes a SubVP related regression: "Switching between windowed video and
fullscreen can intermittently cause black screen"
Fixes: e6cf22ef5fae49 ("drm/amd/display: program k1/k2 divider for virtual signal for DCN32") Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[HOW&WHY]
EDP link detection must
be updated to support a primary EDP with a
link index of greater than 0.
* SWDEV-342936 - dc: DSC bringup for SAG 1.5
[WHY]
SmartAccess Graphics 1.5 (a.k.a SmartMux 1.5)
requires seamless switching between GPUs
with DSC enabled.
[HOW]
Moved DSC programming to
apply_single_control_ctx_to_hw before the stream
enablement logic to ensure the CRC checker provides valid
values for non-black frames
allowing the system to come out of forced PSR on
d2i.
Added additional logic to both generate a black
frame through setVisibility calls and keep track
of the CRCs values for this black frame when
coming out of forced PSR.
Updating logic for DalRegKey_DisableDSC to disable
DSC on EDP and all ports for systems.
[CLEANED]
dc: Moved DSC programming to before stream enablement
[HOW&WHY]
Moved DSC programming to
apply_single_control_ctx_to_hw before the stream
enablement logic.
Co-authored-by: sregolui <sregolui@amd.com> Reviewed-by: Jayendran Ramani <Jayendran.Ramani@amd.com> Reviewed-by: Harry Vanzylldejong <Harry.Vanzylldejong@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: sregolui <sregolui@amd.com> Signed-off-by: Iswara Nagulendran <Iswara.Nagulendran@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Charlene Liu [Fri, 19 Aug 2022 00:24:26 +0000 (20:24 -0400)]
drm/amd/display: fix wrong register access
[why]
fw version check was for release branch.
for staging, it has a chance to enter wrong code path.
Reviewed-by: Hansen Dsouza <hansen.dsouza@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Thu, 18 Aug 2022 21:55:01 +0000 (17:55 -0400)]
drm/amd/display: use actual cursor size instead of max for CAB allocation
[Why&How]
When calculating allocation for cursor size, get the real cursor through
the HUBP instead of using the maximum cursor size for more optimal
allocation
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Thu, 18 Aug 2022 16:34:06 +0000 (12:34 -0400)]
drm/amd/display: disable display fresh from MALL on an edge case for DCN321
[Why&How]
When using a 4k monitor when cursor caching is not supported due to
framebuffer being on an uncacheable address, enabling display refresh
from MALL would trigger corruption if SS is enabled.
Prevent entering SS if we are on the edge case and cursor caching is not
possible. Do this only if cursor size larger than a 64x64@4bpp. Pull the
cursor size calculation out of if condition since cursor address may not
be set on all platforms
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Thu, 18 Aug 2022 21:25:05 +0000 (17:25 -0400)]
drm/amd/display: Fix CAB cursor size allocation for DCN32/321
For calculating cursor size allocation, surface size was used, resulting
in over allocation
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Chen [Thu, 18 Aug 2022 17:21:37 +0000 (13:21 -0400)]
drm/amd/display: Missing HPO instance added
[Why & How]
Number of encoder is set to 4 but only 3 instances are created.
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Leo Chen <sancchen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ian Chen [Thu, 4 Aug 2022 07:44:27 +0000 (15:44 +0800)]
drm/amd/display: Refactor edp dsc codes.
Refactor edp dsc codes.
We split out edp dsc config from "global" to "per-panel" config settings.
Reviewed-by: Mike Hsieh <mike.hsieh@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Ian Chen <ian.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin Lee [Mon, 15 Aug 2022 17:12:42 +0000 (13:12 -0400)]
drm/amd/display: SubVP missing scaling case
[Description]
For SubVP scaling case we have to combine
the plane scaling and stream scaling.
Use UCLK dummy p-state WM for FCLK WM set C
[Description]
For DCN32/321 program dummy UCLK P-state watermark into FCLK
watermark set C register.
Reviewed-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add support for visual confirm color
[Why]
We want to get the visual confirm color of the bottom-most pipe
for test automation.
[How]
Save the visual confirm color to plane_state before program to MPC;
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Taimur Hassan [Thu, 18 Aug 2022 15:18:33 +0000 (11:18 -0400)]
drm/amd/display: Allow PHY state update between same states
[Why & How]
In some cases, there are calls to transition from TX_ON to TX_ON, such as
when using MST or during resolution change. This is expected, so allow HW
programming to continue.
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Gabe Teeger [Thu, 18 Aug 2022 02:25:01 +0000 (22:25 -0400)]
drm/amd/display: Cleanup PSR flag
[Why]
enable_sw_cntl_psr flag is not needed.
For PSR1 and PSR2, we should be passing
dirty rectangle and cursor updates to FW
regardless of enable_sw_cntl_psr flag.
[How]
Remove enable_sw_cntl_psr flag from driver.
Send cursor info and dirty rectagle status to
dmub only in the case of dcn31 and above.
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Robin Chen <robin.chen@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Gabe Teeger <gabe.teeger@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Gabe Teeger [Tue, 16 Aug 2022 02:52:46 +0000 (22:52 -0400)]
drm/amd/display: Cursor lag with PSR1 eDP
[Why]
On edp with psr1, we do not provide updates
of the cursor position regularly to firmware
like with PSR2. To send updates regularly,
the flag enable_sw_cntl_psr has to equal 1,
but cursor update should be provided
regularly to FW regardless of that flag.
[How]
Ensure that we always send cursor updates to
firmware when PSR version equals 1.
Reviewed-by: Robin Chen <robin.chen@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Gabe Teeger <gabe.teeger@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Michael Strauss [Wed, 17 Aug 2022 14:57:10 +0000 (10:57 -0400)]
drm/amd/display: Add DC debug option to force LTTPR mode
[WHY]
Useful for external teams debugging LTTPR issues
Reviewed-by: George Shen <George.Shen@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Chen [Wed, 17 Aug 2022 15:15:48 +0000 (11:15 -0400)]
drm/amd/display: add a override flag as wa for some specific dongle
[Why & How]
Add a override flag as wa for some specific dongle
Co-authored-by: Leo Chen <sancchen@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Leo Chen <SanChuan.Chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin Lee [Wed, 17 Aug 2022 14:47:59 +0000 (10:47 -0400)]
drm/amd/display: Only commit SubVP state after pipe programming
[Description]
We only want to commit the SubVP config to DMCUB
after the main and phantom pipe programming has
completed. Commiting the state early can cause
issues such as P-State being allowed by the HW
early which causes the SubVP state machine to
go into a bad state
Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Taimur Hassan [Tue, 16 Aug 2022 21:10:50 +0000 (17:10 -0400)]
drm/amd/display: Remove assert from PHY state update
[Why & How]
In some cases, there are calls to transition from TX_ON to TX_ON. This is
expected, so do not assert. However, these are redundant, so return
prematurely.
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Brian Chang <Brian.Chang@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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